Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 0626624566569fbb8e1d781ae1f6ff57267ee161 / . / drivers / pinctrl / renesas / pfc-r8a77980.c
blob: 59f4bdde2028f2340a5a0f61b70389af53a30f7a [file] [log] [blame]
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]22#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]23 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]24 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]25 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]27 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
28 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
29
30#define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
32 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
35 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
36 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
37 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
38 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]39 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
40 PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
41 PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]42
43/*
44 * F_() : just information
45 * FM() : macro for FN_xxx / xxx_MARK
46 */
47
48/* GPSR0 */
49#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
50#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
51#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
52#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
53#define GPSR0_17 F_(DU_DB7, IP2_7_4)
54#define GPSR0_16 F_(DU_DB6, IP2_3_0)
55#define GPSR0_15 F_(DU_DB5, IP1_31_28)
56#define GPSR0_14 F_(DU_DB4, IP1_27_24)
57#define GPSR0_13 F_(DU_DB3, IP1_23_20)
58#define GPSR0_12 F_(DU_DB2, IP1_19_16)
59#define GPSR0_11 F_(DU_DG7, IP1_15_12)
60#define GPSR0_10 F_(DU_DG6, IP1_11_8)
61#define GPSR0_9 F_(DU_DG5, IP1_7_4)
62#define GPSR0_8 F_(DU_DG4, IP1_3_0)
63#define GPSR0_7 F_(DU_DG3, IP0_31_28)
64#define GPSR0_6 F_(DU_DG2, IP0_27_24)
65#define GPSR0_5 F_(DU_DR7, IP0_23_20)
66#define GPSR0_4 F_(DU_DR6, IP0_19_16)
67#define GPSR0_3 F_(DU_DR5, IP0_15_12)
68#define GPSR0_2 F_(DU_DR4, IP0_11_8)
69#define GPSR0_1 F_(DU_DR3, IP0_7_4)
70#define GPSR0_0 F_(DU_DR2, IP0_3_0)
71
72/* GPSR1 */
73#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
74#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
75#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
76#define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
77#define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
78#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
79#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
80#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
81#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
82#define GPSR1_18 FM(AVB_LINK)
83#define GPSR1_17 FM(AVB_PHY_INT)
84#define GPSR1_16 FM(AVB_MAGIC)
85#define GPSR1_15 FM(AVB_MDC)
86#define GPSR1_14 FM(AVB_MDIO)
87#define GPSR1_13 FM(AVB_TXCREFCLK)
88#define GPSR1_12 FM(AVB_TD3)
89#define GPSR1_11 FM(AVB_TD2)
90#define GPSR1_10 FM(AVB_TD1)
91#define GPSR1_9 FM(AVB_TD0)
92#define GPSR1_8 FM(AVB_TXC)
93#define GPSR1_7 FM(AVB_TX_CTL)
94#define GPSR1_6 FM(AVB_RD3)
95#define GPSR1_5 FM(AVB_RD2)
96#define GPSR1_4 FM(AVB_RD1)
97#define GPSR1_3 FM(AVB_RD0)
98#define GPSR1_2 FM(AVB_RXC)
99#define GPSR1_1 FM(AVB_RX_CTL)
100#define GPSR1_0 F_(IRQ0, IP2_27_24)
101
102/* GPSR2 */
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]103#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]104#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
105#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
106#define GPSR2_26 F_(SDA3, IP10_7_4)
107#define GPSR2_25 F_(SCL3, IP10_3_0)
108#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
109#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
110#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
111#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
112#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
113#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
114#define GPSR2_18 F_(IRQ5, IP9_7_4)
115#define GPSR2_17 F_(IRQ4, IP9_3_0)
116#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
117#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
118#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
119#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
120#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
121#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
122#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
123#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
124#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
125#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
126#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
127#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
128#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
129#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
130#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
131#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
132#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
133
134/* GPSR3 */
135#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
136#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
137#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
138#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
139#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
140#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
141#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
142#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
143#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
144#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
145#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
146#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
147#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
148#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
149#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
150#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
151#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
152
153/* GPSR4 */
154#define GPSR4_24 FM(GETHER_LINK_A)
155#define GPSR4_23 FM(GETHER_PHY_INT_A)
156#define GPSR4_22 FM(GETHER_MAGIC)
157#define GPSR4_21 FM(GETHER_MDC_A)
158#define GPSR4_20 FM(GETHER_MDIO_A)
159#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
160#define GPSR4_18 FM(GETHER_TXCREFCLK)
161#define GPSR4_17 FM(GETHER_TD3)
162#define GPSR4_16 FM(GETHER_TD2)
163#define GPSR4_15 FM(GETHER_TD1)
164#define GPSR4_14 FM(GETHER_TD0)
165#define GPSR4_13 FM(GETHER_TXC)
166#define GPSR4_12 FM(GETHER_TX_CTL)
167#define GPSR4_11 FM(GETHER_RD3)
168#define GPSR4_10 FM(GETHER_RD2)
169#define GPSR4_9 FM(GETHER_RD1)
170#define GPSR4_8 FM(GETHER_RD0)
171#define GPSR4_7 FM(GETHER_RXC)
172#define GPSR4_6 FM(GETHER_RX_CTL)
173#define GPSR4_5 F_(SDA2, IP7_27_24)
174#define GPSR4_4 F_(SCL2, IP7_23_20)
175#define GPSR4_3 F_(SDA1, IP7_19_16)
176#define GPSR4_2 F_(SCL1, IP7_15_12)
177#define GPSR4_1 F_(SDA0, IP7_11_8)
178#define GPSR4_0 F_(SCL0, IP7_7_4)
179
180/* GPSR5 */
181#define GPSR5_14 FM(RPC_INT_N)
182#define GPSR5_13 FM(RPC_WP_N)
183#define GPSR5_12 FM(RPC_RESET_N)
184#define GPSR5_11 FM(QSPI1_SSL)
185#define GPSR5_10 FM(QSPI1_IO3)
186#define GPSR5_9 FM(QSPI1_IO2)
187#define GPSR5_8 FM(QSPI1_MISO_IO1)
188#define GPSR5_7 FM(QSPI1_MOSI_IO0)
189#define GPSR5_6 FM(QSPI1_SPCLK)
190#define GPSR5_5 FM(QSPI0_SSL)
191#define GPSR5_4 FM(QSPI0_IO3)
192#define GPSR5_3 FM(QSPI0_IO2)
193#define GPSR5_2 FM(QSPI0_MISO_IO1)
194#define GPSR5_1 FM(QSPI0_MOSI_IO0)
195#define GPSR5_0 FM(QSPI0_SPCLK)
196
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]197/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
198#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]267#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]268#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]271#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]272#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]283
284#define PINMUX_GPSR \
285\
286 GPSR2_29 \
287 GPSR2_28 \
288 GPSR1_27 GPSR2_27 \
289 GPSR1_26 GPSR2_26 \
290 GPSR1_25 GPSR2_25 \
291 GPSR1_24 GPSR2_24 GPSR4_24 \
292 GPSR1_23 GPSR2_23 GPSR4_23 \
293 GPSR1_22 GPSR2_22 GPSR4_22 \
294GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
295GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
296GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
297GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
298GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
299GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
300GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
301GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
302GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
303GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
304GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
305GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
306GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
307GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
308GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
309GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
310GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
311GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
312GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
313GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
314GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
315GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
316
317#define PINMUX_IPSR \
318\
319FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
320FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
321FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
322FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
323FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
324FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
325FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
326FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
327\
328FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
329FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
330FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
331FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
332FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
333FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
334FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
335FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
336\
337FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
338FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
339FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
340FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
341FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]342FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
343FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
344FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]345
346/* MOD_SEL0 */ /* 0 */ /* 1 */
347#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
348#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
349#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
350#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
351#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
352#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
353#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
354#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
355#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
356#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
357#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
358
359#define PINMUX_MOD_SELS \
360\
361MOD_SEL0_11 \
362MOD_SEL0_10 \
363MOD_SEL0_9 \
364MOD_SEL0_8 \
365MOD_SEL0_7 \
366MOD_SEL0_6 \
367MOD_SEL0_5 \
368MOD_SEL0_4 \
369MOD_SEL0_2 \
370MOD_SEL0_1 \
371MOD_SEL0_0
372
373enum {
374 PINMUX_RESERVED = 0,
375
376 PINMUX_DATA_BEGIN,
377 GP_ALL(DATA),
378 PINMUX_DATA_END,
379
380#define F_(x, y)
381#define FM(x) FN_##x,
382 PINMUX_FUNCTION_BEGIN,
383 GP_ALL(FN),
384 PINMUX_GPSR
385 PINMUX_IPSR
386 PINMUX_MOD_SELS
387 PINMUX_FUNCTION_END,
388#undef F_
389#undef FM
390
391#define F_(x, y)
392#define FM(x) x##_MARK,
393 PINMUX_MARK_BEGIN,
394 PINMUX_GPSR
395 PINMUX_IPSR
396 PINMUX_MOD_SELS
397 PINMUX_MARK_END,
398#undef F_
399#undef FM
400};
401
402static const u16 pinmux_data[] = {
403 PINMUX_DATA_GP_ALL(),
404
405 PINMUX_SINGLE(AVB_RX_CTL),
406 PINMUX_SINGLE(AVB_RXC),
407 PINMUX_SINGLE(AVB_RD0),
408 PINMUX_SINGLE(AVB_RD1),
409 PINMUX_SINGLE(AVB_RD2),
410 PINMUX_SINGLE(AVB_RD3),
411 PINMUX_SINGLE(AVB_TX_CTL),
412 PINMUX_SINGLE(AVB_TXC),
413 PINMUX_SINGLE(AVB_TD0),
414 PINMUX_SINGLE(AVB_TD1),
415 PINMUX_SINGLE(AVB_TD2),
416 PINMUX_SINGLE(AVB_TD3),
417 PINMUX_SINGLE(AVB_TXCREFCLK),
418 PINMUX_SINGLE(AVB_MDIO),
419 PINMUX_SINGLE(AVB_MDC),
420 PINMUX_SINGLE(AVB_MAGIC),
421 PINMUX_SINGLE(AVB_PHY_INT),
422 PINMUX_SINGLE(AVB_LINK),
423
424 PINMUX_SINGLE(GETHER_RX_CTL),
425 PINMUX_SINGLE(GETHER_RXC),
426 PINMUX_SINGLE(GETHER_RD0),
427 PINMUX_SINGLE(GETHER_RD1),
428 PINMUX_SINGLE(GETHER_RD2),
429 PINMUX_SINGLE(GETHER_RD3),
430 PINMUX_SINGLE(GETHER_TX_CTL),
431 PINMUX_SINGLE(GETHER_TXC),
432 PINMUX_SINGLE(GETHER_TD0),
433 PINMUX_SINGLE(GETHER_TD1),
434 PINMUX_SINGLE(GETHER_TD2),
435 PINMUX_SINGLE(GETHER_TD3),
436 PINMUX_SINGLE(GETHER_TXCREFCLK),
437 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
438 PINMUX_SINGLE(GETHER_MDIO_A),
439 PINMUX_SINGLE(GETHER_MDC_A),
440 PINMUX_SINGLE(GETHER_MAGIC),
441 PINMUX_SINGLE(GETHER_PHY_INT_A),
442 PINMUX_SINGLE(GETHER_LINK_A),
443
444 PINMUX_SINGLE(QSPI0_SPCLK),
445 PINMUX_SINGLE(QSPI0_MOSI_IO0),
446 PINMUX_SINGLE(QSPI0_MISO_IO1),
447 PINMUX_SINGLE(QSPI0_IO2),
448 PINMUX_SINGLE(QSPI0_IO3),
449 PINMUX_SINGLE(QSPI0_SSL),
450 PINMUX_SINGLE(QSPI1_SPCLK),
451 PINMUX_SINGLE(QSPI1_MOSI_IO0),
452 PINMUX_SINGLE(QSPI1_MISO_IO1),
453 PINMUX_SINGLE(QSPI1_IO2),
454 PINMUX_SINGLE(QSPI1_IO3),
455 PINMUX_SINGLE(QSPI1_SSL),
456 PINMUX_SINGLE(RPC_RESET_N),
457 PINMUX_SINGLE(RPC_WP_N),
458 PINMUX_SINGLE(RPC_INT_N),
459
460 /* IPSR0 */
461 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
462 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
463 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
464 PINMUX_IPSR_GPSR(IP0_3_0, A0),
465
466 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
467 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
468 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
469 PINMUX_IPSR_GPSR(IP0_7_4, A1),
470
471 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
472 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
473 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
474 PINMUX_IPSR_GPSR(IP0_11_8, A2),
475
476 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
477 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
478 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
479 PINMUX_IPSR_GPSR(IP0_15_12, A3),
480
481 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
482 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
483 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
484 PINMUX_IPSR_GPSR(IP0_19_16, A4),
485
486 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
487 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
488 PINMUX_IPSR_GPSR(IP0_23_20, A5),
489
490 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
491 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
492 PINMUX_IPSR_GPSR(IP0_27_24, A6),
493
494 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
495 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
496 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
497 PINMUX_IPSR_GPSR(IP0_31_28, A7),
498 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
499
500 /* IPSR1 */
501 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
502 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
503 PINMUX_IPSR_GPSR(IP1_3_0, A8),
504
505 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
506 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
507 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
508 PINMUX_IPSR_GPSR(IP1_7_4, A9),
509
510 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
511 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
512 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
513 PINMUX_IPSR_GPSR(IP1_11_8, A10),
514
515 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
516 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
517 PINMUX_IPSR_GPSR(IP1_15_12, A11),
518
519 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
520 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
521 PINMUX_IPSR_GPSR(IP1_19_16, A12),
522 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
523
524 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
525 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
526 PINMUX_IPSR_GPSR(IP1_23_20, A13),
527 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
528
529 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
530 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
531 PINMUX_IPSR_GPSR(IP1_27_24, A14),
532 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
533
534 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
535 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
536 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
537 PINMUX_IPSR_GPSR(IP1_31_28, A15),
538
539 /* IPSR2 */
540 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
541 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
542 PINMUX_IPSR_GPSR(IP2_3_0, A16),
543
544 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
545 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
546 PINMUX_IPSR_GPSR(IP2_7_4, A17),
547
548 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
549 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
550 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
551 PINMUX_IPSR_GPSR(IP2_11_8, A18),
552
553 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
554 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
555 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
556 PINMUX_IPSR_GPSR(IP2_15_12, A19),
557 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
558
559 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
560 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
561 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
562
563 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
564 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
565
566 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
567
568 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
569 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
570 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
571 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
572
573 /* IPSR3 */
574 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
575 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
576 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
577 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
578 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
579
580 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
581 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
582 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
583 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
584
585 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
586 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
587 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
588 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
589
590 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
591 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
592 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
593 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
594
595 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
596 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
597 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
598 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
599
600 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
601 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
602
603 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
604 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
605
606 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
607 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
608 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
609
610 /* IPSR4 */
611 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
612 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
613 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
614
615 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
616 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
617 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
618
619 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
620 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
621 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
622
623 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
624 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
625
626 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
627 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
628 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
629
630 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
631 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
632 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
633
634 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
635 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
636 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
637
638 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
639 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
640 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
641 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
642
643 /* IPSR5 */
644 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
645 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
646 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
647
648 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
649 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
650 PINMUX_IPSR_GPSR(IP5_7_4, D0),
651
652 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
653 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
654 PINMUX_IPSR_GPSR(IP5_11_8, D1),
655
656 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
657 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
658 PINMUX_IPSR_GPSR(IP5_15_12, D2),
659
660 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
661 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
662 PINMUX_IPSR_GPSR(IP5_19_16, D3),
663 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
664
665 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
666 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
667 PINMUX_IPSR_GPSR(IP5_23_20, D4),
668 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
669
670 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
671 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
672 PINMUX_IPSR_GPSR(IP5_27_24, D5),
673 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
674
675 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
676 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
677 PINMUX_IPSR_GPSR(IP5_31_28, D6),
678 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
679
680 /* IPSR6 */
681 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
682 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
683 PINMUX_IPSR_GPSR(IP6_3_0, D7),
684 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
685
686 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
687 PINMUX_IPSR_GPSR(IP6_7_4, D8),
688 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
689
690 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
691 PINMUX_IPSR_GPSR(IP6_11_8, D9),
692 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
693
694 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
695 PINMUX_IPSR_GPSR(IP6_15_12, D10),
696 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
697
698 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
699 PINMUX_IPSR_GPSR(IP6_19_16, D11),
700 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
701
702 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
703 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
704 PINMUX_IPSR_GPSR(IP6_23_20, D12),
705 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
706
707 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
708 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
709 PINMUX_IPSR_GPSR(IP6_27_24, D13),
710 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
711
712 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
713 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
714 PINMUX_IPSR_GPSR(IP6_31_28, D14),
715 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
716
717 /* IPSR7 */
718 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
719 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
720 PINMUX_IPSR_GPSR(IP7_3_0, D15),
721 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
722
723 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
724 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
725
726 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
727 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
728 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
729 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
730
731 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
732 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
733 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
734 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
735 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
736
737 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
738 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
739 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
740 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
741 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
742
743 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
744 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
745 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
746 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
747
748 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
749 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
750 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
751 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
752
753 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
754 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
755
756 /* IPSR8 */
757 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
758 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
759
760 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
761 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
762 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
763 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
764
765 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
766 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
767 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
768 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
769
770 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
771 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
772 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
773 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
774 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
775
776 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
777 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
778 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
779 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
780 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
781
782 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
783 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
784 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
785 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
786 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
787
788 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
789 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
790
791 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
792 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
793
794 /* IPSR9 */
795 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
796 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
797
798 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
799 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
800
801 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
802 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
803 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
804
805 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
806 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
807 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
808
809 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
810 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
811 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
812
813 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
814 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
815 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
816
817 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
818 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
819 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
820 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
821
822 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
823 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
824 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
825 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
826
827 /* IPSR10 */
828 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
829 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
830
831 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
832 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
833
834 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
835 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
836
837 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
838 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
839
840 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
841};
842
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]843/*
844 * Pins not associated with a GPIO port.
845 */
846enum {
847 GP_ASSIGN_LAST(),
848 NOGP_ALL(),
849};
850
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]851static const struct sh_pfc_pin pinmux_pins[] = {
852 PINMUX_GPIO_GP_ALL(),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]853 PINMUX_NOGP_ALL(),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]854};
855
856/* - AVB -------------------------------------------------------------------- */
857static const unsigned int avb_link_pins[] = {
858 /* AVB_LINK */
859 RCAR_GP_PIN(1, 18),
860};
861static const unsigned int avb_link_mux[] = {
862 AVB_LINK_MARK,
863};
864static const unsigned int avb_magic_pins[] = {
865 /* AVB_MAGIC */
866 RCAR_GP_PIN(1, 16),
867};
868static const unsigned int avb_magic_mux[] = {
869 AVB_MAGIC_MARK,
870};
871static const unsigned int avb_phy_int_pins[] = {
872 /* AVB_PHY_INT */
873 RCAR_GP_PIN(1, 17),
874};
875static const unsigned int avb_phy_int_mux[] = {
876 AVB_PHY_INT_MARK,
877};
878static const unsigned int avb_mdio_pins[] = {
879 /* AVB_MDC, AVB_MDIO */
880 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
881};
882static const unsigned int avb_mdio_mux[] = {
883 AVB_MDC_MARK, AVB_MDIO_MARK,
884};
885static const unsigned int avb_rgmii_pins[] = {
886 /*
887 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
888 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
889 */
890 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
891 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
892 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
893 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
894 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
895 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
896};
897static const unsigned int avb_rgmii_mux[] = {
898 AVB_TX_CTL_MARK, AVB_TXC_MARK,
899 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
900 AVB_RX_CTL_MARK, AVB_RXC_MARK,
901 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
902};
903static const unsigned int avb_txcrefclk_pins[] = {
904 /* AVB_TXCREFCLK */
905 RCAR_GP_PIN(1, 13),
906};
907static const unsigned int avb_txcrefclk_mux[] = {
908 AVB_TXCREFCLK_MARK,
909};
910static const unsigned int avb_avtp_pps_pins[] = {
911 /* AVB_AVTP_PPS */
912 RCAR_GP_PIN(2, 6),
913};
914static const unsigned int avb_avtp_pps_mux[] = {
915 AVB_AVTP_PPS_MARK,
916};
917static const unsigned int avb_avtp_capture_pins[] = {
918 /* AVB_AVTP_CAPTURE */
919 RCAR_GP_PIN(1, 20),
920};
921static const unsigned int avb_avtp_capture_mux[] = {
922 AVB_AVTP_CAPTURE_MARK,
923};
924static const unsigned int avb_avtp_match_pins[] = {
925 /* AVB_AVTP_MATCH */
926 RCAR_GP_PIN(1, 19),
927};
928static const unsigned int avb_avtp_match_mux[] = {
929 AVB_AVTP_MATCH_MARK,
930};
931
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]932#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]933/* - CANFD0 ----------------------------------------------------------------- */
934static const unsigned int canfd0_data_a_pins[] = {
935 /* CANFD0_TX, CANFD0_RX */
936 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
937};
938static const unsigned int canfd0_data_a_mux[] = {
939 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
940};
941static const unsigned int canfd0_data_b_pins[] = {
942 /* CANFD0_TX, CANFD0_RX */
943 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
944};
945static const unsigned int canfd0_data_b_mux[] = {
946 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
947};
948
949/* - CANFD1 ----------------------------------------------------------------- */
950static const unsigned int canfd1_data_pins[] = {
951 /* CANFD1_TX, CANFD1_RX */
952 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
953};
954static const unsigned int canfd1_data_mux[] = {
955 CANFD1_TX_MARK, CANFD1_RX_MARK,
956};
957
958/* - CANFD Clock ------------------------------------------------------------ */
959static const unsigned int canfd_clk_a_pins[] = {
960 /* CANFD_CLK */
961 RCAR_GP_PIN(1, 25),
962};
963static const unsigned int canfd_clk_a_mux[] = {
964 CANFD_CLK_A_MARK,
965};
966static const unsigned int canfd_clk_b_pins[] = {
967 /* CANFD_CLK */
968 RCAR_GP_PIN(3, 8),
969};
970static const unsigned int canfd_clk_b_mux[] = {
971 CANFD_CLK_B_MARK,
972};
973
974/* - DU --------------------------------------------------------------------- */
975static const unsigned int du_rgb666_pins[] = {
976 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
977 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
978 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
979 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
980 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
981 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
982 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
983};
984static const unsigned int du_rgb666_mux[] = {
985 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
986 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
987 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
988 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
989 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
990 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
991};
992static const unsigned int du_rgb888_pins[] = {
993 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
994 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
995 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
996 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
997 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
998 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
999 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1000 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
1001 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1002 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1003};
1004static const unsigned int du_rgb888_mux[] = {
1005 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1006 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1007 DU_DR1_MARK, DU_DR0_MARK,
1008 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1009 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1010 DU_DG1_MARK, DU_DG0_MARK,
1011 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1012 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1013 DU_DB1_MARK, DU_DB0_MARK,
1014};
1015static const unsigned int du_clk_out_pins[] = {
1016 /* DU_DOTCLKOUT */
1017 RCAR_GP_PIN(0, 18),
1018};
1019static const unsigned int du_clk_out_mux[] = {
1020 DU_DOTCLKOUT_MARK,
1021};
1022static const unsigned int du_sync_pins[] = {
1023 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1024 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1025};
1026static const unsigned int du_sync_mux[] = {
1027 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1028};
1029static const unsigned int du_oddf_pins[] = {
1030 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1031 RCAR_GP_PIN(0, 21),
1032};
1033static const unsigned int du_oddf_mux[] = {
1034 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1035};
1036static const unsigned int du_cde_pins[] = {
1037 /* DU_CDE */
1038 RCAR_GP_PIN(1, 22),
1039};
1040static const unsigned int du_cde_mux[] = {
1041 DU_CDE_MARK,
1042};
1043static const unsigned int du_disp_pins[] = {
1044 /* DU_DISP */
1045 RCAR_GP_PIN(1, 21),
1046};
1047static const unsigned int du_disp_mux[] = {
1048 DU_DISP_MARK,
1049};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1050#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1051
1052/* - GETHER ----------------------------------------------------------------- */
1053static const unsigned int gether_link_a_pins[] = {
1054 /* GETHER_LINK */
1055 RCAR_GP_PIN(4, 24),
1056};
1057static const unsigned int gether_link_a_mux[] = {
1058 GETHER_LINK_A_MARK,
1059};
1060static const unsigned int gether_phy_int_a_pins[] = {
1061 /* GETHER_PHY_INT */
1062 RCAR_GP_PIN(4, 23),
1063};
1064static const unsigned int gether_phy_int_a_mux[] = {
1065 GETHER_PHY_INT_A_MARK,
1066};
1067static const unsigned int gether_mdio_a_pins[] = {
1068 /* GETHER_MDC, GETHER_MDIO */
1069 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1070};
1071static const unsigned int gether_mdio_a_mux[] = {
1072 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1073};
1074static const unsigned int gether_link_b_pins[] = {
1075 /* GETHER_LINK */
1076 RCAR_GP_PIN(0, 18),
1077};
1078static const unsigned int gether_link_b_mux[] = {
1079 GETHER_LINK_B_MARK,
1080};
1081static const unsigned int gether_phy_int_b_pins[] = {
1082 /* GETHER_PHY_INT */
1083 RCAR_GP_PIN(0, 19),
1084};
1085static const unsigned int gether_phy_int_b_mux[] = {
1086 GETHER_PHY_INT_B_MARK,
1087};
1088static const unsigned int gether_mdio_b_mux[] = {
1089 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1090};
1091static const unsigned int gether_mdio_b_pins[] = {
1092 /* GETHER_MDC, GETHER_MDIO */
1093 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1094};
1095static const unsigned int gether_magic_pins[] = {
1096 /* GETHER_MAGIC */
1097 RCAR_GP_PIN(4, 22),
1098};
1099static const unsigned int gether_magic_mux[] = {
1100 GETHER_MAGIC_MARK,
1101};
1102static const unsigned int gether_rgmii_pins[] = {
1103 /*
1104 * GETHER_TX_CTL, GETHER_TXC,
1105 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1106 * GETHER_RX_CTL, GETHER_RXC,
1107 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1108 */
1109 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1110 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1111 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1112 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1113 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1114 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1115};
1116static const unsigned int gether_rgmii_mux[] = {
1117 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1118 GETHER_TD0_MARK, GETHER_TD1_MARK,
1119 GETHER_TD2_MARK, GETHER_TD3_MARK,
1120 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1121 GETHER_RD0_MARK, AVB_RD1_MARK,
1122 GETHER_RD2_MARK, AVB_RD3_MARK,
1123};
1124static const unsigned int gether_txcrefclk_pins[] = {
1125 /* GETHER_TXCREFCLK */
1126 RCAR_GP_PIN(4, 18),
1127};
1128static const unsigned int gether_txcrefclk_mux[] = {
1129 GETHER_TXCREFCLK_MARK,
1130};
1131static const unsigned int gether_txcrefclk_mega_pins[] = {
1132 /* GETHER_TXCREFCLK_MEGA */
1133 RCAR_GP_PIN(4, 19),
1134};
1135static const unsigned int gether_txcrefclk_mega_mux[] = {
1136 GETHER_TXCREFCLK_MEGA_MARK,
1137};
1138static const unsigned int gether_rmii_pins[] = {
1139 /*
1140 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1141 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1142 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1143 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1144 */
1145 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1146 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1147 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1148 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1149};
1150static const unsigned int gether_rmii_mux[] = {
1151 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1152 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1153 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1154 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1155};
1156
1157/* - HSCIF0 ----------------------------------------------------------------- */
1158static const unsigned int hscif0_data_a_pins[] = {
1159 /* HRX0, HTX0 */
1160 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1161};
1162static const unsigned int hscif0_data_a_mux[] = {
1163 HRX0_A_MARK, HTX0_A_MARK,
1164};
1165static const unsigned int hscif0_clk_a_pins[] = {
1166 /* HSCK0 */
1167 RCAR_GP_PIN(0, 12),
1168};
1169static const unsigned int hscif0_clk_a_mux[] = {
1170 HSCK0_A_MARK,
1171};
1172static const unsigned int hscif0_ctrl_a_pins[] = {
1173 /* HRTS0#, HCTS0# */
1174 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1175};
1176static const unsigned int hscif0_ctrl_a_mux[] = {
1177 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1178};
1179static const unsigned int hscif0_data_b_pins[] = {
1180 /* HRX0, HTX0 */
1181 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1182};
1183static const unsigned int hscif0_data_b_mux[] = {
1184 HRX0_B_MARK, HTX0_B_MARK,
1185};
1186static const unsigned int hscif0_clk_b_pins[] = {
1187 /* HSCK0 */
1188 RCAR_GP_PIN(4, 1),
1189};
1190static const unsigned int hscif0_clk_b_mux[] = {
1191 HSCK0_B_MARK,
1192};
1193static const unsigned int hscif0_ctrl_b_pins[] = {
1194 /* HRTS0#, HCTS0# */
1195 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1196};
1197static const unsigned int hscif0_ctrl_b_mux[] = {
1198 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1199};
1200
1201/* - HSCIF1 ----------------------------------------------------------------- */
1202static const unsigned int hscif1_data_pins[] = {
1203 /* HRX1, HTX1 */
1204 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1205};
1206static const unsigned int hscif1_data_mux[] = {
1207 HRX1_MARK, HTX1_MARK,
1208};
1209static const unsigned int hscif1_clk_pins[] = {
1210 /* HSCK1 */
1211 RCAR_GP_PIN(2, 7),
1212};
1213static const unsigned int hscif1_clk_mux[] = {
1214 HSCK1_MARK,
1215};
1216static const unsigned int hscif1_ctrl_pins[] = {
1217 /* HRTS1#, HCTS1# */
1218 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1219};
1220static const unsigned int hscif1_ctrl_mux[] = {
1221 HRTS1_N_MARK, HCTS1_N_MARK,
1222};
1223
1224/* - HSCIF2 ----------------------------------------------------------------- */
1225static const unsigned int hscif2_data_pins[] = {
1226 /* HRX2, HTX2 */
1227 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1228};
1229static const unsigned int hscif2_data_mux[] = {
1230 HRX2_MARK, HTX2_MARK,
1231};
1232static const unsigned int hscif2_clk_pins[] = {
1233 /* HSCK2 */
1234 RCAR_GP_PIN(2, 12),
1235};
1236static const unsigned int hscif2_clk_mux[] = {
1237 HSCK2_MARK,
1238};
1239static const unsigned int hscif2_ctrl_pins[] = {
1240 /* HRTS2#, HCTS2# */
1241 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1242};
1243static const unsigned int hscif2_ctrl_mux[] = {
1244 HRTS2_N_MARK, HCTS2_N_MARK,
1245};
1246
1247/* - HSCIF3 ----------------------------------------------------------------- */
1248static const unsigned int hscif3_data_pins[] = {
1249 /* HRX3, HTX3 */
1250 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1251};
1252static const unsigned int hscif3_data_mux[] = {
1253 HRX3_MARK, HTX3_MARK,
1254};
1255static const unsigned int hscif3_clk_pins[] = {
1256 /* HSCK3 */
1257 RCAR_GP_PIN(2, 0),
1258};
1259static const unsigned int hscif3_clk_mux[] = {
1260 HSCK3_MARK,
1261};
1262static const unsigned int hscif3_ctrl_pins[] = {
1263 /* HRTS3#, HCTS3# */
1264 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1265};
1266static const unsigned int hscif3_ctrl_mux[] = {
1267 HRTS3_N_MARK, HCTS3_N_MARK,
1268};
1269
1270/* - I2C0 ------------------------------------------------------------------- */
1271static const unsigned int i2c0_pins[] = {
1272 /* SDA0, SCL0 */
1273 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1274};
1275static const unsigned int i2c0_mux[] = {
1276 SDA0_MARK, SCL0_MARK,
1277};
1278
1279/* - I2C1 ------------------------------------------------------------------- */
1280static const unsigned int i2c1_pins[] = {
1281 /* SDA1, SCL1 */
1282 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1283};
1284static const unsigned int i2c1_mux[] = {
1285 SDA1_MARK, SCL1_MARK,
1286};
1287
1288/* - I2C2 ------------------------------------------------------------------- */
1289static const unsigned int i2c2_pins[] = {
1290 /* SDA2, SCL2 */
1291 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1292};
1293static const unsigned int i2c2_mux[] = {
1294 SDA2_MARK, SCL2_MARK,
1295};
1296
1297/* - I2C3 ------------------------------------------------------------------- */
1298static const unsigned int i2c3_pins[] = {
1299 /* SDA3, SCL3 */
1300 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1301};
1302static const unsigned int i2c3_mux[] = {
1303 SDA3_MARK, SCL3_MARK,
1304};
1305
1306/* - I2C4 ------------------------------------------------------------------- */
1307static const unsigned int i2c4_pins[] = {
1308 /* SDA4, SCL4 */
1309 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1310};
1311static const unsigned int i2c4_mux[] = {
1312 SDA4_MARK, SCL4_MARK,
1313};
1314
1315/* - I2C5 ------------------------------------------------------------------- */
1316static const unsigned int i2c5_pins[] = {
1317 /* SDA5, SCL5 */
1318 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1319};
1320static const unsigned int i2c5_mux[] = {
1321 SDA5_MARK, SCL5_MARK,
1322};
1323
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1324#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1325/* - INTC-EX ---------------------------------------------------------------- */
1326static const unsigned int intc_ex_irq0_pins[] = {
1327 /* IRQ0 */
1328 RCAR_GP_PIN(1, 0),
1329};
1330static const unsigned int intc_ex_irq0_mux[] = {
1331 IRQ0_MARK,
1332};
1333static const unsigned int intc_ex_irq1_pins[] = {
1334 /* IRQ1 */
1335 RCAR_GP_PIN(0, 12),
1336};
1337static const unsigned int intc_ex_irq1_mux[] = {
1338 IRQ1_MARK,
1339};
1340static const unsigned int intc_ex_irq2_pins[] = {
1341 /* IRQ2 */
1342 RCAR_GP_PIN(0, 13),
1343};
1344static const unsigned int intc_ex_irq2_mux[] = {
1345 IRQ2_MARK,
1346};
1347static const unsigned int intc_ex_irq3_pins[] = {
1348 /* IRQ3 */
1349 RCAR_GP_PIN(0, 14),
1350};
1351static const unsigned int intc_ex_irq3_mux[] = {
1352 IRQ3_MARK,
1353};
1354static const unsigned int intc_ex_irq4_pins[] = {
1355 /* IRQ4 */
1356 RCAR_GP_PIN(2, 17),
1357};
1358static const unsigned int intc_ex_irq4_mux[] = {
1359 IRQ4_MARK,
1360};
1361static const unsigned int intc_ex_irq5_pins[] = {
1362 /* IRQ5 */
1363 RCAR_GP_PIN(2, 18),
1364};
1365static const unsigned int intc_ex_irq5_mux[] = {
1366 IRQ5_MARK,
1367};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1368#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1369
1370/* - MMC -------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1371static const unsigned int mmc_data_pins[] = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1372 /* MMC_D[0:7] */
1373 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1374 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1375 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1376 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1377};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1378static const unsigned int mmc_data_mux[] = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1379 MMC_D0_MARK, MMC_D1_MARK,
1380 MMC_D2_MARK, MMC_D3_MARK,
1381 MMC_D4_MARK, MMC_D5_MARK,
1382 MMC_D6_MARK, MMC_D7_MARK,
1383};
1384static const unsigned int mmc_ctrl_pins[] = {
1385 /* MMC_CLK, MMC_CMD */
1386 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1387};
1388static const unsigned int mmc_ctrl_mux[] = {
1389 MMC_CLK_MARK, MMC_CMD_MARK,
1390};
1391static const unsigned int mmc_cd_pins[] = {
1392 /* MMC_CD */
1393 RCAR_GP_PIN(3, 5),
1394};
1395static const unsigned int mmc_cd_mux[] = {
1396 MMC_CD_MARK,
1397};
1398static const unsigned int mmc_wp_pins[] = {
1399 /* MMC_WP */
1400 RCAR_GP_PIN(3, 4),
1401};
1402static const unsigned int mmc_wp_mux[] = {
1403 MMC_WP_MARK,
1404};
1405static const unsigned int mmc_ds_pins[] = {
1406 /* MMC_DS */
1407 RCAR_GP_PIN(3, 6),
1408};
1409static const unsigned int mmc_ds_mux[] = {
1410 MMC_DS_MARK,
1411};
1412
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1413#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1414/* - MSIOF0 ----------------------------------------------------------------- */
1415static const unsigned int msiof0_clk_pins[] = {
1416 /* MSIOF0_SCK */
1417 RCAR_GP_PIN(2, 21),
1418};
1419static const unsigned int msiof0_clk_mux[] = {
1420 MSIOF0_SCK_MARK,
1421};
1422static const unsigned int msiof0_sync_pins[] = {
1423 /* MSIOF0_SYNC */
1424 RCAR_GP_PIN(2, 22),
1425};
1426static const unsigned int msiof0_sync_mux[] = {
1427 MSIOF0_SYNC_MARK,
1428};
1429static const unsigned int msiof0_ss1_pins[] = {
1430 /* MSIOF0_SS1 */
1431 RCAR_GP_PIN(2, 23),
1432};
1433static const unsigned int msiof0_ss1_mux[] = {
1434 MSIOF0_SS1_MARK,
1435};
1436static const unsigned int msiof0_ss2_pins[] = {
1437 /* MSIOF0_SS2 */
1438 RCAR_GP_PIN(2, 24),
1439};
1440static const unsigned int msiof0_ss2_mux[] = {
1441 MSIOF0_SS2_MARK,
1442};
1443static const unsigned int msiof0_txd_pins[] = {
1444 /* MSIOF0_TXD */
1445 RCAR_GP_PIN(2, 20),
1446};
1447static const unsigned int msiof0_txd_mux[] = {
1448 MSIOF0_TXD_MARK,
1449};
1450static const unsigned int msiof0_rxd_pins[] = {
1451 /* MSIOF0_RXD */
1452 RCAR_GP_PIN(2, 19),
1453};
1454static const unsigned int msiof0_rxd_mux[] = {
1455 MSIOF0_RXD_MARK,
1456};
1457
1458/* - MSIOF1 ----------------------------------------------------------------- */
1459static const unsigned int msiof1_clk_pins[] = {
1460 /* MSIOF1_SCK */
1461 RCAR_GP_PIN(3, 2),
1462};
1463static const unsigned int msiof1_clk_mux[] = {
1464 MSIOF1_SCK_MARK,
1465};
1466static const unsigned int msiof1_sync_pins[] = {
1467 /* MSIOF1_SYNC */
1468 RCAR_GP_PIN(3, 3),
1469};
1470static const unsigned int msiof1_sync_mux[] = {
1471 MSIOF1_SYNC_MARK,
1472};
1473static const unsigned int msiof1_ss1_pins[] = {
1474 /* MSIOF1_SS1 */
1475 RCAR_GP_PIN(3, 4),
1476};
1477static const unsigned int msiof1_ss1_mux[] = {
1478 MSIOF1_SS1_MARK,
1479};
1480static const unsigned int msiof1_ss2_pins[] = {
1481 /* MSIOF1_SS2 */
1482 RCAR_GP_PIN(3, 5),
1483};
1484static const unsigned int msiof1_ss2_mux[] = {
1485 MSIOF1_SS2_MARK,
1486};
1487static const unsigned int msiof1_txd_pins[] = {
1488 /* MSIOF1_TXD */
1489 RCAR_GP_PIN(3, 1),
1490};
1491static const unsigned int msiof1_txd_mux[] = {
1492 MSIOF1_TXD_MARK,
1493};
1494static const unsigned int msiof1_rxd_pins[] = {
1495 /* MSIOF1_RXD */
1496 RCAR_GP_PIN(3, 0),
1497};
1498static const unsigned int msiof1_rxd_mux[] = {
1499 MSIOF1_RXD_MARK,
1500};
1501
1502/* - MSIOF2 ----------------------------------------------------------------- */
1503static const unsigned int msiof2_clk_pins[] = {
1504 /* MSIOF2_SCK */
1505 RCAR_GP_PIN(2, 0),
1506};
1507static const unsigned int msiof2_clk_mux[] = {
1508 MSIOF2_SCK_MARK,
1509};
1510static const unsigned int msiof2_sync_pins[] = {
1511 /* MSIOF2_SYNC */
1512 RCAR_GP_PIN(2, 3),
1513};
1514static const unsigned int msiof2_sync_mux[] = {
1515 MSIOF2_SYNC_MARK,
1516};
1517static const unsigned int msiof2_ss1_pins[] = {
1518 /* MSIOF2_SS1 */
1519 RCAR_GP_PIN(2, 4),
1520};
1521static const unsigned int msiof2_ss1_mux[] = {
1522 MSIOF2_SS1_MARK,
1523};
1524static const unsigned int msiof2_ss2_pins[] = {
1525 /* MSIOF2_SS2 */
1526 RCAR_GP_PIN(2, 5),
1527};
1528static const unsigned int msiof2_ss2_mux[] = {
1529 MSIOF2_SS2_MARK,
1530};
1531static const unsigned int msiof2_txd_pins[] = {
1532 /* MSIOF2_TXD */
1533 RCAR_GP_PIN(2, 2),
1534};
1535static const unsigned int msiof2_txd_mux[] = {
1536 MSIOF2_TXD_MARK,
1537};
1538static const unsigned int msiof2_rxd_pins[] = {
1539 /* MSIOF2_RXD */
1540 RCAR_GP_PIN(2, 1),
1541};
1542static const unsigned int msiof2_rxd_mux[] = {
1543 MSIOF2_RXD_MARK,
1544};
1545
1546/* - MSIOF3 ----------------------------------------------------------------- */
1547static const unsigned int msiof3_clk_pins[] = {
1548 /* MSIOF3_SCK */
1549 RCAR_GP_PIN(0, 20),
1550};
1551static const unsigned int msiof3_clk_mux[] = {
1552 MSIOF3_SCK_MARK,
1553};
1554static const unsigned int msiof3_sync_pins[] = {
1555 /* MSIOF3_SYNC */
1556 RCAR_GP_PIN(0, 21),
1557};
1558static const unsigned int msiof3_sync_mux[] = {
1559 MSIOF3_SYNC_MARK,
1560};
1561static const unsigned int msiof3_ss1_pins[] = {
1562 /* MSIOF3_SS1 */
1563 RCAR_GP_PIN(0, 18),
1564};
1565static const unsigned int msiof3_ss1_mux[] = {
1566 MSIOF3_SS1_MARK,
1567};
1568static const unsigned int msiof3_ss2_pins[] = {
1569 /* MSIOF3_SS2 */
1570 RCAR_GP_PIN(0, 19),
1571};
1572static const unsigned int msiof3_ss2_mux[] = {
1573 MSIOF3_SS2_MARK,
1574};
1575static const unsigned int msiof3_txd_pins[] = {
1576 /* MSIOF3_TXD */
1577 RCAR_GP_PIN(0, 17),
1578};
1579static const unsigned int msiof3_txd_mux[] = {
1580 MSIOF3_TXD_MARK,
1581};
1582static const unsigned int msiof3_rxd_pins[] = {
1583 /* MSIOF3_RXD */
1584 RCAR_GP_PIN(0, 16),
1585};
1586static const unsigned int msiof3_rxd_mux[] = {
1587 MSIOF3_RXD_MARK,
1588};
1589
1590/* - PWM0 ------------------------------------------------------------------- */
1591static const unsigned int pwm0_a_pins[] = {
1592 /* PWM0 */
1593 RCAR_GP_PIN(0, 15),
1594};
1595static const unsigned int pwm0_a_mux[] = {
1596 PWM0_A_MARK,
1597};
1598static const unsigned int pwm0_b_pins[] = {
1599 /* PWM0 */
1600 RCAR_GP_PIN(1, 21),
1601};
1602static const unsigned int pwm0_b_mux[] = {
1603 PWM0_B_MARK,
1604};
1605
1606/* - PWM1 ------------------------------------------------------------------- */
1607static const unsigned int pwm1_a_pins[] = {
1608 /* PWM1 */
1609 RCAR_GP_PIN(2, 13),
1610};
1611static const unsigned int pwm1_a_mux[] = {
1612 PWM1_A_MARK,
1613};
1614static const unsigned int pwm1_b_pins[] = {
1615 /* PWM1 */
1616 RCAR_GP_PIN(1, 22),
1617};
1618static const unsigned int pwm1_b_mux[] = {
1619 PWM1_B_MARK,
1620};
1621
1622/* - PWM2 ------------------------------------------------------------------- */
1623static const unsigned int pwm2_a_pins[] = {
1624 /* PWM2 */
1625 RCAR_GP_PIN(2, 14),
1626};
1627static const unsigned int pwm2_a_mux[] = {
1628 PWM2_A_MARK,
1629};
1630static const unsigned int pwm2_b_pins[] = {
1631 /* PWM2 */
1632 RCAR_GP_PIN(1, 23),
1633};
1634static const unsigned int pwm2_b_mux[] = {
1635 PWM2_B_MARK,
1636};
1637
1638/* - PWM3 ------------------------------------------------------------------- */
1639static const unsigned int pwm3_a_pins[] = {
1640 /* PWM3 */
1641 RCAR_GP_PIN(2, 15),
1642};
1643static const unsigned int pwm3_a_mux[] = {
1644 PWM3_A_MARK,
1645};
1646static const unsigned int pwm3_b_pins[] = {
1647 /* PWM3 */
1648 RCAR_GP_PIN(1, 24),
1649};
1650static const unsigned int pwm3_b_mux[] = {
1651 PWM3_B_MARK,
1652};
1653
1654/* - PWM4 ------------------------------------------------------------------- */
1655static const unsigned int pwm4_a_pins[] = {
1656 /* PWM4 */
1657 RCAR_GP_PIN(2, 16),
1658};
1659static const unsigned int pwm4_a_mux[] = {
1660 PWM4_A_MARK,
1661};
1662static const unsigned int pwm4_b_pins[] = {
1663 /* PWM4 */
1664 RCAR_GP_PIN(1, 25),
1665};
1666static const unsigned int pwm4_b_mux[] = {
1667 PWM4_B_MARK,
1668};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1669#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1670
1671/* - QSPI0 ------------------------------------------------------------------ */
1672static const unsigned int qspi0_ctrl_pins[] = {
1673 /* SPCLK, SSL */
1674 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1675};
1676static const unsigned int qspi0_ctrl_mux[] = {
1677 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1678};
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1679
1680/* - QSPI1 ------------------------------------------------------------------ */
1681static const unsigned int qspi1_ctrl_pins[] = {
1682 /* SPCLK, SSL */
1683 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1684};
1685static const unsigned int qspi1_ctrl_mux[] = {
1686 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1687};
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1688
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1689/* - RPC -------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1690static const unsigned int rpc_clk_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1691 /* Octal-SPI flash: C/SCLK */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1692 /* HyperFlash: CK, CK# */
1693 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1694};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1695static const unsigned int rpc_clk_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1696 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1697};
1698static const unsigned int rpc_ctrl_pins[] = {
1699 /* Octal-SPI flash: S#/CS, DQS */
1700 /* HyperFlash: CS#, RDS */
1701 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1702};
1703static const unsigned int rpc_ctrl_mux[] = {
1704 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1705};
1706static const unsigned int rpc_data_pins[] = {
1707 /* DQ[0:7] */
1708 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1709 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1710 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1711 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1712};
1713static const unsigned int rpc_data_mux[] = {
1714 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1715 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1716 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1717 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1718};
1719static const unsigned int rpc_reset_pins[] = {
1720 /* RPC_RESET# */
1721 RCAR_GP_PIN(5, 12),
1722};
1723static const unsigned int rpc_reset_mux[] = {
1724 RPC_RESET_N_MARK,
1725};
1726static const unsigned int rpc_int_pins[] = {
1727 /* RPC_INT# */
1728 RCAR_GP_PIN(5, 14),
1729};
1730static const unsigned int rpc_int_mux[] = {
1731 RPC_INT_N_MARK,
1732};
1733static const unsigned int rpc_wp_pins[] = {
1734 /* RPC_WP# */
1735 RCAR_GP_PIN(5, 13),
1736};
1737static const unsigned int rpc_wp_mux[] = {
1738 RPC_WP_N_MARK,
1739};
1740
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1741/* - SCIF0 ------------------------------------------------------------------ */
1742static const unsigned int scif0_data_pins[] = {
1743 /* RX0, TX0 */
1744 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1745};
1746static const unsigned int scif0_data_mux[] = {
1747 RX0_MARK, TX0_MARK,
1748};
1749static const unsigned int scif0_clk_pins[] = {
1750 /* SCK0 */
1751 RCAR_GP_PIN(4, 1),
1752};
1753static const unsigned int scif0_clk_mux[] = {
1754 SCK0_MARK,
1755};
1756static const unsigned int scif0_ctrl_pins[] = {
1757 /* RTS0#, CTS0# */
1758 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1759};
1760static const unsigned int scif0_ctrl_mux[] = {
1761 RTS0_N_MARK, CTS0_N_MARK,
1762};
1763
1764/* - SCIF1 ------------------------------------------------------------------ */
1765static const unsigned int scif1_data_a_pins[] = {
1766 /* RX1, TX1 */
1767 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1768};
1769static const unsigned int scif1_data_a_mux[] = {
1770 RX1_A_MARK, TX1_A_MARK,
1771};
1772static const unsigned int scif1_clk_pins[] = {
1773 /* SCK1 */
1774 RCAR_GP_PIN(2, 5),
1775};
1776static const unsigned int scif1_clk_mux[] = {
1777 SCK1_MARK,
1778};
1779static const unsigned int scif1_ctrl_pins[] = {
1780 /* RTS1#, CTS1# */
1781 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1782};
1783static const unsigned int scif1_ctrl_mux[] = {
1784 RTS1_N_MARK, CTS1_N_MARK,
1785};
1786static const unsigned int scif1_data_b_pins[] = {
1787 /* RX1, TX1 */
1788 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1789};
1790static const unsigned int scif1_data_b_mux[] = {
1791 RX1_B_MARK, TX1_B_MARK,
1792};
1793
1794/* - SCIF3 ------------------------------------------------------------------ */
1795static const unsigned int scif3_data_pins[] = {
1796 /* RX3, TX3 */
1797 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1798};
1799static const unsigned int scif3_data_mux[] = {
1800 RX3_MARK, TX3_MARK,
1801};
1802static const unsigned int scif3_clk_pins[] = {
1803 /* SCK3 */
1804 RCAR_GP_PIN(2, 0),
1805};
1806static const unsigned int scif3_clk_mux[] = {
1807 SCK3_MARK,
1808};
1809static const unsigned int scif3_ctrl_pins[] = {
1810 /* RTS3#, CTS3# */
1811 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1812};
1813static const unsigned int scif3_ctrl_mux[] = {
1814 RTS3_N_MARK, CTS3_N_MARK,
1815};
1816
1817/* - SCIF4 ------------------------------------------------------------------ */
1818static const unsigned int scif4_data_pins[] = {
1819 /* RX4, TX4 */
1820 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1821};
1822static const unsigned int scif4_data_mux[] = {
1823 RX4_MARK, TX4_MARK,
1824};
1825static const unsigned int scif4_clk_pins[] = {
1826 /* SCK4 */
1827 RCAR_GP_PIN(0, 0),
1828};
1829static const unsigned int scif4_clk_mux[] = {
1830 SCK4_MARK,
1831};
1832static const unsigned int scif4_ctrl_pins[] = {
1833 /* RTS4#, CTS4# */
1834 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1835};
1836static const unsigned int scif4_ctrl_mux[] = {
1837 RTS4_N_MARK, CTS4_N_MARK,
1838};
1839
1840/* - SCIF Clock ------------------------------------------------------------- */
1841static const unsigned int scif_clk_a_pins[] = {
1842 /* SCIF_CLK */
1843 RCAR_GP_PIN(0, 10),
1844};
1845static const unsigned int scif_clk_a_mux[] = {
1846 SCIF_CLK_A_MARK,
1847};
1848static const unsigned int scif_clk_b_pins[] = {
1849 /* SCIF_CLK */
1850 RCAR_GP_PIN(1, 25),
1851};
1852static const unsigned int scif_clk_b_mux[] = {
1853 SCIF_CLK_B_MARK,
1854};
1855
1856/* - TMU -------------------------------------------------------------------- */
1857static const unsigned int tmu_tclk1_a_pins[] = {
1858 /* TCLK1 */
1859 RCAR_GP_PIN(3, 13),
1860};
1861static const unsigned int tmu_tclk1_a_mux[] = {
1862 TCLK1_A_MARK,
1863};
1864static const unsigned int tmu_tclk1_b_pins[] = {
1865 /* TCLK1 */
1866 RCAR_GP_PIN(1, 23),
1867};
1868static const unsigned int tmu_tclk1_b_mux[] = {
1869 TCLK1_B_MARK,
1870};
1871static const unsigned int tmu_tclk2_a_pins[] = {
1872 /* TCLK2 */
1873 RCAR_GP_PIN(3, 14),
1874};
1875static const unsigned int tmu_tclk2_a_mux[] = {
1876 TCLK2_A_MARK,
1877};
1878static const unsigned int tmu_tclk2_b_pins[] = {
1879 /* TCLK2 */
1880 RCAR_GP_PIN(1, 24),
1881};
1882static const unsigned int tmu_tclk2_b_mux[] = {
1883 TCLK2_B_MARK,
1884};
1885
1886/* - TPU ------------------------------------------------------------------- */
1887static const unsigned int tpu_to0_pins[] = {
1888 /* TPU0TO0 */
1889 RCAR_GP_PIN(1, 19),
1890};
1891static const unsigned int tpu_to0_mux[] = {
1892 TPU0TO0_MARK,
1893};
1894static const unsigned int tpu_to1_pins[] = {
1895 /* TPU0TO1 */
1896 RCAR_GP_PIN(1, 20),
1897};
1898static const unsigned int tpu_to1_mux[] = {
1899 TPU0TO1_MARK,
1900};
1901static const unsigned int tpu_to2_pins[] = {
1902 /* TPU0TO2 */
1903 RCAR_GP_PIN(4, 2),
1904};
1905static const unsigned int tpu_to2_mux[] = {
1906 TPU0TO2_MARK,
1907};
1908static const unsigned int tpu_to3_pins[] = {
1909 /* TPU0TO3 */
1910 RCAR_GP_PIN(4, 3),
1911};
1912static const unsigned int tpu_to3_mux[] = {
1913 TPU0TO3_MARK,
1914};
1915
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]1916#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1917/* - VIN0 ------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1918static const unsigned int vin0_data_pins[] = {
1919 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1920 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1921 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1922 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1923 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1924 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1925 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1926 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1927 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1928 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1929 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1930 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1931};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1932static const unsigned int vin0_data_mux[] = {
1933 VI0_DATA0_MARK, VI0_DATA1_MARK,
1934 VI0_DATA2_MARK, VI0_DATA3_MARK,
1935 VI0_DATA4_MARK, VI0_DATA5_MARK,
1936 VI0_DATA6_MARK, VI0_DATA7_MARK,
1937 VI0_DATA8_MARK, VI0_DATA9_MARK,
1938 VI0_DATA10_MARK, VI0_DATA11_MARK,
1939 VI0_DATA12_MARK, VI0_DATA13_MARK,
1940 VI0_DATA14_MARK, VI0_DATA15_MARK,
1941 VI0_DATA16_MARK, VI0_DATA17_MARK,
1942 VI0_DATA18_MARK, VI0_DATA19_MARK,
1943 VI0_DATA20_MARK, VI0_DATA21_MARK,
1944 VI0_DATA22_MARK, VI0_DATA23_MARK,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1945};
1946static const unsigned int vin0_data18_pins[] = {
1947 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1948 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1949 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1950 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1951 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1952 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1953 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1954 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1955 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1956};
1957static const unsigned int vin0_data18_mux[] = {
1958 VI0_DATA2_MARK, VI0_DATA3_MARK,
1959 VI0_DATA4_MARK, VI0_DATA5_MARK,
1960 VI0_DATA6_MARK, VI0_DATA7_MARK,
1961 VI0_DATA10_MARK, VI0_DATA11_MARK,
1962 VI0_DATA12_MARK, VI0_DATA13_MARK,
1963 VI0_DATA14_MARK, VI0_DATA15_MARK,
1964 VI0_DATA18_MARK, VI0_DATA19_MARK,
1965 VI0_DATA20_MARK, VI0_DATA21_MARK,
1966 VI0_DATA22_MARK, VI0_DATA23_MARK,
1967};
1968static const unsigned int vin0_sync_pins[] = {
1969 /* VI0_VSYNC#, VI0_HSYNC# */
1970 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1971};
1972static const unsigned int vin0_sync_mux[] = {
1973 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1974};
1975static const unsigned int vin0_field_pins[] = {
1976 /* VI0_FIELD */
1977 RCAR_GP_PIN(2, 16),
1978};
1979static const unsigned int vin0_field_mux[] = {
1980 VI0_FIELD_MARK,
1981};
1982static const unsigned int vin0_clkenb_pins[] = {
1983 /* VI0_CLKENB */
1984 RCAR_GP_PIN(2, 1),
1985};
1986static const unsigned int vin0_clkenb_mux[] = {
1987 VI0_CLKENB_MARK,
1988};
1989static const unsigned int vin0_clk_pins[] = {
1990 /* VI0_CLK */
1991 RCAR_GP_PIN(2, 0),
1992};
1993static const unsigned int vin0_clk_mux[] = {
1994 VI0_CLK_MARK,
1995};
1996
1997/* - VIN1 ------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1998static const unsigned int vin1_data_pins[] = {
1999 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2000 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2001 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2002 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2003 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2004 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2005};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2006static const unsigned int vin1_data_mux[] = {
2007 VI1_DATA0_MARK, VI1_DATA1_MARK,
2008 VI1_DATA2_MARK, VI1_DATA3_MARK,
2009 VI1_DATA4_MARK, VI1_DATA5_MARK,
2010 VI1_DATA6_MARK, VI1_DATA7_MARK,
2011 VI1_DATA8_MARK, VI1_DATA9_MARK,
2012 VI1_DATA10_MARK, VI1_DATA11_MARK,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2013};
2014static const unsigned int vin1_sync_pins[] = {
2015 /* VI1_VSYNC#, VI1_HSYNC# */
2016 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2017};
2018static const unsigned int vin1_sync_mux[] = {
2019 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2020};
2021static const unsigned int vin1_field_pins[] = {
2022 /* VI1_FIELD */
2023 RCAR_GP_PIN(3, 16),
2024};
2025static const unsigned int vin1_field_mux[] = {
2026 VI1_FIELD_MARK,
2027};
2028static const unsigned int vin1_clkenb_pins[] = {
2029 /* VI1_CLKENB */
2030 RCAR_GP_PIN(3, 1),
2031};
2032static const unsigned int vin1_clkenb_mux[] = {
2033 VI1_CLKENB_MARK,
2034};
2035static const unsigned int vin1_clk_pins[] = {
2036 /* VI1_CLK */
2037 RCAR_GP_PIN(3, 0),
2038};
2039static const unsigned int vin1_clk_mux[] = {
2040 VI1_CLK_MARK,
2041};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2042#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2043
2044static const struct sh_pfc_pin_group pinmux_groups[] = {
2045 SH_PFC_PIN_GROUP(avb_link),
2046 SH_PFC_PIN_GROUP(avb_magic),
2047 SH_PFC_PIN_GROUP(avb_phy_int),
2048 SH_PFC_PIN_GROUP(avb_mdio),
2049 SH_PFC_PIN_GROUP(avb_rgmii),
2050 SH_PFC_PIN_GROUP(avb_txcrefclk),
2051 SH_PFC_PIN_GROUP(avb_avtp_pps),
2052 SH_PFC_PIN_GROUP(avb_avtp_capture),
2053 SH_PFC_PIN_GROUP(avb_avtp_match),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2054#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2055 SH_PFC_PIN_GROUP(canfd0_data_a),
2056 SH_PFC_PIN_GROUP(canfd0_data_b),
2057 SH_PFC_PIN_GROUP(canfd1_data),
2058 SH_PFC_PIN_GROUP(canfd_clk_a),
2059 SH_PFC_PIN_GROUP(canfd_clk_b),
2060 SH_PFC_PIN_GROUP(du_rgb666),
2061 SH_PFC_PIN_GROUP(du_rgb888),
2062 SH_PFC_PIN_GROUP(du_clk_out),
2063 SH_PFC_PIN_GROUP(du_sync),
2064 SH_PFC_PIN_GROUP(du_oddf),
2065 SH_PFC_PIN_GROUP(du_cde),
2066 SH_PFC_PIN_GROUP(du_disp),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2067#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2068 SH_PFC_PIN_GROUP(gether_link_a),
2069 SH_PFC_PIN_GROUP(gether_phy_int_a),
2070 SH_PFC_PIN_GROUP(gether_mdio_a),
2071 SH_PFC_PIN_GROUP(gether_link_b),
2072 SH_PFC_PIN_GROUP(gether_phy_int_b),
2073 SH_PFC_PIN_GROUP(gether_mdio_b),
2074 SH_PFC_PIN_GROUP(gether_magic),
2075 SH_PFC_PIN_GROUP(gether_rgmii),
2076 SH_PFC_PIN_GROUP(gether_txcrefclk),
2077 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2078 SH_PFC_PIN_GROUP(gether_rmii),
2079 SH_PFC_PIN_GROUP(hscif0_data_a),
2080 SH_PFC_PIN_GROUP(hscif0_clk_a),
2081 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2082 SH_PFC_PIN_GROUP(hscif0_data_b),
2083 SH_PFC_PIN_GROUP(hscif0_clk_b),
2084 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2085 SH_PFC_PIN_GROUP(hscif1_data),
2086 SH_PFC_PIN_GROUP(hscif1_clk),
2087 SH_PFC_PIN_GROUP(hscif1_ctrl),
2088 SH_PFC_PIN_GROUP(hscif2_data),
2089 SH_PFC_PIN_GROUP(hscif2_clk),
2090 SH_PFC_PIN_GROUP(hscif2_ctrl),
2091 SH_PFC_PIN_GROUP(hscif3_data),
2092 SH_PFC_PIN_GROUP(hscif3_clk),
2093 SH_PFC_PIN_GROUP(hscif3_ctrl),
2094 SH_PFC_PIN_GROUP(i2c0),
2095 SH_PFC_PIN_GROUP(i2c1),
2096 SH_PFC_PIN_GROUP(i2c2),
2097 SH_PFC_PIN_GROUP(i2c3),
2098 SH_PFC_PIN_GROUP(i2c4),
2099 SH_PFC_PIN_GROUP(i2c5),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2100#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2101 SH_PFC_PIN_GROUP(intc_ex_irq0),
2102 SH_PFC_PIN_GROUP(intc_ex_irq1),
2103 SH_PFC_PIN_GROUP(intc_ex_irq2),
2104 SH_PFC_PIN_GROUP(intc_ex_irq3),
2105 SH_PFC_PIN_GROUP(intc_ex_irq4),
2106 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2107#endif
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2108 BUS_DATA_PIN_GROUP(mmc_data, 1),
2109 BUS_DATA_PIN_GROUP(mmc_data, 4),
2110 BUS_DATA_PIN_GROUP(mmc_data, 8),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2111 SH_PFC_PIN_GROUP(mmc_ctrl),
2112 SH_PFC_PIN_GROUP(mmc_cd),
2113 SH_PFC_PIN_GROUP(mmc_wp),
2114 SH_PFC_PIN_GROUP(mmc_ds),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2115#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2116 SH_PFC_PIN_GROUP(msiof0_clk),
2117 SH_PFC_PIN_GROUP(msiof0_sync),
2118 SH_PFC_PIN_GROUP(msiof0_ss1),
2119 SH_PFC_PIN_GROUP(msiof0_ss2),
2120 SH_PFC_PIN_GROUP(msiof0_txd),
2121 SH_PFC_PIN_GROUP(msiof0_rxd),
2122 SH_PFC_PIN_GROUP(msiof1_clk),
2123 SH_PFC_PIN_GROUP(msiof1_sync),
2124 SH_PFC_PIN_GROUP(msiof1_ss1),
2125 SH_PFC_PIN_GROUP(msiof1_ss2),
2126 SH_PFC_PIN_GROUP(msiof1_txd),
2127 SH_PFC_PIN_GROUP(msiof1_rxd),
2128 SH_PFC_PIN_GROUP(msiof2_clk),
2129 SH_PFC_PIN_GROUP(msiof2_sync),
2130 SH_PFC_PIN_GROUP(msiof2_ss1),
2131 SH_PFC_PIN_GROUP(msiof2_ss2),
2132 SH_PFC_PIN_GROUP(msiof2_txd),
2133 SH_PFC_PIN_GROUP(msiof2_rxd),
2134 SH_PFC_PIN_GROUP(msiof3_clk),
2135 SH_PFC_PIN_GROUP(msiof3_sync),
2136 SH_PFC_PIN_GROUP(msiof3_ss1),
2137 SH_PFC_PIN_GROUP(msiof3_ss2),
2138 SH_PFC_PIN_GROUP(msiof3_txd),
2139 SH_PFC_PIN_GROUP(msiof3_rxd),
2140 SH_PFC_PIN_GROUP(pwm0_a),
2141 SH_PFC_PIN_GROUP(pwm0_b),
2142 SH_PFC_PIN_GROUP(pwm1_a),
2143 SH_PFC_PIN_GROUP(pwm1_b),
2144 SH_PFC_PIN_GROUP(pwm2_a),
2145 SH_PFC_PIN_GROUP(pwm2_b),
2146 SH_PFC_PIN_GROUP(pwm3_a),
2147 SH_PFC_PIN_GROUP(pwm3_b),
2148 SH_PFC_PIN_GROUP(pwm4_a),
2149 SH_PFC_PIN_GROUP(pwm4_b),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2150#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2151 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2152 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2153 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2154 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2155 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2156 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2157 BUS_DATA_PIN_GROUP(rpc_clk, 1),
2158 BUS_DATA_PIN_GROUP(rpc_clk, 2),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2159 SH_PFC_PIN_GROUP(rpc_ctrl),
2160 SH_PFC_PIN_GROUP(rpc_data),
2161 SH_PFC_PIN_GROUP(rpc_reset),
2162 SH_PFC_PIN_GROUP(rpc_int),
2163 SH_PFC_PIN_GROUP(rpc_wp),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2164 SH_PFC_PIN_GROUP(scif0_data),
2165 SH_PFC_PIN_GROUP(scif0_clk),
2166 SH_PFC_PIN_GROUP(scif0_ctrl),
2167 SH_PFC_PIN_GROUP(scif1_data_a),
2168 SH_PFC_PIN_GROUP(scif1_clk),
2169 SH_PFC_PIN_GROUP(scif1_ctrl),
2170 SH_PFC_PIN_GROUP(scif1_data_b),
2171 SH_PFC_PIN_GROUP(scif3_data),
2172 SH_PFC_PIN_GROUP(scif3_clk),
2173 SH_PFC_PIN_GROUP(scif3_ctrl),
2174 SH_PFC_PIN_GROUP(scif4_data),
2175 SH_PFC_PIN_GROUP(scif4_clk),
2176 SH_PFC_PIN_GROUP(scif4_ctrl),
2177 SH_PFC_PIN_GROUP(scif_clk_a),
2178 SH_PFC_PIN_GROUP(scif_clk_b),
2179 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2180 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2181 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2182 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2183 SH_PFC_PIN_GROUP(tpu_to0),
2184 SH_PFC_PIN_GROUP(tpu_to1),
2185 SH_PFC_PIN_GROUP(tpu_to2),
2186 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2187#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2188 BUS_DATA_PIN_GROUP(vin0_data, 8),
2189 BUS_DATA_PIN_GROUP(vin0_data, 10),
2190 BUS_DATA_PIN_GROUP(vin0_data, 12),
2191 BUS_DATA_PIN_GROUP(vin0_data, 16),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2192 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2193 BUS_DATA_PIN_GROUP(vin0_data, 20),
2194 BUS_DATA_PIN_GROUP(vin0_data, 24),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2195 SH_PFC_PIN_GROUP(vin0_sync),
2196 SH_PFC_PIN_GROUP(vin0_field),
2197 SH_PFC_PIN_GROUP(vin0_clkenb),
2198 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2199 BUS_DATA_PIN_GROUP(vin1_data, 8),
2200 BUS_DATA_PIN_GROUP(vin1_data, 10),
2201 BUS_DATA_PIN_GROUP(vin1_data, 12),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2202 SH_PFC_PIN_GROUP(vin1_sync),
2203 SH_PFC_PIN_GROUP(vin1_field),
2204 SH_PFC_PIN_GROUP(vin1_clkenb),
2205 SH_PFC_PIN_GROUP(vin1_clk),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2206#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2207};
2208
2209static const char * const avb_groups[] = {
2210 "avb_link",
2211 "avb_magic",
2212 "avb_phy_int",
2213 "avb_mdio",
2214 "avb_rgmii",
2215 "avb_txcrefclk",
2216 "avb_avtp_pps",
2217 "avb_avtp_capture",
2218 "avb_avtp_match",
2219};
2220
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2221#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2222static const char * const canfd0_groups[] = {
2223 "canfd0_data_a",
2224 "canfd0_data_b",
2225};
2226
2227static const char * const canfd1_groups[] = {
2228 "canfd1_data",
2229};
2230
2231static const char * const canfd_clk_groups[] = {
2232 "canfd_clk_a",
2233 "canfd_clk_b",
2234};
2235
2236static const char * const du_groups[] = {
2237 "du_rgb666",
2238 "du_rgb888",
2239 "du_clk_out",
2240 "du_sync",
2241 "du_oddf",
2242 "du_cde",
2243 "du_disp",
2244};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2245#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2246
2247static const char * const gether_groups[] = {
2248 "gether_link_a",
2249 "gether_phy_int_a",
2250 "gether_mdio_a",
2251 "gether_link_b",
2252 "gether_phy_int_b",
2253 "gether_mdio_b",
2254 "gether_magic",
2255 "gether_rgmii",
2256 "gether_txcrefclk",
2257 "gether_txcrefclk_mega",
2258 "gether_rmii",
2259};
2260
2261static const char * const hscif0_groups[] = {
2262 "hscif0_data_a",
2263 "hscif0_clk_a",
2264 "hscif0_ctrl_a",
2265 "hscif0_data_b",
2266 "hscif0_clk_b",
2267 "hscif0_ctrl_b",
2268};
2269
2270static const char * const hscif1_groups[] = {
2271 "hscif1_data",
2272 "hscif1_clk",
2273 "hscif1_ctrl",
2274};
2275
2276static const char * const hscif2_groups[] = {
2277 "hscif2_data",
2278 "hscif2_clk",
2279 "hscif2_ctrl",
2280};
2281
2282static const char * const hscif3_groups[] = {
2283 "hscif3_data",
2284 "hscif3_clk",
2285 "hscif3_ctrl",
2286};
2287
2288static const char * const i2c0_groups[] = {
2289 "i2c0",
2290};
2291
2292static const char * const i2c1_groups[] = {
2293 "i2c1",
2294};
2295
2296static const char * const i2c2_groups[] = {
2297 "i2c2",
2298};
2299
2300static const char * const i2c3_groups[] = {
2301 "i2c3",
2302};
2303
2304static const char * const i2c4_groups[] = {
2305 "i2c4",
2306};
2307
2308static const char * const i2c5_groups[] = {
2309 "i2c5",
2310};
2311
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2312#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2313static const char * const intc_ex_groups[] = {
2314 "intc_ex_irq0",
2315 "intc_ex_irq1",
2316 "intc_ex_irq2",
2317 "intc_ex_irq3",
2318 "intc_ex_irq4",
2319 "intc_ex_irq5",
2320};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2321#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2322
2323static const char * const mmc_groups[] = {
2324 "mmc_data1",
2325 "mmc_data4",
2326 "mmc_data8",
2327 "mmc_ctrl",
2328 "mmc_cd",
2329 "mmc_wp",
2330 "mmc_ds",
2331};
2332
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2333#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2334static const char * const msiof0_groups[] = {
2335 "msiof0_clk",
2336 "msiof0_sync",
2337 "msiof0_ss1",
2338 "msiof0_ss2",
2339 "msiof0_txd",
2340 "msiof0_rxd",
2341};
2342
2343static const char * const msiof1_groups[] = {
2344 "msiof1_clk",
2345 "msiof1_sync",
2346 "msiof1_ss1",
2347 "msiof1_ss2",
2348 "msiof1_txd",
2349 "msiof1_rxd",
2350};
2351
2352static const char * const msiof2_groups[] = {
2353 "msiof2_clk",
2354 "msiof2_sync",
2355 "msiof2_ss1",
2356 "msiof2_ss2",
2357 "msiof2_txd",
2358 "msiof2_rxd",
2359};
2360
2361static const char * const msiof3_groups[] = {
2362 "msiof3_clk",
2363 "msiof3_sync",
2364 "msiof3_ss1",
2365 "msiof3_ss2",
2366 "msiof3_txd",
2367 "msiof3_rxd",
2368};
2369
2370static const char * const pwm0_groups[] = {
2371 "pwm0_a",
2372 "pwm0_b",
2373};
2374
2375static const char * const pwm1_groups[] = {
2376 "pwm1_a",
2377 "pwm1_b",
2378};
2379
2380static const char * const pwm2_groups[] = {
2381 "pwm2_a",
2382 "pwm2_b",
2383};
2384
2385static const char * const pwm3_groups[] = {
2386 "pwm3_a",
2387 "pwm3_b",
2388};
2389
2390static const char * const pwm4_groups[] = {
2391 "pwm4_a",
2392 "pwm4_b",
2393};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2394#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2395
2396static const char * const qspi0_groups[] = {
2397 "qspi0_ctrl",
2398 "qspi0_data2",
2399 "qspi0_data4",
2400};
2401
2402static const char * const qspi1_groups[] = {
2403 "qspi1_ctrl",
2404 "qspi1_data2",
2405 "qspi1_data4",
2406};
2407
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2408static const char * const rpc_groups[] = {
2409 "rpc_clk1",
2410 "rpc_clk2",
2411 "rpc_ctrl",
2412 "rpc_data",
2413 "rpc_reset",
2414 "rpc_int",
2415 "rpc_wp",
2416};
2417
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2418static const char * const scif0_groups[] = {
2419 "scif0_data",
2420 "scif0_clk",
2421 "scif0_ctrl",
2422};
2423
2424static const char * const scif1_groups[] = {
2425 "scif1_data_a",
2426 "scif1_clk",
2427 "scif1_ctrl",
2428 "scif1_data_b",
2429};
2430
2431static const char * const scif3_groups[] = {
2432 "scif3_data",
2433 "scif3_clk",
2434 "scif3_ctrl",
2435};
2436
2437static const char * const scif4_groups[] = {
2438 "scif4_data",
2439 "scif4_clk",
2440 "scif4_ctrl",
2441};
2442
2443static const char * const scif_clk_groups[] = {
2444 "scif_clk_a",
2445 "scif_clk_b",
2446};
2447
2448static const char * const tmu_groups[] = {
2449 "tmu_tclk1_a",
2450 "tmu_tclk1_b",
2451 "tmu_tclk2_a",
2452 "tmu_tclk2_b",
2453};
2454
2455static const char * const tpu_groups[] = {
2456 "tpu_to0",
2457 "tpu_to1",
2458 "tpu_to2",
2459 "tpu_to3",
2460};
2461
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2462#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2463static const char * const vin0_groups[] = {
2464 "vin0_data8",
2465 "vin0_data10",
2466 "vin0_data12",
2467 "vin0_data16",
2468 "vin0_data18",
2469 "vin0_data20",
2470 "vin0_data24",
2471 "vin0_sync",
2472 "vin0_field",
2473 "vin0_clkenb",
2474 "vin0_clk",
2475};
2476
2477static const char * const vin1_groups[] = {
2478 "vin1_data8",
2479 "vin1_data10",
2480 "vin1_data12",
2481 "vin1_sync",
2482 "vin1_field",
2483 "vin1_clkenb",
2484 "vin1_clk",
2485};
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2486#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2487
2488static const struct sh_pfc_function pinmux_functions[] = {
2489 SH_PFC_FUNCTION(avb),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2490#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2491 SH_PFC_FUNCTION(canfd0),
2492 SH_PFC_FUNCTION(canfd1),
2493 SH_PFC_FUNCTION(canfd_clk),
2494 SH_PFC_FUNCTION(du),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2495#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2496 SH_PFC_FUNCTION(gether),
2497 SH_PFC_FUNCTION(hscif0),
2498 SH_PFC_FUNCTION(hscif1),
2499 SH_PFC_FUNCTION(hscif2),
2500 SH_PFC_FUNCTION(hscif3),
2501 SH_PFC_FUNCTION(i2c0),
2502 SH_PFC_FUNCTION(i2c1),
2503 SH_PFC_FUNCTION(i2c2),
2504 SH_PFC_FUNCTION(i2c3),
2505 SH_PFC_FUNCTION(i2c4),
2506 SH_PFC_FUNCTION(i2c5),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2507#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2508 SH_PFC_FUNCTION(intc_ex),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2509#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2510 SH_PFC_FUNCTION(mmc),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2511#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2512 SH_PFC_FUNCTION(msiof0),
2513 SH_PFC_FUNCTION(msiof1),
2514 SH_PFC_FUNCTION(msiof2),
2515 SH_PFC_FUNCTION(msiof3),
2516 SH_PFC_FUNCTION(pwm0),
2517 SH_PFC_FUNCTION(pwm1),
2518 SH_PFC_FUNCTION(pwm2),
2519 SH_PFC_FUNCTION(pwm3),
2520 SH_PFC_FUNCTION(pwm4),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2521#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2522 SH_PFC_FUNCTION(qspi0),
2523 SH_PFC_FUNCTION(qspi1),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2524 SH_PFC_FUNCTION(rpc),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2525 SH_PFC_FUNCTION(scif0),
2526 SH_PFC_FUNCTION(scif1),
2527 SH_PFC_FUNCTION(scif3),
2528 SH_PFC_FUNCTION(scif4),
2529 SH_PFC_FUNCTION(scif_clk),
2530 SH_PFC_FUNCTION(tmu),
2531 SH_PFC_FUNCTION(tpu),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2532#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2533 SH_PFC_FUNCTION(vin0),
2534 SH_PFC_FUNCTION(vin1),
Marek Vasut06266242024-12-23 14:34:14 +0100[diff] [blame^]2535#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2536};
2537
2538static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2539#define F_(x, y) FN_##y
2540#define FM(x) FN_##x
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2541 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2542 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2544 GROUP(
2545 /* GP0_31_22 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2546 GP_0_21_FN, GPSR0_21,
2547 GP_0_20_FN, GPSR0_20,
2548 GP_0_19_FN, GPSR0_19,
2549 GP_0_18_FN, GPSR0_18,
2550 GP_0_17_FN, GPSR0_17,
2551 GP_0_16_FN, GPSR0_16,
2552 GP_0_15_FN, GPSR0_15,
2553 GP_0_14_FN, GPSR0_14,
2554 GP_0_13_FN, GPSR0_13,
2555 GP_0_12_FN, GPSR0_12,
2556 GP_0_11_FN, GPSR0_11,
2557 GP_0_10_FN, GPSR0_10,
2558 GP_0_9_FN, GPSR0_9,
2559 GP_0_8_FN, GPSR0_8,
2560 GP_0_7_FN, GPSR0_7,
2561 GP_0_6_FN, GPSR0_6,
2562 GP_0_5_FN, GPSR0_5,
2563 GP_0_4_FN, GPSR0_4,
2564 GP_0_3_FN, GPSR0_3,
2565 GP_0_2_FN, GPSR0_2,
2566 GP_0_1_FN, GPSR0_1,
2567 GP_0_0_FN, GPSR0_0, ))
2568 },
2569 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2570 0, 0,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 GP_1_27_FN, GPSR1_27,
2575 GP_1_26_FN, GPSR1_26,
2576 GP_1_25_FN, GPSR1_25,
2577 GP_1_24_FN, GPSR1_24,
2578 GP_1_23_FN, GPSR1_23,
2579 GP_1_22_FN, GPSR1_22,
2580 GP_1_21_FN, GPSR1_21,
2581 GP_1_20_FN, GPSR1_20,
2582 GP_1_19_FN, GPSR1_19,
2583 GP_1_18_FN, GPSR1_18,
2584 GP_1_17_FN, GPSR1_17,
2585 GP_1_16_FN, GPSR1_16,
2586 GP_1_15_FN, GPSR1_15,
2587 GP_1_14_FN, GPSR1_14,
2588 GP_1_13_FN, GPSR1_13,
2589 GP_1_12_FN, GPSR1_12,
2590 GP_1_11_FN, GPSR1_11,
2591 GP_1_10_FN, GPSR1_10,
2592 GP_1_9_FN, GPSR1_9,
2593 GP_1_8_FN, GPSR1_8,
2594 GP_1_7_FN, GPSR1_7,
2595 GP_1_6_FN, GPSR1_6,
2596 GP_1_5_FN, GPSR1_5,
2597 GP_1_4_FN, GPSR1_4,
2598 GP_1_3_FN, GPSR1_3,
2599 GP_1_2_FN, GPSR1_2,
2600 GP_1_1_FN, GPSR1_1,
2601 GP_1_0_FN, GPSR1_0, ))
2602 },
2603 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2604 0, 0,
2605 0, 0,
2606 GP_2_29_FN, GPSR2_29,
2607 GP_2_28_FN, GPSR2_28,
2608 GP_2_27_FN, GPSR2_27,
2609 GP_2_26_FN, GPSR2_26,
2610 GP_2_25_FN, GPSR2_25,
2611 GP_2_24_FN, GPSR2_24,
2612 GP_2_23_FN, GPSR2_23,
2613 GP_2_22_FN, GPSR2_22,
2614 GP_2_21_FN, GPSR2_21,
2615 GP_2_20_FN, GPSR2_20,
2616 GP_2_19_FN, GPSR2_19,
2617 GP_2_18_FN, GPSR2_18,
2618 GP_2_17_FN, GPSR2_17,
2619 GP_2_16_FN, GPSR2_16,
2620 GP_2_15_FN, GPSR2_15,
2621 GP_2_14_FN, GPSR2_14,
2622 GP_2_13_FN, GPSR2_13,
2623 GP_2_12_FN, GPSR2_12,
2624 GP_2_11_FN, GPSR2_11,
2625 GP_2_10_FN, GPSR2_10,
2626 GP_2_9_FN, GPSR2_9,
2627 GP_2_8_FN, GPSR2_8,
2628 GP_2_7_FN, GPSR2_7,
2629 GP_2_6_FN, GPSR2_6,
2630 GP_2_5_FN, GPSR2_5,
2631 GP_2_4_FN, GPSR2_4,
2632 GP_2_3_FN, GPSR2_3,
2633 GP_2_2_FN, GPSR2_2,
2634 GP_2_1_FN, GPSR2_1,
2635 GP_2_0_FN, GPSR2_0, ))
2636 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2637 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2638 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2639 1, 1, 1, 1, 1, 1),
2640 GROUP(
2641 /* GP3_31_17 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2642 GP_3_16_FN, GPSR3_16,
2643 GP_3_15_FN, GPSR3_15,
2644 GP_3_14_FN, GPSR3_14,
2645 GP_3_13_FN, GPSR3_13,
2646 GP_3_12_FN, GPSR3_12,
2647 GP_3_11_FN, GPSR3_11,
2648 GP_3_10_FN, GPSR3_10,
2649 GP_3_9_FN, GPSR3_9,
2650 GP_3_8_FN, GPSR3_8,
2651 GP_3_7_FN, GPSR3_7,
2652 GP_3_6_FN, GPSR3_6,
2653 GP_3_5_FN, GPSR3_5,
2654 GP_3_4_FN, GPSR3_4,
2655 GP_3_3_FN, GPSR3_3,
2656 GP_3_2_FN, GPSR3_2,
2657 GP_3_1_FN, GPSR3_1,
2658 GP_3_0_FN, GPSR3_0, ))
2659 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2660 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2661 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2663 1, 1),
2664 GROUP(
2665 /* GP4_31_25 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2666 GP_4_24_FN, GPSR4_24,
2667 GP_4_23_FN, GPSR4_23,
2668 GP_4_22_FN, GPSR4_22,
2669 GP_4_21_FN, GPSR4_21,
2670 GP_4_20_FN, GPSR4_20,
2671 GP_4_19_FN, GPSR4_19,
2672 GP_4_18_FN, GPSR4_18,
2673 GP_4_17_FN, GPSR4_17,
2674 GP_4_16_FN, GPSR4_16,
2675 GP_4_15_FN, GPSR4_15,
2676 GP_4_14_FN, GPSR4_14,
2677 GP_4_13_FN, GPSR4_13,
2678 GP_4_12_FN, GPSR4_12,
2679 GP_4_11_FN, GPSR4_11,
2680 GP_4_10_FN, GPSR4_10,
2681 GP_4_9_FN, GPSR4_9,
2682 GP_4_8_FN, GPSR4_8,
2683 GP_4_7_FN, GPSR4_7,
2684 GP_4_6_FN, GPSR4_6,
2685 GP_4_5_FN, GPSR4_5,
2686 GP_4_4_FN, GPSR4_4,
2687 GP_4_3_FN, GPSR4_3,
2688 GP_4_2_FN, GPSR4_2,
2689 GP_4_1_FN, GPSR4_1,
2690 GP_4_0_FN, GPSR4_0, ))
2691 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2692 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2693 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2694 1, 1, 1, 1),
2695 GROUP(
2696 /* GP5_31_15 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2697 GP_5_14_FN, GPSR5_14,
2698 GP_5_13_FN, GPSR5_13,
2699 GP_5_12_FN, GPSR5_12,
2700 GP_5_11_FN, GPSR5_11,
2701 GP_5_10_FN, GPSR5_10,
2702 GP_5_9_FN, GPSR5_9,
2703 GP_5_8_FN, GPSR5_8,
2704 GP_5_7_FN, GPSR5_7,
2705 GP_5_6_FN, GPSR5_6,
2706 GP_5_5_FN, GPSR5_5,
2707 GP_5_4_FN, GPSR5_4,
2708 GP_5_3_FN, GPSR5_3,
2709 GP_5_2_FN, GPSR5_2,
2710 GP_5_1_FN, GPSR5_1,
2711 GP_5_0_FN, GPSR5_0, ))
2712 },
2713#undef F_
2714#undef FM
2715
2716#define F_(x, y) x,
2717#define FM(x) FN_##x,
2718 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2719 IP0_31_28
2720 IP0_27_24
2721 IP0_23_20
2722 IP0_19_16
2723 IP0_15_12
2724 IP0_11_8
2725 IP0_7_4
2726 IP0_3_0 ))
2727 },
2728 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2729 IP1_31_28
2730 IP1_27_24
2731 IP1_23_20
2732 IP1_19_16
2733 IP1_15_12
2734 IP1_11_8
2735 IP1_7_4
2736 IP1_3_0 ))
2737 },
2738 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2739 IP2_31_28
2740 IP2_27_24
2741 IP2_23_20
2742 IP2_19_16
2743 IP2_15_12
2744 IP2_11_8
2745 IP2_7_4
2746 IP2_3_0 ))
2747 },
2748 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2749 IP3_31_28
2750 IP3_27_24
2751 IP3_23_20
2752 IP3_19_16
2753 IP3_15_12
2754 IP3_11_8
2755 IP3_7_4
2756 IP3_3_0 ))
2757 },
2758 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2759 IP4_31_28
2760 IP4_27_24
2761 IP4_23_20
2762 IP4_19_16
2763 IP4_15_12
2764 IP4_11_8
2765 IP4_7_4
2766 IP4_3_0 ))
2767 },
2768 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2769 IP5_31_28
2770 IP5_27_24
2771 IP5_23_20
2772 IP5_19_16
2773 IP5_15_12
2774 IP5_11_8
2775 IP5_7_4
2776 IP5_3_0 ))
2777 },
2778 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2779 IP6_31_28
2780 IP6_27_24
2781 IP6_23_20
2782 IP6_19_16
2783 IP6_15_12
2784 IP6_11_8
2785 IP6_7_4
2786 IP6_3_0 ))
2787 },
2788 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2789 IP7_31_28
2790 IP7_27_24
2791 IP7_23_20
2792 IP7_19_16
2793 IP7_15_12
2794 IP7_11_8
2795 IP7_7_4
2796 IP7_3_0 ))
2797 },
2798 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2799 IP8_31_28
2800 IP8_27_24
2801 IP8_23_20
2802 IP8_19_16
2803 IP8_15_12
2804 IP8_11_8
2805 IP8_7_4
2806 IP8_3_0 ))
2807 },
2808 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2809 IP9_31_28
2810 IP9_27_24
2811 IP9_23_20
2812 IP9_19_16
2813 IP9_15_12
2814 IP9_11_8
2815 IP9_7_4
2816 IP9_3_0 ))
2817 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2818 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2819 GROUP(-12, 4, 4, 4, 4, 4),
2820 GROUP(
2821 /* IP10_31_20 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2822 IP10_19_16
2823 IP10_15_12
2824 IP10_11_8
2825 IP10_7_4
2826 IP10_3_0 ))
2827 },
2828#undef F_
2829#undef FM
2830
2831#define F_(x, y) x,
2832#define FM(x) FN_##x,
2833 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2834 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2835 GROUP(
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2836 /* RESERVED 31-12 */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2837 MOD_SEL0_11
2838 MOD_SEL0_10
2839 MOD_SEL0_9
2840 MOD_SEL0_8
2841 MOD_SEL0_7
2842 MOD_SEL0_6
2843 MOD_SEL0_5
2844 MOD_SEL0_4
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2845 /* RESERVED 3 */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2846 MOD_SEL0_2
2847 MOD_SEL0_1
2848 MOD_SEL0_0 ))
2849 },
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2850 { /* sentinel */ }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2851};
2852
2853enum ioctrl_regs {
2854 POCCTRL0,
2855 POCCTRL1,
2856 POCCTRL2,
2857 POCCTRL3,
2858 TDSELCTRL,
2859};
2860
2861static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2862 [POCCTRL0] = { 0xe6060380, },
2863 [POCCTRL1] = { 0xe6060384, },
2864 [POCCTRL2] = { 0xe6060388, },
2865 [POCCTRL3] = { 0xe606038c, },
2866 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2867 { /* sentinel */ }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2868};
2869
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2870static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2871{
2872 int bit = pin & 0x1f;
2873
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2874 switch (pin) {
2875 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2876 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2877 return bit;
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2878
2879 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2880 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2881 return bit + 22;
2882
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2883 case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2884 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2885 return bit - 10;
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2886
2887 case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
2888 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
2889 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2890 return bit + 7;
2891
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2892 case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
2893 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2894 return pin - 25;
2895
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2896 case PIN_VDDQ_AVB:
2897 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2898 return 0;
2899
2900 case PIN_VDDQ_GE:
2901 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2902 return 1;
2903
2904 default:
2905 return -EINVAL;
2906 }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2907}
2908
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2909static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2910 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2911 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2912 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2913 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2914 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2915 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2916 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2917 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2918 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2919 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2920 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2921 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2922 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2923 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2924 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2925 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2926 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2927 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2928 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2929 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2930 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2931 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2932 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2933 [22] = SH_PFC_PIN_NONE,
2934 [23] = SH_PFC_PIN_NONE,
2935 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
2936 [25] = SH_PFC_PIN_NONE,
2937 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */
2938 [27] = SH_PFC_PIN_NONE,
2939 [28] = SH_PFC_PIN_NONE,
2940 [29] = SH_PFC_PIN_NONE,
2941 [30] = PIN_EXTALR, /* EXTALR */
2942 [31] = PIN_FSCLKST_N, /* FSCLKST# */
2943 } },
2944 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2945 [ 0] = PIN_FSCLKST, /* FSCLKST */
2946 [ 1] = SH_PFC_PIN_NONE,
2947 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2948 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */
2949 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
2950 [ 5] = PIN_DCUTMS, /* DCUTMS */
2951 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
2952 [ 7] = SH_PFC_PIN_NONE,
2953 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2954 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2955 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
2956 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
2957 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
2958 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
2959 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
2960 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
2961 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
2962 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2963 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2964 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
2965 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
2966 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
2967 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
2968 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
2969 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
2970 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2971 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
2972 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
2973 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
2974 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
2975 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
2976 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
2977 } },
2978 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2979 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2980 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
2981 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2982 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
2983 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
2984 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
2985 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
2986 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
2987 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
2988 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2989 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */
2990 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */
2991 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */
2992 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */
2993 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */
2994 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */
2995 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
2996 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
2997 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
2998 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
2999 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
3000 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
3001 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
3002 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
3003 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
3004 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
3005 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
3006 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
3007 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
3008 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
3009 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
3010 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
3011 } },
3012 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
3013 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
3014 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
3015 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
3016 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
3017 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
3018 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
3019 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
3020 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
3021 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
3022 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
3023 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
3024 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
3025 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
3026 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
3027 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
3028 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
3029 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
3030 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
3031 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
3032 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
3033 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
3034 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
3035 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
3036 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
3037 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
3038 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
3039 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
3040 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
3041 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
3042 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
3043 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
3044 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
3045 } },
3046 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3047 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
3048 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
3049 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
3050 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
3051 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
3052 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
3053 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
3054 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
3055 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
3056 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
3057 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
3058 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
3059 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
3060 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
3061 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
3062 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */
3063 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */
3064 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
3065 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
3066 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
3067 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
3068 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
3069 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
3070 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
3071 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
3072 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
3073 [26] = SH_PFC_PIN_NONE,
3074 [27] = SH_PFC_PIN_NONE,
3075 [28] = SH_PFC_PIN_NONE,
3076 [29] = SH_PFC_PIN_NONE,
3077 [30] = SH_PFC_PIN_NONE,
3078 [31] = SH_PFC_PIN_NONE,
3079 } },
3080 { /* sentinel */ }
3081};
3082
3083static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3084 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3085 .get_bias = rcar_pinmux_get_bias,
3086 .set_bias = rcar_pinmux_set_bias,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3087};
3088
3089const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3090 .name = "r8a77980_pfc",
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3091 .ops = &r8a77980_pfc_ops,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3092 .unlock_reg = 0xe6060000, /* PMMR */
3093
3094 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3095
3096 .pins = pinmux_pins,
3097 .nr_pins = ARRAY_SIZE(pinmux_pins),
3098 .groups = pinmux_groups,
3099 .nr_groups = ARRAY_SIZE(pinmux_groups),
3100 .functions = pinmux_functions,
3101 .nr_functions = ARRAY_SIZE(pinmux_functions),
3102
3103 .cfg_regs = pinmux_config_regs,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3104 .bias_regs = pinmux_bias_regs,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3105 .ioctrl_regs = pinmux_ioctrl_regs,
3106
3107 .pinmux_data = pinmux_data,
3108 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3109};