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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peter Howard9ed4f702015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da850evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howard9ed4f702015-03-23 09:19:56 +11009 */
10
11#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060012#include <env.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110013#include <i2c.h>
14#include <net.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110015#include <asm/arch/hardware.h>
16#include <asm/ti-common/davinci_nand.h>
17#include <asm/io.h>
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +020018#include <ns16550.h>
19#include <dm/platdata.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060021#include <asm/mach-types.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110022#include <asm/arch/davinci_misc.h>
Masahiro Yamadab2c88682017-01-10 13:32:07 +090023#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110024#include <mmc.h>
25#include <asm/arch/sdmmc_defs.h>
26#endif
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
31
Masahiro Yamadab2c88682017-01-10 13:32:07 +090032#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110033/* MMC0 pin muxer settings */
34const struct pinmux_config mmc0_pins[] = {
35 /* GP0[11] is required for SD to work on Rev 3 EVMs */
36 { pinmux(0), 8, 4 }, /* GP0[11] */
37 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
38 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
39 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
40 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
41 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
42 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
43 /* LCDK supports only 4-bit mode, remaining pins are not configured */
44};
45#endif
46
47/* UART pin muxer settings */
48static const struct pinmux_config uart_pins[] = {
49 { pinmux(0), 4, 6 },
50 { pinmux(0), 4, 7 },
51 { pinmux(4), 2, 4 },
52 { pinmux(4), 2, 5 }
53};
54
55#ifdef CONFIG_DRIVER_TI_EMAC
56static const struct pinmux_config emac_pins[] = {
57 { pinmux(2), 8, 1 },
58 { pinmux(2), 8, 2 },
59 { pinmux(2), 8, 3 },
60 { pinmux(2), 8, 4 },
61 { pinmux(2), 8, 5 },
62 { pinmux(2), 8, 6 },
63 { pinmux(2), 8, 7 },
64 { pinmux(3), 8, 0 },
65 { pinmux(3), 8, 1 },
66 { pinmux(3), 8, 2 },
67 { pinmux(3), 8, 3 },
68 { pinmux(3), 8, 4 },
69 { pinmux(3), 8, 5 },
70 { pinmux(3), 8, 6 },
71 { pinmux(3), 8, 7 },
72 { pinmux(4), 8, 0 },
73 { pinmux(4), 8, 1 }
74};
75#endif /* CONFIG_DRIVER_TI_EMAC */
76
77/* I2C pin muxer settings */
78static const struct pinmux_config i2c_pins[] = {
79 { pinmux(4), 2, 2 },
80 { pinmux(4), 2, 3 }
81};
82
83#ifdef CONFIG_NAND_DAVINCI
84const struct pinmux_config nand_pins[] = {
85 { pinmux(7), 1, 1 },
86 { pinmux(7), 1, 2 },
87 { pinmux(7), 1, 4 },
88 { pinmux(7), 1, 5 },
89 { pinmux(8), 1, 0 },
90 { pinmux(8), 1, 1 },
91 { pinmux(8), 1, 2 },
92 { pinmux(8), 1, 3 },
93 { pinmux(8), 1, 4 },
94 { pinmux(8), 1, 5 },
95 { pinmux(8), 1, 6 },
96 { pinmux(8), 1, 7 },
97 { pinmux(9), 1, 0 },
98 { pinmux(9), 1, 1 },
99 { pinmux(9), 1, 2 },
100 { pinmux(9), 1, 3 },
101 { pinmux(9), 1, 4 },
102 { pinmux(9), 1, 5 },
103 { pinmux(9), 1, 6 },
104 { pinmux(9), 1, 7 },
105 { pinmux(12), 1, 5 },
106 { pinmux(12), 1, 6 }
107};
108
109#endif
110
111#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
112#define HAS_RMII 1
113#else
114#define HAS_RMII 0
115#endif
116
117const struct pinmux_resource pinmuxes[] = {
118 PINMUX_ITEM(uart_pins),
119 PINMUX_ITEM(i2c_pins),
120#ifdef CONFIG_NAND_DAVINCI
121 PINMUX_ITEM(nand_pins),
122#endif
123};
124
125const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
126
127const struct lpsc_resource lpsc[] = {
128 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
129 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
130 { DAVINCI_LPSC_EMAC }, /* image download */
131 { DAVINCI_LPSC_UART2 }, /* console */
132 { DAVINCI_LPSC_GPIO },
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900133#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100134 { DAVINCI_LPSC_MMC_SD },
135#endif
136};
137
138const int lpsc_size = ARRAY_SIZE(lpsc);
139
140#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
141#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
142#endif
143
144/*
145 * get_board_rev() - setup to pass kernel board revision information
146 * Returns:
147 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
148 * 0000b - 300 MHz
149 * 0001b - 372 MHz
150 * 0010b - 408 MHz
151 * 0011b - 456 MHz
152 */
153u32 get_board_rev(void)
154{
155 return 0;
156}
157
158int board_early_init_f(void)
159{
160 /*
161 * Power on required peripherals
162 * ARM does not have access by default to PSC0 and PSC1
163 * assuming here that the DSP bootloader has set the IOPU
164 * such that PSC access is available to ARM
165 */
166 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
167 return 1;
168
169 return 0;
170}
171
172int board_init(void)
173{
Peter Howard9ed4f702015-03-23 09:19:56 +1100174 irq_init();
Peter Howard9ed4f702015-03-23 09:19:56 +1100175
Tom Rini48157342017-01-25 20:42:35 -0500176 /* arch number of the board */
177 gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
178
Peter Howard9ed4f702015-03-23 09:19:56 +1100179 /* address of boot parameters */
180 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
181
182
183 /* setup the SUSPSRC for ARM to control emulation suspend */
184 writel(readl(&davinci_syscfg_regs->suspsrc) &
185 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
186 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
187 DAVINCI_SYSCFG_SUSPSRC_UART2),
188 &davinci_syscfg_regs->suspsrc);
189
190 /* configure pinmux settings */
191 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
192 return 1;
193
194#ifdef CONFIG_NAND_DAVINCI
195 /*
196 * NAND CS setup - cycle counts based on da850evm NAND timings in the
197 * Linux kernel @ 25MHz EMIFA
198 */
199 writel((DAVINCI_ABCR_WSETUP(15) |
200 DAVINCI_ABCR_WSTROBE(63) |
201 DAVINCI_ABCR_WHOLD(7) |
202 DAVINCI_ABCR_RSETUP(15) |
203 DAVINCI_ABCR_RSTROBE(63) |
204 DAVINCI_ABCR_RHOLD(7) |
205 DAVINCI_ABCR_TA(3) |
206 DAVINCI_ABCR_ASIZE_16BIT),
207 &davinci_emif_regs->ab2cr); /* CS3 */
208#endif
209
210
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900211#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100212 if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
213 return 1;
214#endif
215
216#ifdef CONFIG_DRIVER_TI_EMAC
217 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
218 return 1;
219 davinci_emac_mii_mode_sel(HAS_RMII);
220#endif /* CONFIG_DRIVER_TI_EMAC */
221
222 /* enable the console UART */
223 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
224 DAVINCI_UART_PWREMU_MGMT_UTRST),
225 &davinci_uart2_ctrl_regs->pwremu_mgmt);
226
227 return 0;
228}
229
Peter Howard9ed4f702015-03-23 09:19:56 +1100230#define CFG_MAC_ADDR_SPI_BUS 0
231#define CFG_MAC_ADDR_SPI_CS 0
232#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
233#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
234
235#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
236
237static int get_mac_addr(u8 *addr)
238{
239 /* Need to find a way to get MAC ADDRESS */
240 return 0;
241}
242
243void dsp_lpsc_on(unsigned domain, unsigned int id)
244{
245 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
246 struct davinci_psc_regs *psc_regs;
247
248 psc_regs = davinci_psc0_regs;
249 mdstat = &psc_regs->psc0.mdstat[id];
250 mdctl = &psc_regs->psc0.mdctl[id];
251 ptstat = &psc_regs->ptstat;
252 ptcmd = &psc_regs->ptcmd;
253
254 while (*ptstat & (0x1 << domain))
255 ;
256
257 if ((*mdstat & 0x1f) == 0x03)
258 return; /* Already on and enabled */
259
260 *mdctl |= 0x03;
261
262 *ptcmd = 0x1 << domain;
263
264 while (*ptstat & (0x1 << domain))
265 ;
266 while ((*mdstat & 0x1f) != 0x03)
267 ; /* Probably an overkill... */
268}
269
270static void dspwake(void)
271{
272 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
273
274 /* if the device is ARM only, return */
275 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
276 return;
277
Simon Glass64b723f2017-08-03 12:22:12 -0600278 if (!strcmp(env_get("dspwake"), "no"))
Peter Howard9ed4f702015-03-23 09:19:56 +1100279 return;
280
281 *resetvect++ = 0x1E000; /* DSP Idle */
282 /* clear out the next 10 words as NOP */
283 memset(resetvect, 0, sizeof(unsigned) * 10);
284
285 /* setup the DSP reset vector */
286 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
287
288 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
289 REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
290}
291
292#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
293/**
294 * rmii_hw_init
295 *
296 */
297int rmii_hw_init(void)
298{
299 return 0;
300}
301#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
302
303int misc_init_r(void)
304{
305 uint8_t tmp[20], addr[10];
306
307
Simon Glass64b723f2017-08-03 12:22:12 -0600308 if (env_get("ethaddr") == NULL) {
Peter Howard9ed4f702015-03-23 09:19:56 +1100309 /* Read Ethernet MAC address from EEPROM */
310 if (dvevm_read_mac_address(addr)) {
311 /* Set Ethernet MAC address from EEPROM */
312 davinci_sync_env_enetaddr(addr);
313 } else {
314 get_mac_addr(addr);
315 }
316
Fabien Parenteceb18f2016-11-10 17:16:35 +0100317 if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
318 sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
319 addr[0], addr[1], addr[2], addr[3], addr[4],
320 addr[5]);
321
Simon Glass6a38e412017-08-03 12:22:09 -0600322 env_set("ethaddr", (char *)tmp);
Fabien Parenteceb18f2016-11-10 17:16:35 +0100323 } else {
Peter Howard9ed4f702015-03-23 09:19:56 +1100324 printf("Invalid MAC address read.\n");
Peter Howard9ed4f702015-03-23 09:19:56 +1100325 }
Peter Howard9ed4f702015-03-23 09:19:56 +1100326 }
Fabien Parenteceb18f2016-11-10 17:16:35 +0100327
Peter Howard9ed4f702015-03-23 09:19:56 +1100328#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
329 /* Select RMII fucntion through the expander */
330 if (rmii_hw_init())
331 printf("RMII hardware init failed!!!\n");
332#endif
333
334 dspwake();
335
336 return 0;
337}
338
Sekhar Norib8545762019-05-30 19:04:54 +0530339#if !CONFIG_IS_ENABLED(DM_MMC)
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900340#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100341static struct davinci_mmc mmc_sd0 = {
342 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
343 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
344 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
345 .version = MMC_CTLR_VERSION_2,
346};
347
348int board_mmc_init(bd_t *bis)
349{
350 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
351
352 /* Add slot-0 to mmc subsystem */
353 return davinci_mmc_init(bis, &mmc_sd0);
354}
355#endif
Adam Fordd4df8142018-08-09 06:15:14 -0500356#endif
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200357
358#ifdef CONFIG_SPL_BUILD
359static const struct ns16550_platdata serial_pdata = {
360 .base = DAVINCI_UART2_BASE,
361 .reg_shift = 2,
362 .clock = 228000000,
363 .fcr = UART_FCR_DEFVAL,
364};
365
366U_BOOT_DEVICE(omapl138_uart) = {
367 .name = "ns16550_serial",
368 .platdata = &serial_pdata,
369};
370#endif