Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 3 | Kontron SMARC-sAL28 |
| 4 | =================== |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 5 | |
| 6 | The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 |
| 7 | processor module with an on-chip 6-port TSN switch and a 3D GPU. |
| 8 | |
| 9 | |
| 10 | Quickstart |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 11 | ---------- |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 12 | |
| 13 | Compile U-Boot |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 14 | ^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 15 | |
| 16 | Configure and compile the binary:: |
| 17 | |
| 18 | $ make kontron_sl28_defconfig |
| 19 | $ CROSS_COMPILE=aarch64-linux-gnu make |
| 20 | |
| 21 | Copy u-boot.rom to a TFTP server. |
| 22 | |
| 23 | Install the bootloader on the board |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 24 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 25 | |
| 26 | Please note, this bootloader doesn't support the builtin watchdog (yet), |
| 27 | therefore you have to disable it, see below. Otherwise you'll end up in |
| 28 | the failsafe bootloader on every reset:: |
| 29 | |
| 30 | > tftp path/to/u-boot.rom |
| 31 | > sf probe 0 |
| 32 | > sf update $fileaddr 0x210000 $filesize |
| 33 | |
| 34 | The board is fully failsafe, you can't break anything. But because you've |
| 35 | disabled the builtin watchdog you might have to manually enter failsafe |
| 36 | mode by asserting the ``FORCE_RECOV#`` line during board reset. |
| 37 | |
Michael Walle | 53c7bfa | 2021-09-29 13:39:13 +0200 | [diff] [blame] | 38 | Update image |
| 39 | ------------ |
| 40 | |
| 41 | After the build finished, there will be an update image called |
| 42 | u-boot.update. This can either be used in the DFU mode (which isn't |
| 43 | supported yet) or encapsulated in an EFI UpdateCapsule. |
| 44 | |
| 45 | To build the capsule use the following command |
| 46 | |
| 47 | $ tools/mkeficapsule -f u-boot.update -i 1 UpdateUboot |
| 48 | |
| 49 | Afterward you can copy this file to your ESP into the /EFI/UpdateCapsule/ |
| 50 | folder. On the next EFI boot this will automatically update your |
| 51 | bootloader. |
| 52 | |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 53 | Useful I2C tricks |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 54 | ----------------- |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 55 | |
| 56 | The board has a board management controller which is not supported in |
| 57 | u-boot (yet). But you can use the i2c command to access it. |
| 58 | |
| 59 | - reset into failsafe bootloader:: |
| 60 | |
| 61 | > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42 |
| 62 | |
| 63 | - read board management controller version:: |
| 64 | |
| 65 | > i2c md 4a 3.1 1 |
| 66 | |
Michael Walle | fa84201 | 2021-11-15 23:45:43 +0100 | [diff] [blame] | 67 | |
| 68 | Builtin watchdog |
| 69 | ---------------- |
| 70 | |
| 71 | The builtin watchdog will supervise the bootloader startup. If anything |
| 72 | goes wrong it will reset the board and boot into the failsafe bootloader. |
| 73 | |
| 74 | Once the bootloader is started successfully, it will disable the watchdog |
| 75 | timer. |
| 76 | |
| 77 | wdt command flags |
| 78 | ^^^^^^^^^^^^^^^^^ |
| 79 | |
| 80 | The `wdt start` as well as the `wdt expire` command take a flags argument. |
| 81 | The supported bitmask is as follows. |
| 82 | |
| 83 | | Bit | Description | |
| 84 | | --- | ----------------------------- | |
| 85 | | 0 | Enable failsafe mode | |
| 86 | | 1 | Lock the control register | |
| 87 | | 2 | Disable board reset | |
| 88 | | 3 | Enable WDT_TIME_OUT# line | |
| 89 | |
| 90 | For example, you can use `wdt expire 1` to issue a reset and boot into the |
| 91 | failsafe bootloader. |
| 92 | |
| 93 | Disable the builtin watchdog |
| 94 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 95 | |
| 96 | If for some reason, this isn't a desired behavior, the watchdog can also |
| 97 | be configured to not be enabled on board reset. It's configuration is saved |
| 98 | in the non-volatile board configuration bits. To change these you can use |
| 99 | the `sl28 nvm` command. |
| 100 | |
| 101 | For more information on the non-volatile board configuration bits, see the |
| 102 | following section. |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 103 | |
| 104 | Non-volatile Board Configuration Bits |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 105 | ------------------------------------- |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 106 | |
| 107 | The board has 16 configuration bits which are stored in the CPLD and are |
| 108 | non-volatile. These can be changed by the `sl28 nvm` command. |
| 109 | |
| 110 | === =============================================================== |
| 111 | Bit Description |
| 112 | === =============================================================== |
| 113 | 0 Power-on inhibit |
| 114 | 1 Enable eMMC boot |
| 115 | 2 Enable watchdog by default |
| 116 | 3 Disable failsafe watchdog by default |
| 117 | 4 Clock generator selection bit 0 |
| 118 | 5 Clock generator selection bit 1 |
| 119 | 6 Disable CPU SerDes clock #2 and PCIe-A clock output |
| 120 | 7 Disable PCIe-B and PCIe-C clock output |
| 121 | 8 Keep onboard PHYs in reset |
| 122 | 9 Keep USB hub in reset |
| 123 | 10 Keep eDP-to-LVDS converter in reset |
| 124 | 11 Enable I2C stuck recovery on I2C PM and I2C GP busses |
| 125 | 12 Enable automatic onboard PHY H/W reset |
| 126 | 13 reserved |
| 127 | 14 Used by the RCW to determine boot source |
| 128 | 15 Used by the RCW to determine boot source |
| 129 | === =============================================================== |
| 130 | |
| 131 | Please note, that if the board is in failsafe mode, the bits will have the |
| 132 | factory defaults, ie. all bits are off. |
| 133 | |
| 134 | Power-On Inhibit |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 135 | ^^^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 136 | |
| 137 | If this is set, the board doesn't automatically turn on when power is |
| 138 | applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or |
| 139 | use any other wake-up source such as RTC alarm or Wake-on-LAN. |
| 140 | |
| 141 | eMMC Boot |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 142 | ^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 143 | |
| 144 | If this is set, the RCW will be fetched from the on-board eMMC at offset |
| 145 | 1MiB. For further details, have a look at the `Reset Configuration Word |
| 146 | Documentation`_. |
| 147 | |
| 148 | Watchdog |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 149 | ^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 150 | |
| 151 | By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and |
| 152 | 3, the user can change its mode or disable it altogether. |
| 153 | |
| 154 | ===== ===== =============================== |
| 155 | Bit 2 Bit 3 Description |
| 156 | ===== ===== =============================== |
| 157 | 0 0 Watchdog enabled, failsafe mode |
| 158 | 0 1 Watchdog disabled |
| 159 | 1 0 Watchdog enabled, failsafe mode |
| 160 | 1 1 Watchdog enabled, normal mode |
| 161 | ===== ===== =============================== |
| 162 | |
| 163 | Clock Generator Select |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 164 | ^^^^^^^^^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 165 | |
| 166 | The board is prepared to supply different SerDes clock speeds. But for now, |
| 167 | only setting 0 is supported, otherwise the CPU will hang because the PLL |
| 168 | will not lock. |
| 169 | |
| 170 | Clock Output Disable And Keep Devices In Reset |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 171 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 172 | |
| 173 | To safe power, the user might disable different devices and clock output of |
| 174 | the board. It is not supported to disable the "CPU SerDes clock #2" for |
| 175 | now, otherwise the CPU will hang because the PLL will not lock. |
| 176 | |
| 177 | Automatic reset of the onboard PHYs |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 178 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 179 | |
| 180 | By default, there is no hardware reset of the onboard PHY. This is because |
| 181 | for Wake-on-LAN, some registers have to retain their values. If you don't |
| 182 | use the WOL feature and a soft reset of the PHY is not enough you can |
| 183 | enable the hardware reset. The onboard PHY hardware reset follows the |
| 184 | power-on reset. |
| 185 | |
| 186 | |
| 187 | Further documentation |
Frieder Schrempf | 215c72f | 2021-09-29 13:39:12 +0200 | [diff] [blame] | 188 | --------------------- |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 189 | |
| 190 | - `Vendor Documentation`_ |
| 191 | - `Reset Configuration Word Documentation`_ |
| 192 | |
| 193 | .. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md |
| 194 | .. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md |