blob: 812088f3794641ea4d8ada973cde2e33a116466a [file] [log] [blame]
Heiko Schocherf1084d62011-11-01 20:00:31 +00001/*
2 * Copyright (C) 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherf1084d62011-11-01 20:00:31 +00006 */
7#ifndef _DV_SYSCFG_DEFS_H_
8#define _DV_SYSCFG_DEFS_H_
9
10#ifndef CONFIG_SOC_DA8XX
11/* System Control Module register structure for DM365 */
12struct dv_sys_module_regs {
13 unsigned int pinmux[5]; /* 0x00 */
14 unsigned int bootcfg; /* 0x14 */
15 unsigned int arm_intmux; /* 0x18 */
16 unsigned int edma_evtmux; /* 0x1C */
17 unsigned int ddr_slew; /* 0x20 */
18 unsigned int clkout; /* 0x24 */
19 unsigned int device_id; /* 0x28 */
20 unsigned int vdac_config; /* 0x2C */
21 unsigned int timer64_ctl; /* 0x30 */
22 unsigned int usbbphy_ctl; /* 0x34 */
23 unsigned int misc; /* 0x38 */
24 unsigned int mstpri[2]; /* 0x3C */
25 unsigned int vpss_clkctl; /* 0x44 */
26 unsigned int peri_clkctl; /* 0x48 */
27 unsigned int deepsleep; /* 0x4C */
28 unsigned int dft_enable; /* 0x50 */
29 unsigned int debounce[8]; /* 0x54 */
30 unsigned int vtpiocr; /* 0x74 */
31 unsigned int pupdctl0; /* 0x78 */
32 unsigned int pupdctl1; /* 0x7C */
33 unsigned int hdimcopbt; /* 0x80 */
34 unsigned int pll0_config; /* 0x84 */
35 unsigned int pll1_config; /* 0x88 */
36};
37
38#define VPTIO_RDY (1 << 15)
39#define VPTIO_IOPWRDN (1 << 14)
40#define VPTIO_CLRZ (1 << 13)
41#define VPTIO_LOCK (1 << 7)
42#define VPTIO_PWRDN (1 << 6)
43
44#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
45
46#define dv_sys_module_regs \
47 ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
48
49#endif /* !CONFIG_SOC_DA8XX */
50#endif /* _DV_SYSCFG_DEFS_H_ */