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Michal Simek090a2d72018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simek5fc61c82016-04-07 15:58:23 +02002/*
3 * dts file for Xilinx ZynqMP ZCU102 RevB
4 *
Michal Simek090a2d72018-03-27 10:36:39 +02005 * (C) Copyright 2016 - 2018, Xilinx, Inc.
Michal Simek5fc61c82016-04-07 15:58:23 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simek5fc61c82016-04-07 15:58:23 +02008 */
9
Michal Simek40d839a2017-07-20 12:38:27 +020010#include "zynqmp-zcu102-revA.dts"
Michal Simek5fc61c82016-04-07 15:58:23 +020011
12/ {
13 model = "ZynqMP ZCU102 RevB";
Michal Simek56c91422017-11-02 10:22:27 +010014 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Michal Simek5fc61c82016-04-07 15:58:23 +020015};
16
17&gem3 {
18 phy-handle = <&phyc>;
19 phyc: phy@c {
20 reg = <0xc>;
21 ti,rx-internal-delay = <0x8>;
22 ti,tx-internal-delay = <0xa>;
23 ti,fifo-depth = <0x1>;
24 };
25 /* Cleanup from RevA */
26 /delete-node/ phy@21;
27};
28
Michal Simek5fc61c82016-04-07 15:58:23 +020029/* Fix collision with u61 */
30&i2c0 {
Michal Simek2fde09e2018-03-27 10:38:08 +020031 i2c-mux@75 {
Michal Simek5fc61c82016-04-07 15:58:23 +020032 i2c@2 {
33 max15303@1b { /* u8 */
Michal Simekcba5b322018-03-27 10:52:40 +020034 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +020035 reg = <0x1b>;
36 };
37 /delete-node/ max15303@20;
38 };
39 };
40};