Michal Simek | 090a2d7 | 2018-03-27 10:36:39 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 2 | /* |
| 3 | * dts file for Xilinx ZynqMP ZCU102 RevB |
| 4 | * |
Michal Simek | 090a2d7 | 2018-03-27 10:36:39 +0200 | [diff] [blame] | 5 | * (C) Copyright 2016 - 2018, Xilinx, Inc. |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 6 | * |
| 7 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
Michal Simek | 40d839a | 2017-07-20 12:38:27 +0200 | [diff] [blame] | 10 | #include "zynqmp-zcu102-revA.dts" |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 11 | |
| 12 | / { |
| 13 | model = "ZynqMP ZCU102 RevB"; |
Michal Simek | 56c9142 | 2017-11-02 10:22:27 +0100 | [diff] [blame] | 14 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 15 | }; |
| 16 | |
| 17 | &gem3 { |
| 18 | phy-handle = <&phyc>; |
| 19 | phyc: phy@c { |
| 20 | reg = <0xc>; |
| 21 | ti,rx-internal-delay = <0x8>; |
| 22 | ti,tx-internal-delay = <0xa>; |
| 23 | ti,fifo-depth = <0x1>; |
| 24 | }; |
| 25 | /* Cleanup from RevA */ |
| 26 | /delete-node/ phy@21; |
| 27 | }; |
| 28 | |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 29 | /* Fix collision with u61 */ |
| 30 | &i2c0 { |
Michal Simek | 2fde09e | 2018-03-27 10:38:08 +0200 | [diff] [blame] | 31 | i2c-mux@75 { |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 32 | i2c@2 { |
| 33 | max15303@1b { /* u8 */ |
Michal Simek | cba5b32 | 2018-03-27 10:52:40 +0200 | [diff] [blame] | 34 | compatible = "maxim,max15303"; |
Michal Simek | 5fc61c8 | 2016-04-07 15:58:23 +0200 | [diff] [blame] | 35 | reg = <0x1b>; |
| 36 | }; |
| 37 | /delete-node/ max15303@20; |
| 38 | }; |
| 39 | }; |
| 40 | }; |