| Sean Anderson | 998e218 | 2022-03-22 16:59:10 -0400 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | LS1046ARDB |
| 4 | ========== |
| 5 | |
| 6 | The LS1046A Reference Design Board (RDB) is a high-performance computing, |
| 7 | evaluation, and development platform that supports the QorIQ LS1046A |
| 8 | LayerScape Architecture processor. The LS1046ARDB provides SW development |
| 9 | platform for the Freescale LS1046A processor series, with a complete |
| 10 | debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. |
| 11 | |
| 12 | LS1046A SoC Overview |
| 13 | -------------------- |
| 14 | Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A |
| 15 | SoC overview. |
| 16 | |
| 17 | LS1046ARDB board Overview |
| 18 | ------------------------- |
| 19 | - SERDES1 Connections, 4 lanes supporting: |
| 20 | |
| 21 | - Lane0: 10GBase-R with x1 RJ45 connector |
| 22 | - Lane1: 10GBase-R Cage |
| 23 | - Lane2: SGMII.5 |
| 24 | - Lane3: SGMII.6 |
| 25 | |
| 26 | - SERDES2 Connections, 4 lanes supporting: |
| 27 | |
| 28 | - Lane0: PCIe1 with miniPCIe slot |
| 29 | - Lane1: PCIe2 with PCIe x2 slot |
| 30 | - Lane2: PCIe3 with PCIe x4 slot |
| 31 | - Lane3: SATA |
| 32 | |
| 33 | - DDR Controller |
| 34 | |
| 35 | - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s |
| 36 | |
| 37 | - IFC/Local Bus |
| 38 | |
| 39 | - One 512 MB NAND flash with ECC support |
| 40 | - CPLD connection |
| 41 | |
| 42 | - USB 3.0 |
| 43 | |
| 44 | - one Type A port, one Micro-AB port |
| 45 | |
| 46 | - SDHC: connects directly to a full SD/MMC slot |
| 47 | - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) |
| 48 | - 4 I2C controllers |
| 49 | - UART |
| 50 | |
| 51 | - Two 4-pin serial ports at up to 115.2 Kbit/s |
| 52 | - Two DB9 D-Type connectors supporting one Serial port each |
| 53 | |
| 54 | - ARM JTAG support |
| 55 | |
| 56 | Memory map from core's view |
| 57 | ---------------------------- |
| 58 | |
| 59 | ================== ================== ================ ===== |
| 60 | Start Address End Address Description Size |
| 61 | ================== ================== ================ ===== |
| 62 | ``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M |
| 63 | ``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M |
| 64 | ``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K |
| 65 | ``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K |
| 66 | ``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M |
| 67 | ``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K |
| 68 | ``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K |
| 69 | ``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G |
| 70 | ``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M |
| 71 | ``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M |
| 72 | ``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G |
| 73 | ``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G |
| 74 | ``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G |
| 75 | ``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G |
| 76 | ================== ================== ================ ===== |
| 77 | |
| 78 | QSPI flash map |
| 79 | -------------- |
| 80 | |
| 81 | ================== ================== ================== ===== |
| 82 | Start Address End Address Description Size |
| 83 | ================== ================== ================== ===== |
| 84 | ``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M |
| 85 | ``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M |
| 86 | ``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M |
| 87 | ``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M |
| 88 | ``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M |
| 89 | + bootscript |
| 90 | ``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K |
| 91 | ``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K |
| 92 | ``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M |
| 93 | ``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M |
| 94 | ================== ================== ================== ===== |
| 95 | |
| 96 | Booting Options |
| 97 | --------------- |
| Sean Anderson | 058d780 | 2022-03-22 16:59:11 -0400 | [diff] [blame^] | 98 | |
| 99 | NB: The reference manual documents the RCW source with the *least-significant |
| 100 | bit first*. |
| 101 | |
| 102 | QSPI boot |
| 103 | ^^^^^^^^^ |
| 104 | |
| 105 | This is the default. ``{ SW5[0:8], SW4[0] }`` should be ``0010_0010_0``. |
| 106 | |
| 107 | SD boot and eMMC boot |
| 108 | ^^^^^^^^^^^^^^^^^^^^^ |
| 109 | |
| 110 | ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if |
| 111 | there is no SD card in the slot. |