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Mathew McBridee605fb12022-01-31 18:34:43 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Travese Ten64 (LS1088) board
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
7 *
8 * Author: Mathew McBride <matt@traverse.com.au>
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1088a.dtsi"
14
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/input/input.h>
17
18/ {
19 model = "Traverse Ten64";
20 compatible = "traverse,ten64", "fsl,ls1088a";
21
22 aliases {
Ioana Ciorneif86ce812023-03-15 13:04:11 +020023 serial0 = &duart0;
24 serial1 = &duart1;
Mathew McBridee605fb12022-01-31 18:34:43 +053025 spi0 = &qspi;
26 };
27
28 chosen {
29 stdout-path = "serial0:115200n8";
30 };
31
32 buttons {
33 compatible = "gpio-keys";
34
35 /* Fired by system controller when
36 * external power off (e.g ATX Power Button)
37 * asserted
38 */
39 powerdn {
40 label = "External Power Down";
41 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
42 interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
43 linux,code = <KEY_POWER>;
44 };
45
46 /* Rear Panel 'ADMIN' button (GPIO_H) */
47 admin {
48 label = "ADMIN button";
49 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
50 interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
51 linux,code = <KEY_WPS_BUTTON>;
52 };
53 };
54
55 leds {
56 compatible = "gpio-leds";
57
58 sfp1down {
59 label = "ten64:green:sfp1:down";
60 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
61 };
62
63 sfp2up {
64 label = "ten64:green:sfp2:up";
65 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
66 };
67
68 admin {
69 label = "ten64:admin";
70 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
71 };
72 };
73
74 sfp_xg0: dpmac2-sfp {
75 compatible = "sff,sfp";
76 i2c-bus = <&sfplower_i2c>;
77 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
78 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
79 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
80 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
81 maximum-power-milliwatt = <2000>;
82 };
83
84 sfp_xg1: dpmac1-sfp {
85 compatible = "sff,sfp";
86 i2c-bus = <&sfpupper_i2c>;
87 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
88 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
89 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
90 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
91 maximum-power-milliwatt = <2000>;
92 };
93};
94
95/* XG1 - Upper SFP */
96&dpmac1 {
97 sfp = <&sfp_xg1>;
98 phy-connection-type = "10gbase-r";
99 managed = "in-band-status";
100 status = "okay";
101};
102
103/* XG0 - Lower SFP */
104&dpmac2 {
105 sfp = <&sfp_xg0>;
106 phy-connection-type = "10gbase-r";
107 managed = "in-band-status";
108 status = "okay";
109};
110
111/* DPMAC3..6 is GE4 to GE8 */
112&dpmac3 {
113 phy-handle = <&mdio1_phy5>;
114 phy-connection-type = "qsgmii";
115 managed = "in-band-status";
116 status = "okay";
117};
118
119&dpmac4 {
120 phy-handle = <&mdio1_phy6>;
121 phy-connection-type = "qsgmii";
122 managed = "in-band-status";
123 status = "okay";
124};
125
126&dpmac5 {
127 phy-handle = <&mdio1_phy7>;
128 phy-connection-type = "qsgmii";
129 managed = "in-band-status";
130 status = "okay";
131};
132
133&dpmac6 {
134 phy-handle = <&mdio1_phy8>;
135 phy-connection-type = "qsgmii";
136 managed = "in-band-status";
137 status = "okay";
138};
139
140/* DPMAC7..10 is GE0 to GE3 */
141&dpmac7 {
142 phy-handle = <&mdio1_phy1>;
143 phy-connection-type = "qsgmii";
144 managed = "in-band-status";
145 status = "okay";
146};
147
148&dpmac8 {
149 phy-handle = <&mdio1_phy2>;
150 phy-connection-type = "qsgmii";
151 managed = "in-band-status";
152 status = "okay";
153};
154
155&dpmac9 {
156 phy-handle = <&mdio1_phy3>;
157 phy-connection-type = "qsgmii";
158 managed = "in-band-status";
159 status = "okay";
160};
161
162&dpmac10 {
163 phy-handle = <&mdio1_phy4>;
164 phy-connection-type = "qsgmii";
165 managed = "in-band-status";
166 status = "okay";
167};
168
Ioana Ciorneif86ce812023-03-15 13:04:11 +0200169&duart0 {
Mathew McBridee605fb12022-01-31 18:34:43 +0530170 status = "okay";
171};
172
Ioana Ciorneif86ce812023-03-15 13:04:11 +0200173&duart1 {
Mathew McBridee605fb12022-01-31 18:34:43 +0530174 status = "okay";
175};
176
177&emdio1 {
178 status = "okay";
179
180 mdio1_phy5: ethernet-phy@c {
181 reg = <0xc>;
182 };
183
184 mdio1_phy6: ethernet-phy@d {
185 reg = <0xd>;
186 };
187
188 mdio1_phy7: ethernet-phy@e {
189 reg = <0xe>;
190 };
191
192 mdio1_phy8: ethernet-phy@f {
193 reg = <0xf>;
194 };
195
196 mdio1_phy1: ethernet-phy@1c {
197 reg = <0x1c>;
198 };
199
200 mdio1_phy2: ethernet-phy@1d {
201 reg = <0x1d>;
202 };
203
204 mdio1_phy3: ethernet-phy@1e {
205 reg = <0x1e>;
206 };
207
208 mdio1_phy4: ethernet-phy@1f {
209 reg = <0x1f>;
210 };
211};
212
213&esdhc {
214 status = "okay";
215};
216
217&i2c0 {
218 status = "okay";
219
220 sfpgpio: gpio@76 {
221 compatible = "ti,tca9539";
222 reg = <0x76>;
223 #gpio-cells = <2>;
224 gpio-controller;
225
226 admin_led_lower {
227 gpio-hog;
228 gpios = <13 GPIO_ACTIVE_HIGH>;
229 output-low;
230 };
231 };
232
233 at97sc: tpm@29 {
234 compatible = "atmel,at97sc3204t";
235 reg = <0x29>;
236 };
237
238 uc: board-controller@7e {
239 compatible = "traverse,ten64-controller";
240 reg = <0x7e>;
241 };
242};
243
244&i2c2 {
245 status = "okay";
246
247 rx8035: rtc@32 {
248 compatible = "epson,rx8035";
249 reg = <0x32>;
250 };
251};
252
253&i2c3 {
254 status = "okay";
255
256 i2c-switch@70 {
257 compatible = "nxp,pca9540";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x70>;
261
262 sfpupper_i2c: i2c@0 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 reg = <0>;
266 };
267
268 sfplower_i2c: i2c@1 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <1>;
272 };
273 };
274};
275
276&qspi {
277 status = "okay";
278
279 en25s64: flash@0 {
280 compatible = "jedec,spi-nor";
281 #address-cells = <1>;
282 #size-cells = <1>;
283 reg = <0>;
284 spi-max-frequency = <20000000>;
285 spi-rx-bus-width = <4>;
286 spi-tx-bus-width = <4>;
287
288 partitions {
289 compatible = "fixed-partitions";
290 #address-cells = <1>;
291 #size-cells = <1>;
292
293 partition@0 {
294 label = "bl2";
295 reg = <0 0x100000>;
296 };
297
298 partition@100000 {
299 label = "bl3";
300 reg = <0x100000 0x200000>;
301 };
302
303 partition@300000 {
304 label = "mcfirmware";
305 reg = <0x300000 0x200000>;
306 };
307
308 partition@500000 {
309 label = "ubootenv";
310 reg = <0x500000 0x80000>;
311 };
312
313 partition@580000 {
314 label = "dpl";
315 reg = <0x580000 0x40000>;
316 };
317
318 partition@5C0000 {
319 label = "dpc";
320 reg = <0x5C0000 0x40000>;
321 };
322
323 partition@600000 {
324 label = "devicetree";
325 reg = <0x600000 0x40000>;
326 };
327 };
328 };
329
330 nand: flash@1 {
331 compatible = "spi-nand";
332 #address-cells = <1>;
333 #size-cells = <1>;
334 reg = <1>;
335 spi-max-frequency = <20000000>;
336 spi-rx-bus-width = <4>;
337 spi-tx-bus-width = <4>;
338
339 partitions {
340 compatible = "fixed-partitions";
341 #address-cells = <1>;
342 #size-cells = <1>;
343
344 /* reserved for future boot direct from NAND flash
345 * (this would use the same layout as the 8MiB NOR flash)
346 */
347 partition@0 {
348 label = "nand-boot-reserved";
349 reg = <0 0x800000>;
350 };
351
352 /* recovery / install environment */
353 partition@800000 {
354 label = "recovery";
355 reg = <0x800000 0x2000000>;
356 };
357
358 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
359 partition@2800000 {
360 label = "ubia";
361 reg = <0x2800000 0x6C00000>;
362 };
363
364 /* ubib (second OpenWrt) */
365 partition@9400000 {
366 label = "ubib";
367 reg = <0x9400000 0x6C00000>;
368 };
369 };
370 };
371};
372
373&usb0 {
374 status = "okay";
375};
376
377&usb1 {
378 status = "okay";
379};