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git01.mediatek.com / filogic / uboot / 05618996966865486cdfa92f3068cf6f7a32f6ae / . / arch / arm / dts / at91sam9rl.dtsi
blob: b855c8fe0fecc054ed1c64722bd6428e05caeb7e [file] [log] [blame]
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]1/*
2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 model = "Atmel AT91SAM9RL family SoC";
18 compatible = "atmel,at91sam9rl", "atmel,at91sam9";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 serial4 = &usart3;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 pwm0 = &pwm0;
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]37 spi0 = &spi0;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]38 };
39
40 cpus {
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
44 };
45 };
46
47 memory {
48 reg = <0x20000000 0x04000000>;
49 };
50
51 clocks {
52 slow_xtal: slow_xtal {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 main_xtal: main_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 adc_op_clk: adc_op_clk{
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <1000000>;
68 };
69 };
70
71 sram: sram@00300000 {
72 compatible = "mmio-sram";
73 reg = <0x00300000 0x10000>;
74 };
75
76 ahb {
77 compatible = "simple-bus";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]82
83 fb0: fb@00500000 {
84 compatible = "atmel,at91sam9rl-lcdc";
85 reg = <0x00500000 0x1000>;
86 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_fb>;
89 clocks = <&lcd_clk>, <&lcd_clk>;
90 clock-names = "hclk", "lcdc_clk";
91 status = "disabled";
92 };
93
94 nand0: nand@40000000 {
95 compatible = "atmel,at91rm9200-nand";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x40000000 0x10000000>,
99 <0xffffe800 0x200>;
100 atmel,nand-addr-offset = <21>;
101 atmel,nand-cmd-offset = <22>;
102 atmel,nand-has-dma;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_nand>;
105 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
106 <&pioB 6 GPIO_ACTIVE_HIGH>,
107 <0>;
108 status = "disabled";
109 };
110
111 apb {
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]117
118 tcb0: timer@fffa0000 {
119 compatible = "atmel,at91rm9200-tcb";
120 reg = <0xfffa0000 0x100>;
121 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
122 <17 IRQ_TYPE_LEVEL_HIGH 0>,
123 <18 IRQ_TYPE_LEVEL_HIGH 0>;
124 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
125 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
126 };
127
128 mmc0: mmc@fffa4000 {
129 compatible = "atmel,hsmci";
130 reg = <0xfffa4000 0x600>;
131 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 pinctrl-names = "default";
135 clocks = <&mci0_clk>;
136 clock-names = "mci_clk";
137 status = "disabled";
138 };
139
140 i2c0: i2c@fffa8000 {
141 compatible = "atmel,at91sam9260-i2c";
142 reg = <0xfffa8000 0x100>;
143 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
144 #address-cells = <1>;
145 #size-cells = <0>;
146 clocks = <&twi0_clk>;
147 status = "disabled";
148 };
149
150 i2c1: i2c@fffac000 {
151 compatible = "atmel,at91sam9260-i2c";
152 reg = <0xfffac000 0x100>;
153 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 status = "disabled";
157 };
158
159 usart0: serial@fffb0000 {
160 compatible = "atmel,at91sam9260-usart";
161 reg = <0xfffb0000 0x200>;
162 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
163 atmel,use-dma-rx;
164 atmel,use-dma-tx;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usart0>;
167 clocks = <&usart0_clk>;
168 clock-names = "usart";
169 status = "disabled";
170 };
171
172 usart1: serial@fffb4000 {
173 compatible = "atmel,at91sam9260-usart";
174 reg = <0xfffb4000 0x200>;
175 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
176 atmel,use-dma-rx;
177 atmel,use-dma-tx;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_usart1>;
180 clocks = <&usart1_clk>;
181 clock-names = "usart";
182 status = "disabled";
183 };
184
185 usart2: serial@fffb8000 {
186 compatible = "atmel,at91sam9260-usart";
187 reg = <0xfffb8000 0x200>;
188 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
189 atmel,use-dma-rx;
190 atmel,use-dma-tx;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usart2>;
193 clocks = <&usart2_clk>;
194 clock-names = "usart";
195 status = "disabled";
196 };
197
198 usart3: serial@fffbc000 {
199 compatible = "atmel,at91sam9260-usart";
200 reg = <0xfffbc000 0x200>;
201 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
202 atmel,use-dma-rx;
203 atmel,use-dma-tx;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_usart3>;
206 clocks = <&usart3_clk>;
207 clock-names = "usart";
208 status = "disabled";
209 };
210
211 ssc0: ssc@fffc0000 {
212 compatible = "atmel,at91sam9rl-ssc";
213 reg = <0xfffc0000 0x4000>;
214 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
217 status = "disabled";
218 };
219
220 ssc1: ssc@fffc4000 {
221 compatible = "atmel,at91sam9rl-ssc";
222 reg = <0xfffc4000 0x4000>;
223 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
226 status = "disabled";
227 };
228
229 pwm0: pwm@fffc8000 {
230 compatible = "atmel,at91sam9rl-pwm";
231 reg = <0xfffc8000 0x300>;
232 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
233 #pwm-cells = <3>;
234 clocks = <&pwm_clk>;
235 clock-names = "pwm_clk";
236 status = "disabled";
237 };
238
239 spi0: spi@fffcc000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "atmel,at91rm9200-spi";
243 reg = <0xfffcc000 0x200>;
244 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_spi0>;
247 clocks = <&spi0_clk>;
248 clock-names = "spi_clk";
249 status = "disabled";
250 };
251
252 adc0: adc@fffd0000 {
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]253 compatible = "atmel,at91sam9rl-adc";
254 reg = <0xfffd0000 0x100>;
255 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
256 clocks = <&adc_clk>, <&adc_op_clk>;
257 clock-names = "adc_clk", "adc_op_clk";
258 atmel,adc-use-external-triggers;
259 atmel,adc-channels-used = <0x3f>;
260 atmel,adc-vref = <3300>;
261 atmel,adc-startup-time = <40>;
262 atmel,adc-res = <8 10>;
263 atmel,adc-res-names = "lowres", "highres";
264 atmel,adc-use-res = "highres";
265
266 trigger0 {
267 trigger-name = "timer-counter-0";
268 trigger-value = <0x1>;
269 };
270 trigger1 {
271 trigger-name = "timer-counter-1";
272 trigger-value = <0x3>;
273 };
274
275 trigger2 {
276 trigger-name = "timer-counter-2";
277 trigger-value = <0x5>;
278 };
279
280 trigger3 {
281 trigger-name = "external";
282 trigger-value = <0x13>;
283 trigger-external;
284 };
285 };
286
287 usb0: gadget@fffd4000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "atmel,at91sam9rl-udc";
291 reg = <0x00600000 0x100000>,
292 <0xfffd4000 0x4000>;
293 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
294 clocks = <&udphs_clk>, <&utmi>;
295 clock-names = "pclk", "hclk";
296 status = "disabled";
297
298 ep@0 {
299 reg = <0>;
300 atmel,fifo-size = <64>;
301 atmel,nb-banks = <1>;
302 };
303
304 ep@1 {
305 reg = <1>;
306 atmel,fifo-size = <1024>;
307 atmel,nb-banks = <2>;
308 atmel,can-dma;
309 atmel,can-isoc;
310 };
311
312 ep@2 {
313 reg = <2>;
314 atmel,fifo-size = <1024>;
315 atmel,nb-banks = <2>;
316 atmel,can-dma;
317 atmel,can-isoc;
318 };
319
320 ep@3 {
321 reg = <3>;
322 atmel,fifo-size = <1024>;
323 atmel,nb-banks = <3>;
324 atmel,can-dma;
325 };
326
327 ep@4 {
328 reg = <4>;
329 atmel,fifo-size = <1024>;
330 atmel,nb-banks = <3>;
331 atmel,can-dma;
332 };
333
334 ep@5 {
335 reg = <5>;
336 atmel,fifo-size = <1024>;
337 atmel,nb-banks = <3>;
338 atmel,can-dma;
339 atmel,can-isoc;
340 };
341
342 ep@6 {
343 reg = <6>;
344 atmel,fifo-size = <1024>;
345 atmel,nb-banks = <3>;
346 atmel,can-dma;
347 atmel,can-isoc;
348 };
349 };
350
351 dma0: dma-controller@ffffe600 {
352 compatible = "atmel,at91sam9rl-dma";
353 reg = <0xffffe600 0x200>;
354 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
355 #dma-cells = <2>;
356 clocks = <&dma0_clk>;
357 clock-names = "dma_clk";
358 };
359
360 ramc0: ramc@ffffea00 {
361 compatible = "atmel,at91sam9260-sdramc";
362 reg = <0xffffea00 0x200>;
363 };
364
365 aic: interrupt-controller@fffff000 {
366 #interrupt-cells = <3>;
367 compatible = "atmel,at91rm9200-aic";
368 interrupt-controller;
369 reg = <0xfffff000 0x200>;
370 atmel,external-irqs = <31>;
371 };
372
373 dbgu: serial@fffff200 {
374 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
375 reg = <0xfffff200 0x200>;
376 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_dbgu>;
379 clocks = <&mck>;
380 clock-names = "usart";
381 status = "disabled";
382 };
383
384 pinctrl@fffff400 {
385 #address-cells = <1>;
386 #size-cells = <1>;
387 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
388 ranges = <0xfffff400 0xfffff400 0x800>;
389 reg = <0xfffff400 0x200
390 0xfffff600 0x200
391 0xfffff800 0x200
392 0xfffffa00 0x200
393 >;
394
395 atmel,mux-mask =
396 /* A B */
397 <0xffffffff 0xe05c6738>, /* pioA */
398 <0xffffffff 0x0000c780>, /* pioB */
399 <0xffffffff 0xe3ffff0e>, /* pioC */
400 <0x003fffff 0x0001ff3c>; /* pioD */
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]401 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]402
403 /* shared pinctrl settings */
404 adc0 {
405 pinctrl_adc0_ts: adc0_ts-0 {
406 atmel,pins =
407 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
408 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
409 <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
410 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
411 };
412
413 pinctrl_adc0_ad0: adc0_ad0-0 {
414 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
415 };
416
417 pinctrl_adc0_ad1: adc0_ad1-0 {
418 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
419 };
420
421 pinctrl_adc0_ad2: adc0_ad2-0 {
422 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
423 };
424
425 pinctrl_adc0_ad3: adc0_ad3-0 {
426 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
427 };
428
429 pinctrl_adc0_ad4: adc0_ad4-0 {
430 atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
431 };
432
433 pinctrl_adc0_ad5: adc0_ad5-0 {
434 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
435 };
436
437 pinctrl_adc0_adtrg: adc0_adtrg-0 {
438 atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
439 };
440 };
441
442 dbgu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]443 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]444 pinctrl_dbgu: dbgu-0 {
445 atmel,pins =
446 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
447 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
448 };
449 };
450
451 fb {
452 pinctrl_fb: fb-0 {
453 atmel,pins =
454 <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
455 <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
456 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
457 <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
458 <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
459 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
460 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
461 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
462 <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
463 <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
464 <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
465 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
466 <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
467 <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
468 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
469 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
470 <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
471 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
472 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
473 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
474 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
475 };
476 };
477
478 i2c_gpio0 {
479 pinctrl_i2c_gpio0: i2c_gpio0-0 {
480 atmel,pins =
481 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
482 <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
483 };
484 };
485
486 i2c_gpio1 {
487 pinctrl_i2c_gpio1: i2c_gpio1-0 {
488 atmel,pins =
489 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
490 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
491 };
492 };
493
494 mmc0 {
495 pinctrl_mmc0_clk: mmc0_clk-0 {
496 atmel,pins =
497 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
498 };
499
500 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
501 atmel,pins =
502 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
503 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
504 };
505
506 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
507 atmel,pins =
508 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
509 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
510 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
511 };
512 };
513
514 nand {
515 pinctrl_nand: nand-0 {
516 atmel,pins =
517 <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
518 <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
519 };
520
521 pinctrl_nand0_ale_cle: nand_ale_cle-0 {
522 atmel,pins =
523 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
524 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
525 };
526
527 pinctrl_nand0_oe_we: nand_oe_we-0 {
528 atmel,pins =
529 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
530 <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
531 };
532
533 pinctrl_nand0_cs: nand_cs-0 {
534 atmel,pins =
535 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
536 };
537 };
538
539 pwm0 {
540 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
541 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
542 };
543
544 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
545 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
546 };
547
548 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
549 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
550 };
551
552 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
553 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
554 };
555
556 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
557 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
558 };
559
560 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
561 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
562 };
563
564 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
565 atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
566 };
567
568 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
569 atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
570 };
571
572 pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
573 atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
574 };
575
576 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
577 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
578 };
579
580 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
581 atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
582 };
583 };
584
585 spi0 {
586 pinctrl_spi0: spi0-0 {
587 atmel,pins =
588 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
589 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
590 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
591 };
592 };
593
594 ssc0 {
595 pinctrl_ssc0_tx: ssc0_tx-0 {
596 atmel,pins =
597 <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
598 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
599 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
600 };
601
602 pinctrl_ssc0_rx: ssc0_rx-0 {
603 atmel,pins =
604 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
605 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
606 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
607 };
608 };
609
610 ssc1 {
611 pinctrl_ssc1_tx: ssc1_tx-0 {
612 atmel,pins =
613 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
614 <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
615 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
616 };
617
618 pinctrl_ssc1_rx: ssc1_rx-0 {
619 atmel,pins =
620 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
621 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
622 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
623 };
624 };
625
626 tcb0 {
627 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
628 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
629 };
630
631 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
632 atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
633 };
634
635 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
636 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
637 };
638
639 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
640 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
641 };
642
643 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
644 atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
645 };
646
647 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
648 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
649 };
650
651 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
652 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
653 };
654
655 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
656 atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
657 };
658
659 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
660 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
661 };
662 };
663
664 usart0 {
665 pinctrl_usart0: usart0-0 {
666 atmel,pins =
667 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
668 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
669 };
670
671 pinctrl_usart0_rts: usart0_rts-0 {
672 atmel,pins =
673 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
674 };
675
676 pinctrl_usart0_cts: usart0_cts-0 {
677 atmel,pins =
678 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
679 };
680
681 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
682 atmel,pins =
683 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
684 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
685 };
686
687 pinctrl_usart0_dcd: usart0_dcd-0 {
688 atmel,pins =
689 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
690 };
691
692 pinctrl_usart0_ri: usart0_ri-0 {
693 atmel,pins =
694 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
695 };
696
697 pinctrl_usart0_sck: usart0_sck-0 {
698 atmel,pins =
699 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
700 };
701 };
702
703 usart1 {
704 pinctrl_usart1: usart1-0 {
705 atmel,pins =
706 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
707 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
708 };
709
710 pinctrl_usart1_rts: usart1_rts-0 {
711 atmel,pins =
712 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
713 };
714
715 pinctrl_usart1_cts: usart1_cts-0 {
716 atmel,pins =
717 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
718 };
719
720 pinctrl_usart1_sck: usart1_sck-0 {
721 atmel,pins =
722 <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
723 };
724 };
725
726 usart2 {
727 pinctrl_usart2: usart2-0 {
728 atmel,pins =
729 <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
730 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
731 };
732
733 pinctrl_usart2_rts: usart2_rts-0 {
734 atmel,pins =
735 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
736 };
737
738 pinctrl_usart2_cts: usart2_cts-0 {
739 atmel,pins =
740 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
741 };
742
743 pinctrl_usart2_sck: usart2_sck-0 {
744 atmel,pins =
745 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
746 };
747 };
748
749 usart3 {
750 pinctrl_usart3: usart3-0 {
751 atmel,pins =
752 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
753 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
754 };
755
756 pinctrl_usart3_rts: usart3_rts-0 {
757 atmel,pins =
758 <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
759 };
760
761 pinctrl_usart3_cts: usart3_cts-0 {
762 atmel,pins =
763 <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
764 };
765
766 pinctrl_usart3_sck: usart3_sck-0 {
767 atmel,pins =
768 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
769 };
770 };
771 };
772
773 pioA: gpio@fffff400 {
774 compatible = "atmel,at91rm9200-gpio";
775 reg = <0xfffff400 0x200>;
776 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
777 #gpio-cells = <2>;
778 gpio-controller;
779 interrupt-controller;
780 #interrupt-cells = <2>;
781 clocks = <&pioA_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]782 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]783 };
784
785 pioB: gpio@fffff600 {
786 compatible = "atmel,at91rm9200-gpio";
787 reg = <0xfffff600 0x200>;
788 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
789 #gpio-cells = <2>;
790 gpio-controller;
791 interrupt-controller;
792 #interrupt-cells = <2>;
793 clocks = <&pioB_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]794 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]795 };
796
797 pioC: gpio@fffff800 {
798 compatible = "atmel,at91rm9200-gpio";
799 reg = <0xfffff800 0x200>;
800 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
801 #gpio-cells = <2>;
802 gpio-controller;
803 interrupt-controller;
804 #interrupt-cells = <2>;
805 clocks = <&pioC_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]806 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]807 };
808
809 pioD: gpio@fffffa00 {
810 compatible = "atmel,at91rm9200-gpio";
811 reg = <0xfffffa00 0x200>;
812 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
813 #gpio-cells = <2>;
814 gpio-controller;
815 interrupt-controller;
816 #interrupt-cells = <2>;
817 clocks = <&pioD_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]818 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]819 };
820
821 pmc: pmc@fffffc00 {
822 compatible = "atmel,at91sam9g45-pmc", "syscon";
823 reg = <0xfffffc00 0x100>;
824 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
825 interrupt-controller;
826 #address-cells = <1>;
827 #size-cells = <0>;
828 #interrupt-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]829 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]830
831 main: mainck {
832 compatible = "atmel,at91rm9200-clk-main";
833 #clock-cells = <0>;
834 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
835 clocks = <&main_xtal>;
836 };
837
838 plla: pllack@0 {
839 compatible = "atmel,at91rm9200-clk-pll";
840 #clock-cells = <0>;
841 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
842 clocks = <&main>;
843 reg = <0>;
844 atmel,clk-input-range = <1000000 32000000>;
845 #atmel,pll-clk-output-range-cells = <3>;
846 atmel,pll-clk-output-ranges = <80000000 200000000 0>,
847 <190000000 240000000 2>;
848 };
849
850 utmi: utmick {
851 compatible = "atmel,at91sam9x5-clk-utmi";
852 #clock-cells = <0>;
853 interrupt-parent = <&pmc>;
854 interrupts = <AT91_PMC_LOCKU>;
855 clocks = <&main>;
856 };
857
858 mck: masterck {
859 compatible = "atmel,at91rm9200-clk-master";
860 #clock-cells = <0>;
861 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
862 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
863 atmel,clk-output-range = <0 94000000>;
864 atmel,clk-divisors = <1 2 4 0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]865 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]866 };
867
868 prog: progck {
869 compatible = "atmel,at91rm9200-clk-programmable";
870 #address-cells = <1>;
871 #size-cells = <0>;
872 interrupt-parent = <&pmc>;
873 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
874
875 prog0: prog@0 {
876 #clock-cells = <0>;
877 reg = <0>;
878 interrupts = <AT91_PMC_PCKRDY(0)>;
879 };
880
881 prog1: prog@1 {
882 #clock-cells = <0>;
883 reg = <1>;
884 interrupts = <AT91_PMC_PCKRDY(1)>;
885 };
886 };
887
888 systemck {
889 compatible = "atmel,at91rm9200-clk-system";
890 #address-cells = <1>;
891 #size-cells = <0>;
892
893 pck0: pck0@8 {
894 #clock-cells = <0>;
895 reg = <8>;
896 clocks = <&prog0>;
897 };
898
899 pck1: pck1@9 {
900 #clock-cells = <0>;
901 reg = <9>;
902 clocks = <&prog1>;
903 };
904
905 };
906
907 periphck {
908 compatible = "atmel,at91rm9200-clk-peripheral";
909 #address-cells = <1>;
910 #size-cells = <0>;
911 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]912 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]913
914 pioA_clk: pioA_clk@2 {
915 #clock-cells = <0>;
916 reg = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]917 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]918 };
919
920 pioB_clk: pioB_clk@3 {
921 #clock-cells = <0>;
922 reg = <3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]923 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]924 };
925
926 pioC_clk: pioC_clk@4 {
927 #clock-cells = <0>;
928 reg = <4>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]929 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]930 };
931
932 pioD_clk: pioD_clk@5 {
933 #clock-cells = <0>;
934 reg = <5>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]935 bootph-all;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]936 };
937
938 usart0_clk: usart0_clk@6 {
939 #clock-cells = <0>;
940 reg = <6>;
941 };
942
943 usart1_clk: usart1_clk@7 {
944 #clock-cells = <0>;
945 reg = <7>;
946 };
947
948 usart2_clk: usart2_clk@8 {
949 #clock-cells = <0>;
950 reg = <8>;
951 };
952
953 usart3_clk: usart3_clk@9 {
954 #clock-cells = <0>;
955 reg = <9>;
956 };
957
958 mci0_clk: mci0_clk@10 {
959 #clock-cells = <0>;
960 reg = <10>;
961 };
962
963 twi0_clk: twi0_clk@11 {
964 #clock-cells = <0>;
965 reg = <11>;
966 };
967
968 twi1_clk: twi1_clk@12 {
969 #clock-cells = <0>;
970 reg = <12>;
971 };
972
973 spi0_clk: spi0_clk@13 {
974 #clock-cells = <0>;
975 reg = <13>;
976 };
977
978 ssc0_clk: ssc0_clk@14 {
979 #clock-cells = <0>;
980 reg = <14>;
981 };
982
983 ssc1_clk: ssc1_clk@15 {
984 #clock-cells = <0>;
985 reg = <15>;
986 };
987
988 tc0_clk: tc0_clk@16 {
989 #clock-cells = <0>;
990 reg = <16>;
991 };
992
993 tc1_clk: tc1_clk@17 {
994 #clock-cells = <0>;
995 reg = <17>;
996 };
997
998 tc2_clk: tc2_clk@18 {
999 #clock-cells = <0>;
1000 reg = <18>;
1001 };
1002
1003 pwm_clk: pwm_clk@19 {
1004 #clock-cells = <0>;
1005 reg = <19>;
1006 };
1007
1008 adc_clk: adc_clk@20 {
1009 #clock-cells = <0>;
1010 reg = <20>;
1011 };
1012
1013 dma0_clk: dma0_clk@21 {
1014 #clock-cells = <0>;
1015 reg = <21>;
1016 };
1017
1018 udphs_clk: udphs_clk@22 {
1019 #clock-cells = <0>;
1020 reg = <22>;
1021 };
1022
1023 lcd_clk: lcd_clk@23 {
1024 #clock-cells = <0>;
1025 reg = <23>;
1026 };
1027 };
1028 };
1029
1030 rstc@fffffd00 {
1031 compatible = "atmel,at91sam9260-rstc";
1032 reg = <0xfffffd00 0x10>;
1033 clocks = <&clk32k>;
1034 };
1035
1036 shdwc@fffffd10 {
1037 compatible = "atmel,at91sam9260-shdwc";
1038 reg = <0xfffffd10 0x10>;
1039 clocks = <&clk32k>;
1040 };
1041
1042 pit: timer@fffffd30 {
1043 compatible = "atmel,at91sam9260-pit";
1044 reg = <0xfffffd30 0xf>;
1045 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1046 clocks = <&mck>;
1047 };
1048
1049 watchdog@fffffd40 {
1050 compatible = "atmel,at91sam9260-wdt";
1051 reg = <0xfffffd40 0x10>;
1052 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1053 clocks = <&clk32k>;
1054 status = "disabled";
1055 };
1056
1057 sckc@fffffd50 {
1058 compatible = "atmel,at91sam9x5-sckc";
1059 reg = <0xfffffd50 0x4>;
1060
1061 slow_osc: slow_osc {
1062 compatible = "atmel,at91sam9x5-clk-slow-osc";
1063 #clock-cells = <0>;
1064 atmel,startup-time-usec = <1200000>;
1065 clocks = <&slow_xtal>;
1066 };
1067
1068 slow_rc_osc: slow_rc_osc {
1069 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1070 #clock-cells = <0>;
1071 atmel,startup-time-usec = <75>;
1072 clock-frequency = <32768>;
1073 clock-accuracy = <50000000>;
1074 };
1075
1076 clk32k: slck {
1077 compatible = "atmel,at91sam9x5-clk-slow";
1078 #clock-cells = <0>;
1079 clocks = <&slow_rc_osc &slow_osc>;
1080 };
1081 };
1082
1083 rtc@fffffd20 {
1084 compatible = "atmel,at91sam9260-rtt";
1085 reg = <0xfffffd20 0x10>;
1086 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1087 clocks = <&clk32k>;
1088 status = "disabled";
1089 };
1090
1091 gpbr: syscon@fffffd60 {
1092 compatible = "atmel,at91sam9260-gpbr", "syscon";
1093 reg = <0xfffffd60 0x10>;
1094 status = "disabled";
1095 };
1096
1097 rtc@fffffe00 {
1098 compatible = "atmel,at91rm9200-rtc";
1099 reg = <0xfffffe00 0x40>;
1100 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1101 clocks = <&clk32k>;
1102 status = "disabled";
1103 };
1104
1105 };
1106 };
1107
1108 i2c-gpio-0 {
1109 compatible = "i2c-gpio";
1110 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
1111 <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
1112 i2c-gpio,sda-open-drain;
1113 i2c-gpio,scl-open-drain;
1114 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1119 status = "disabled";
1120 };
1121
1122 i2c-gpio-1 {
1123 compatible = "i2c-gpio";
1124 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
1125 <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
1126 i2c-gpio,sda-open-drain;
1127 i2c-gpio,scl-open-drain;
1128 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&pinctrl_i2c_gpio1>;
1133 status = "disabled";
1134 };
1135};