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git01.mediatek.com / filogic / uboot / 0557263874d42466221306d0ff76fe1699e7efbd / . / include / configs / UCP1020.h
blob: 5e80c136f0d399f28b2284fda454c0b28b220668 [file] [log] [blame]
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]1/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]17#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
18#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
19#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
20#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
21#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
22#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
23
24#if defined(CONFIG_TARTGET_UCP1020T1)
25
26#define CONFIG_UCP1020_REV_1_3
27
28#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]29
30#define CONFIG_TSEC_ENET
31#define CONFIG_TSEC1
32#define CONFIG_TSEC3
33#define CONFIG_HAS_ETH0
34#define CONFIG_HAS_ETH1
35#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
36#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
37#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
38#define CONFIG_IPADDR 10.80.41.229
39#define CONFIG_SERVERIP 10.80.41.227
40#define CONFIG_NETMASK 255.255.252.0
41#define CONFIG_ETHPRIME "eTSEC3"
42
43#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]44#endif
45#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
46
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]47#define CONFIG_SYS_L2_SIZE (256 << 10)
48
49#define CONFIG_LAST_STAGE_INIT
50
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]51#endif
52
53#if defined(CONFIG_TARGET_UCP1020)
54
55#define CONFIG_UCP1020
56#define CONFIG_UCP1020_REV_1_3
57
58#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]59
60#define CONFIG_TSEC_ENET
61#define CONFIG_TSEC1
62#define CONFIG_TSEC2
63#define CONFIG_TSEC3
64#define CONFIG_HAS_ETH0
65#define CONFIG_HAS_ETH1
66#define CONFIG_HAS_ETH2
67#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
68#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
69#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
70#define CONFIG_IPADDR 192.168.1.81
71#define CONFIG_IPADDR1 192.168.1.82
72#define CONFIG_IPADDR2 192.168.1.83
73#define CONFIG_SERVERIP 192.168.1.80
74#define CONFIG_GATEWAYIP 102.168.1.1
75#define CONFIG_NETMASK 255.255.255.0
76#define CONFIG_ETHPRIME "eTSEC1"
77
78#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]79#endif
80#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
81
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]82#define CONFIG_SYS_L2_SIZE (256 << 10)
83
84#define CONFIG_LAST_STAGE_INIT
85
86#endif
87
88#ifdef CONFIG_SDCARD
89#define CONFIG_RAMBOOT_SDCARD
90#define CONFIG_SYS_RAMBOOT
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_SYS_TEXT_BASE 0x11000000
93#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
94#endif
95
96#ifdef CONFIG_SPIFLASH
97#define CONFIG_RAMBOOT_SPIFLASH
98#define CONFIG_SYS_RAMBOOT
99#define CONFIG_SYS_EXTRA_ENV_RELOC
100#define CONFIG_SYS_TEXT_BASE 0x11000000
101#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
102#endif
103
104#ifndef CONFIG_SYS_TEXT_BASE
105#define CONFIG_SYS_TEXT_BASE 0xeff80000
106#endif
107#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
108
109#ifndef CONFIG_RESET_VECTOR_ADDRESS
110#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
111#endif
112
113#ifndef CONFIG_SYS_MONITOR_BASE
114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
115#endif
116
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]117#define CONFIG_MP
118
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]119#define CONFIG_ENV_OVERWRITE
120
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]121#define CONFIG_SATA_SIL
122#define CONFIG_SYS_SATA_MAX_DEVICE 2
123#define CONFIG_LIBATA
124#define CONFIG_LBA48
125
126#define CONFIG_SYS_CLK_FREQ 66666666
127#define CONFIG_DDR_CLK_FREQ 66666666
128
129#define CONFIG_HWCONFIG
130
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]131/*
132 * These can be toggled for performance analysis, otherwise use default.
133 */
134#define CONFIG_L2_CACHE
135#define CONFIG_BTB
136
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]137#define CONFIG_ENABLE_36BIT_PHYS
138
139#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x1fffffff
141#define CONFIG_PANIC_HANG /* do not reset board on panic */
142
143#define CONFIG_SYS_CCSRBAR 0xffe00000
144#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
145
146/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
147 SPL code*/
148#ifdef CONFIG_SPL_BUILD
149#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
150#endif
151
152/* DDR Setup */
153#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]154#ifndef CONFIG_DDR_ECC_ENABLE
155#define CONFIG_SYS_DDR_RAW_TIMING
156#define CONFIG_DDR_SPD
157#endif
158#define CONFIG_SYS_SPD_BUS_NUM 1
159#undef CONFIG_FSL_DDR_INTERACTIVE
160
161#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
162#define CONFIG_CHIP_SELECTS_PER_CTRL 1
163#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
164#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
165#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]167#define CONFIG_DIMM_SLOTS_PER_CTLR 1
168
169/* Default settings for DDR3 */
170#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
171#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
172#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
173#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
174#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
175#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
176
177#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
178#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
179#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
180#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
181
182#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
183#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
184#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
185#define CONFIG_SYS_DDR_RCW_1 0x00000000
186#define CONFIG_SYS_DDR_RCW_2 0x00000000
187#ifdef CONFIG_DDR_ECC_ENABLE
188#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
189#else
190#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
191#endif
192#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
193#define CONFIG_SYS_DDR_TIMING_4 0x00220001
194#define CONFIG_SYS_DDR_TIMING_5 0x03402400
195
196#define CONFIG_SYS_DDR_TIMING_3 0x00020000
197#define CONFIG_SYS_DDR_TIMING_0 0x00330004
198#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
199#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
200#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
201#define CONFIG_SYS_DDR_MODE_1 0x40461520
202#define CONFIG_SYS_DDR_MODE_2 0x8000c000
203#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
204
205#undef CONFIG_CLOCKS_IN_MHZ
206
207/*
208 * Memory map
209 *
210 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
211 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
212 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
213 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
214 * (early boot only)
215 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
216 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
217 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
218 */
219
220/*
221 * Local Bus Definitions
222 */
223#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
224#define CONFIG_SYS_FLASH_BASE 0xec000000
225
226#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
227
228#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
229 | BR_PS_16 | BR_V)
230
231#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
232
233#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
234#define CONFIG_SYS_FLASH_QUIET_TEST
235#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
236
237#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
238
239#undef CONFIG_SYS_FLASH_CHECKSUM
240#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
241#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
242
243#define CONFIG_FLASH_CFI_DRIVER
244#define CONFIG_SYS_FLASH_CFI
245#define CONFIG_SYS_FLASH_EMPTY_INFO
246#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
247
248#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
249
250#define CONFIG_SYS_INIT_RAM_LOCK
251#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
252/* Initial L1 address */
253#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
254#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
255#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
256/* Size of used area in RAM */
257#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
258
259#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
260 GENERATED_GBL_DATA_SIZE)
261#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
262
263#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
264#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
265
266#define CONFIG_SYS_PMC_BASE 0xff980000
267#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
268#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
269 BR_PS_8 | BR_V)
270#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
271 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
272 OR_GPCM_EAD)
273
274#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
275#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
276#ifdef CONFIG_NAND_FSL_ELBC
277#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
278#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
279#endif
280
281/* Serial Port - controlled on board with jumper J8
282 * open - index 2
283 * shorted - index 1
284 */
285#define CONFIG_CONS_INDEX 1
286#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]287#define CONFIG_SYS_NS16550_SERIAL
288#define CONFIG_SYS_NS16550_REG_SIZE 1
289#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
290#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
291#define CONFIG_NS16550_MIN_FUNCTIONS
292#endif
293
294#define CONFIG_SYS_BAUDRATE_TABLE \
295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
296
297#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
298#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
299
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]300/* I2C */
301#define CONFIG_SYS_I2C
302#define CONFIG_SYS_I2C_FSL
303#define CONFIG_SYS_FSL_I2C_SPEED 400000
304#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
305#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
306#define CONFIG_SYS_FSL_I2C2_SPEED 400000
307#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
308#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
309#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
310#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
311
312#define CONFIG_RTC_DS1337
Chris Packham2d3ac512017-05-30 12:03:33 +1200[diff] [blame]313#define CONFIG_RTC_DS1337_NOOSC
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]314#define CONFIG_SYS_I2C_RTC_ADDR 0x68
315#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
316#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
317#define CONFIG_SYS_I2C_IDT6V49205B 0x69
318
319/*
320 * eSPI - Enhanced SPI
321 */
322#define CONFIG_HARD_SPI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]323
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]324#define CONFIG_SF_DEFAULT_SPEED 10000000
325#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
326
327#if defined(CONFIG_PCI)
328/*
329 * General PCI
330 * Memory space is mapped 1-1, but I/O space must start from 0.
331 */
332
333/* controller 2, direct to uli, tgtid 2, Base address 9000 */
334#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
335#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
336#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
337#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
338#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
339#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
340#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
341#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
342#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
343
344/* controller 1, Slot 2, tgtid 1, Base address a000 */
345#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
346#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
347#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
348#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
349#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
350#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
351#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
352#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
353#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
354
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]355#define CONFIG_CMD_PCI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]356
357#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]358#endif /* CONFIG_PCI */
359
360/*
361 * Environment
362 */
363#ifdef CONFIG_ENV_FIT_UCBOOT
364
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]365#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
366#define CONFIG_ENV_SIZE 0x20000
367#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
368
369#else
370
371#define CONFIG_ENV_SPI_BUS 0
372#define CONFIG_ENV_SPI_CS 0
373#define CONFIG_ENV_SPI_MAX_HZ 10000000
374#define CONFIG_ENV_SPI_MODE 0
375
376#ifdef CONFIG_RAMBOOT_SPIFLASH
377
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]378#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
379#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
380#define CONFIG_ENV_SECT_SIZE 0x1000
381
382#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
383/* Address and size of Redundant Environment Sector */
384#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
385#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
386#endif
387
388#elif defined(CONFIG_RAMBOOT_SDCARD)
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]389#define CONFIG_FSL_FIXED_MMC_LOCATION
390#define CONFIG_ENV_SIZE 0x2000
391#define CONFIG_SYS_MMC_ENV_DEV 0
392
393#elif defined(CONFIG_SYS_RAMBOOT)
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]394#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
395#define CONFIG_ENV_SIZE 0x2000
396
397#else
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]398#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
399#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
400#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
401#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
402#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
403/* Address and size of Redundant Environment Sector */
404#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
405#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
406#endif
407
408#endif
409
410#endif /* CONFIG_ENV_FIT_UCBOOT */
411
412#define CONFIG_LOADS_ECHO /* echo on for serial download */
413#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
414
415/*
416 * Command line configuration.
417 */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]418#define CONFIG_CMD_REGINFO
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]419
420/*
421 * USB
422 */
423#define CONFIG_HAS_FSL_DR_USB
424
425#if defined(CONFIG_HAS_FSL_DR_USB)
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]426#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
427
Tom Riniceed5d22017-05-12 22:33:27 -0400[diff] [blame]428#ifdef CONFIG_USB_EHCI_HCD
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]429#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
430#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]431#endif
432#endif
433
434#undef CONFIG_WATCHDOG /* watchdog disabled */
435
436#ifdef CONFIG_MMC
437#define CONFIG_FSL_ESDHC
438#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]439#define CONFIG_MMC_SPI
440#define CONFIG_CMD_MMC_SPI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]441#endif
442
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]443/* Misc Extra Settings */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]444#undef CONFIG_WATCHDOG /* watchdog disabled */
445
446/*
447 * Miscellaneous configurable options
448 */
449#define CONFIG_SYS_LONGHELP /* undef to save memory */
450#define CONFIG_CMDLINE_EDITING /* Command-line editing */
451#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]452#if defined(CONFIG_CMD_KGDB)
453#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
454#else
455#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
456#endif
457#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
458 /* Print Buffer Size */
459#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
460#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
461#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
462
463/*
464 * For booting Linux, the board info and command line data
465 * have to be in the first 64 MB of memory, since this is
466 * the maximum mapped by the Linux kernel during initialization.
467 */
468#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
469#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
470
471#if defined(CONFIG_CMD_KGDB)
472#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
473#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
474#endif
475
476/*
477 * Environment Configuration
478 */
479
480#if defined(CONFIG_TSEC_ENET)
481
Alexandru Gagniuc05572632017-07-07 11:36:58 -0700[diff] [blame^]482#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
483#define CONFIG_PHY_MICREL_KSZ90X1
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]484#else
485#error "UCP1020 module revision is not defined !!!"
486#endif
487
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]488#define CONFIG_BOOTP_SERVERIP
489
490#define CONFIG_MII /* MII PHY management */
491#define CONFIG_TSEC1_NAME "eTSEC1"
492#define CONFIG_TSEC2_NAME "eTSEC2"
493#define CONFIG_TSEC3_NAME "eTSEC3"
494
495#define TSEC1_PHY_ADDR 4
496#define TSEC2_PHY_ADDR 0
497#define TSEC2_PHY_ADDR_SGMII 0x00
498#define TSEC3_PHY_ADDR 6
499
500#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
501#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
502#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
503
504#define TSEC1_PHYIDX 0
505#define TSEC2_PHYIDX 0
506#define TSEC3_PHYIDX 0
507
508#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
509
510#endif
511
512#define CONFIG_HOSTNAME UCP1020
513#define CONFIG_ROOTPATH "/opt/nfsroot"
514#define CONFIG_BOOTFILE "uImage"
515#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
516
517/* default location for tftp and bootm */
518#define CONFIG_LOADADDR 1000000
519
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]520#define CONFIG_BOOTARGS /* the boot command will set bootargs */
521
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]522#if defined(CONFIG_DONGLE)
523
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]524#define CONFIG_EXTRA_ENV_SETTINGS \
525"bootcmd=run prog_spi_mbrbootcramfs\0" \
526"bootfile=uImage\0" \
527"consoledev=ttyS0\0" \
528"cramfsfile=image.cramfs\0" \
529"dtbaddr=0x00c00000\0" \
530"dtbfile=image.dtb\0" \
531"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
532"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
533"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
534"fileaddr=0x01000000\0" \
535"filesize=0x00080000\0" \
536"flashmbr=sf probe 0; " \
537 "tftp $loadaddr $mbr; " \
538 "sf erase $mbr_offset +$filesize; " \
539 "sf write $loadaddr $mbr_offset $filesize\0" \
540"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
541 "protect off $nor_recoveryaddr +$filesize; " \
542 "erase $nor_recoveryaddr +$filesize; " \
543 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
544 "protect on $nor_recoveryaddr +$filesize\0 " \
545"flashuboot=tftp $ubootaddr $ubootfile; " \
546 "protect off $nor_ubootaddr +$filesize; " \
547 "erase $nor_ubootaddr +$filesize; " \
548 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
549 "protect on $nor_ubootaddr +$filesize\0 " \
550"flashworking=tftp $workingaddr $cramfsfile; " \
551 "protect off $nor_workingaddr +$filesize; " \
552 "erase $nor_workingaddr +$filesize; " \
553 "cp.b $workingaddr $nor_workingaddr $filesize; " \
554 "protect on $nor_workingaddr +$filesize\0 " \
555"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
556"kerneladdr=0x01100000\0" \
557"kernelfile=uImage\0" \
558"loadaddr=0x01000000\0" \
559"mbr=uCP1020d.mbr\0" \
560"mbr_offset=0x00000000\0" \
561"mmbr=uCP1020Quiet.mbr\0" \
562"mmcpart=0:2\0" \
563"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
564 "mmc erase 1 1; " \
565 "mmc write $loadaddr 1 1\0" \
566"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
567 "mmc erase 0x40 0x400; " \
568 "mmc write $loadaddr 0x40 0x400\0" \
569"netdev=eth0\0" \
570"nor_recoveryaddr=0xEC0A0000\0" \
571"nor_ubootaddr=0xEFF80000\0" \
572"nor_workingaddr=0xECFA0000\0" \
573"norbootrecovery=setenv bootargs $recoverybootargs" \
574 " console=$consoledev,$baudrate $othbootargs; " \
575 "run norloadrecovery; " \
576 "bootm $kerneladdr - $dtbaddr\0" \
577"norbootworking=setenv bootargs $workingbootargs" \
578 " console=$consoledev,$baudrate $othbootargs; " \
579 "run norloadworking; " \
580 "bootm $kerneladdr - $dtbaddr\0" \
581"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
582 "setenv cramfsaddr $nor_recoveryaddr; " \
583 "cramfsload $dtbaddr $dtbfile; " \
584 "cramfsload $kerneladdr $kernelfile\0" \
585"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
586 "setenv cramfsaddr $nor_workingaddr; " \
587 "cramfsload $dtbaddr $dtbfile; " \
588 "cramfsload $kerneladdr $kernelfile\0" \
589"prog_spi_mbr=run spi__mbr\0" \
590"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
591"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
592 "run spi__cramfs\0" \
593"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
594 " console=$consoledev,$baudrate $othbootargs; " \
595 "tftp $rootfsaddr $rootfsfile; " \
596 "tftp $loadaddr $kernelfile; " \
597 "tftp $dtbaddr $dtbfile; " \
598 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
599"ramdisk_size=120000\0" \
600"ramdiskfile=rootfs.ext2.gz.uboot\0" \
601"recoveryaddr=0x02F00000\0" \
602"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
603"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
604 "mw.l 0xffe0f008 0x00400000\0" \
605"rootfsaddr=0x02F00000\0" \
606"rootfsfile=rootfs.ext2.gz.uboot\0" \
607"rootpath=/opt/nfsroot\0" \
608"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
609 "protect off 0xeC000000 +$filesize; " \
610 "erase 0xEC000000 +$filesize; " \
611 "cp.b $loadaddr 0xEC000000 $filesize; " \
612 "cmp.b $loadaddr 0xEC000000 $filesize; " \
613 "protect on 0xeC000000 +$filesize\0" \
614"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
615 "protect off 0xeFF80000 +$filesize; " \
616 "erase 0xEFF80000 +$filesize; " \
617 "cp.b $loadaddr 0xEFF80000 $filesize; " \
618 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
619 "protect on 0xeFF80000 +$filesize\0" \
620"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
621 "sf probe 0; sf erase 0x8000 +$filesize; " \
622 "sf write $loadaddr 0x8000 $filesize\0" \
623"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
624 "protect off 0xec0a0000 +$filesize; " \
625 "erase 0xeC0A0000 +$filesize; " \
626 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
627 "protect on 0xec0a0000 +$filesize\0" \
628"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
629 "sf probe 1; sf erase 0 +$filesize; " \
630 "sf write $loadaddr 0 $filesize\0" \
631"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
632 "sf probe 0; sf erase 0 +$filesize; " \
633 "sf write $loadaddr 0 $filesize\0" \
634"tftpflash=tftpboot $loadaddr $uboot; " \
635 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
636 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
637 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
638 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
639 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
640"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
641"ubootaddr=0x01000000\0" \
642"ubootfile=u-boot.bin\0" \
643"ubootd=u-boot4dongle.bin\0" \
644"upgrade=run flashworking\0" \
645"usb_phy_type=ulpi\0 " \
646"workingaddr=0x02F00000\0" \
647"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
648
649#else
650
651#if defined(CONFIG_UCP1020T1)
652
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]653#define CONFIG_EXTRA_ENV_SETTINGS \
654"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
655"bootfile=uImage\0" \
656"consoledev=ttyS0\0" \
657"cramfsfile=image.cramfs\0" \
658"dtbaddr=0x00c00000\0" \
659"dtbfile=image.dtb\0" \
660"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
661"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
662"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
663"fileaddr=0x01000000\0" \
664"filesize=0x00080000\0" \
665"flashmbr=sf probe 0; " \
666 "tftp $loadaddr $mbr; " \
667 "sf erase $mbr_offset +$filesize; " \
668 "sf write $loadaddr $mbr_offset $filesize\0" \
669"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
670 "protect off $nor_recoveryaddr +$filesize; " \
671 "erase $nor_recoveryaddr +$filesize; " \
672 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
673 "protect on $nor_recoveryaddr +$filesize\0 " \
674"flashuboot=tftp $ubootaddr $ubootfile; " \
675 "protect off $nor_ubootaddr +$filesize; " \
676 "erase $nor_ubootaddr +$filesize; " \
677 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
678 "protect on $nor_ubootaddr +$filesize\0 " \
679"flashworking=tftp $workingaddr $cramfsfile; " \
680 "protect off $nor_workingaddr +$filesize; " \
681 "erase $nor_workingaddr +$filesize; " \
682 "cp.b $workingaddr $nor_workingaddr $filesize; " \
683 "protect on $nor_workingaddr +$filesize\0 " \
684"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
685"kerneladdr=0x01100000\0" \
686"kernelfile=uImage\0" \
687"loadaddr=0x01000000\0" \
688"mbr=uCP1020.mbr\0" \
689"mbr_offset=0x00000000\0" \
690"netdev=eth0\0" \
691"nor_recoveryaddr=0xEC0A0000\0" \
692"nor_ubootaddr=0xEFF80000\0" \
693"nor_workingaddr=0xECFA0000\0" \
694"norbootrecovery=setenv bootargs $recoverybootargs" \
695 " console=$consoledev,$baudrate $othbootargs; " \
696 "run norloadrecovery; " \
697 "bootm $kerneladdr - $dtbaddr\0" \
698"norbootworking=setenv bootargs $workingbootargs" \
699 " console=$consoledev,$baudrate $othbootargs; " \
700 "run norloadworking; " \
701 "bootm $kerneladdr - $dtbaddr\0" \
702"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
703 "setenv cramfsaddr $nor_recoveryaddr; " \
704 "cramfsload $dtbaddr $dtbfile; " \
705 "cramfsload $kerneladdr $kernelfile\0" \
706"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
707 "setenv cramfsaddr $nor_workingaddr; " \
708 "cramfsload $dtbaddr $dtbfile; " \
709 "cramfsload $kerneladdr $kernelfile\0" \
710"othbootargs=quiet\0" \
711"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
712 " console=$consoledev,$baudrate $othbootargs; " \
713 "tftp $rootfsaddr $rootfsfile; " \
714 "tftp $loadaddr $kernelfile; " \
715 "tftp $dtbaddr $dtbfile; " \
716 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
717"ramdisk_size=120000\0" \
718"ramdiskfile=rootfs.ext2.gz.uboot\0" \
719"recoveryaddr=0x02F00000\0" \
720"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
721"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
722 "mw.l 0xffe0f008 0x00400000\0" \
723"rootfsaddr=0x02F00000\0" \
724"rootfsfile=rootfs.ext2.gz.uboot\0" \
725"rootpath=/opt/nfsroot\0" \
726"silent=1\0" \
727"tftpflash=tftpboot $loadaddr $uboot; " \
728 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
729 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
730 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
731 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
732 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
733"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
734"ubootaddr=0x01000000\0" \
735"ubootfile=u-boot.bin\0" \
736"upgrade=run flashworking\0" \
737"workingaddr=0x02F00000\0" \
738"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
739
740#else /* For Arcturus Modules */
741
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]742#define CONFIG_EXTRA_ENV_SETTINGS \
743"bootcmd=run norkernel\0" \
744"bootfile=uImage\0" \
745"consoledev=ttyS0\0" \
746"dtbaddr=0x00c00000\0" \
747"dtbfile=image.dtb\0" \
748"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
749"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
750"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
751"fileaddr=0x01000000\0" \
752"filesize=0x00080000\0" \
753"flashmbr=sf probe 0; " \
754 "tftp $loadaddr $mbr; " \
755 "sf erase $mbr_offset +$filesize; " \
756 "sf write $loadaddr $mbr_offset $filesize\0" \
757"flashuboot=tftp $loadaddr $ubootfile; " \
758 "protect off $nor_ubootaddr0 +$filesize; " \
759 "erase $nor_ubootaddr0 +$filesize; " \
760 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
761 "protect on $nor_ubootaddr0 +$filesize; " \
762 "protect off $nor_ubootaddr1 +$filesize; " \
763 "erase $nor_ubootaddr1 +$filesize; " \
764 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
765 "protect on $nor_ubootaddr1 +$filesize\0 " \
766"format0=protect off $part0base +$part0size; " \
767 "erase $part0base +$part0size\0" \
768"format1=protect off $part1base +$part1size; " \
769 "erase $part1base +$part1size\0" \
770"format2=protect off $part2base +$part2size; " \
771 "erase $part2base +$part2size\0" \
772"format3=protect off $part3base +$part3size; " \
773 "erase $part3base +$part3size\0" \
774"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
775"kerneladdr=0x01100000\0" \
776"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
777"kernelfile=uImage\0" \
778"loadaddr=0x01000000\0" \
779"mbr=uCP1020.mbr\0" \
780"mbr_offset=0x00000000\0" \
781"netdev=eth0\0" \
782"nor_ubootaddr0=0xEC000000\0" \
783"nor_ubootaddr1=0xEFF80000\0" \
784"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
785 "run norkernelload; " \
786 "bootm $kerneladdr - $dtbaddr\0" \
787"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
788 "setenv cramfsaddr $part0base; " \
789 "cramfsload $dtbaddr $dtbfile; " \
790 "cramfsload $kerneladdr $kernelfile\0" \
791"part0base=0xEC100000\0" \
792"part0size=0x00700000\0" \
793"part1base=0xEC800000\0" \
794"part1size=0x02000000\0" \
795"part2base=0xEE800000\0" \
796"part2size=0x00800000\0" \
797"part3base=0xEF000000\0" \
798"part3size=0x00F80000\0" \
799"partENVbase=0xEC080000\0" \
800"partENVsize=0x00080000\0" \
801"program0=tftp part0-000000.bin; " \
802 "protect off $part0base +$filesize; " \
803 "erase $part0base +$filesize; " \
804 "cp.b $loadaddr $part0base $filesize; " \
805 "echo Verifying...; " \
806 "cmp.b $loadaddr $part0base $filesize\0" \
807"program1=tftp part1-000000.bin; " \
808 "protect off $part1base +$filesize; " \
809 "erase $part1base +$filesize; " \
810 "cp.b $loadaddr $part1base $filesize; " \
811 "echo Verifying...; " \
812 "cmp.b $loadaddr $part1base $filesize\0" \
813"program2=tftp part2-000000.bin; " \
814 "protect off $part2base +$filesize; " \
815 "erase $part2base +$filesize; " \
816 "cp.b $loadaddr $part2base $filesize; " \
817 "echo Verifying...; " \
818 "cmp.b $loadaddr $part2base $filesize\0" \
819"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
820 " console=$consoledev,$baudrate $othbootargs; " \
821 "tftp $rootfsaddr $rootfsfile; " \
822 "tftp $loadaddr $kernelfile; " \
823 "tftp $dtbaddr $dtbfile; " \
824 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
825"ramdisk_size=120000\0" \
826"ramdiskfile=rootfs.ext2.gz.uboot\0" \
827"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
828 "mw.l 0xffe0f008 0x00400000\0" \
829"rootfsaddr=0x02F00000\0" \
830"rootfsfile=rootfs.ext2.gz.uboot\0" \
831"rootpath=/opt/nfsroot\0" \
832"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
833 "sf probe 0; sf erase 0 +$filesize; " \
834 "sf write $loadaddr 0 $filesize\0" \
835"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
836 "protect off 0xeC000000 +$filesize; " \
837 "erase 0xEC000000 +$filesize; " \
838 "cp.b $loadaddr 0xEC000000 $filesize; " \
839 "cmp.b $loadaddr 0xEC000000 $filesize; " \
840 "protect on 0xeC000000 +$filesize\0" \
841"tftpflash=tftpboot $loadaddr $uboot; " \
842 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
843 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
844 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
845 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
846 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
847"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
848"ubootfile=u-boot.bin\0" \
849"upgrade=run flashuboot\0" \
850"usb_phy_type=ulpi\0 " \
851"boot_nfs= " \
852 "setenv bootargs root=/dev/nfs rw " \
853 "nfsroot=$serverip:$rootpath " \
854 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
855 "console=$consoledev,$baudrate $othbootargs;" \
856 "tftp $loadaddr $bootfile;" \
857 "tftp $fdtaddr $fdtfile;" \
858 "bootm $loadaddr - $fdtaddr\0" \
859"boot_hd = " \
860 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
861 "console=$consoledev,$baudrate $othbootargs;" \
862 "usb start;" \
863 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
864 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
865 "bootm $loadaddr - $fdtaddr\0" \
866"boot_usb_fat = " \
867 "setenv bootargs root=/dev/ram rw " \
868 "console=$consoledev,$baudrate $othbootargs " \
869 "ramdisk_size=$ramdisk_size;" \
870 "usb start;" \
871 "fatload usb 0:2 $loadaddr $bootfile;" \
872 "fatload usb 0:2 $fdtaddr $fdtfile;" \
873 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
874 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
875"boot_usb_ext2 = " \
876 "setenv bootargs root=/dev/ram rw " \
877 "console=$consoledev,$baudrate $othbootargs " \
878 "ramdisk_size=$ramdisk_size;" \
879 "usb start;" \
880 "ext2load usb 0:4 $loadaddr $bootfile;" \
881 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
882 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
883 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
884"boot_nor = " \
885 "setenv bootargs root=/dev/$jffs2nor rw " \
886 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
887 "bootm $norbootaddr - $norfdtaddr\0 " \
888"boot_ram = " \
889 "setenv bootargs root=/dev/ram rw " \
890 "console=$consoledev,$baudrate $othbootargs " \
891 "ramdisk_size=$ramdisk_size;" \
892 "tftp $ramdiskaddr $ramdiskfile;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
896
897#endif
898#endif
899
900#endif /* __CONFIG_H */