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git01.mediatek.com / filogic / uboot / 0539665cef75c77d28eb05f61d73adefeec24557 / . / arch / arm / mach-k3 / r5 / am62x / clk-data.c
blob: d7bfed0e031c463c4229202c313a90d848d7cb72 [file] [log] [blame]
Suman Annaa9768c92022-05-25 13:38:43 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * AM62X specific clock platform data
4 *
5 * This file is auto generated. Please do not hand edit and report any issues
6 * to Dave Gerlach <d-gerlach@ti.com>.
7 *
8 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
9 */
10
11#include <linux/clk-provider.h>
12#include "k3-clk.h"
13
14static const char * const gluelogic_hfosc0_clkout_parents[] = {
15 NULL,
16 NULL,
17 "osc_24_mhz",
18 "osc_25_mhz",
19 "osc_26_mhz",
20 NULL,
21};
22
23static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
24 "board_0_mmc0_clklb_out",
25 "board_0_mmc0_clk_out",
26};
27
28static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
29 "board_0_mmc1_clklb_out",
30 "board_0_mmc1_clk_out",
31};
32
33static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
34 "board_0_ospi0_dqs_out",
35 "board_0_ospi0_lbclko_out",
36};
37
38static const char * const main_usb0_refclk_sel_out0_parents[] = {
39 "gluelogic_hfosc0_clkout",
40 "postdiv4_16ff_main_0_hsdivout8_clk",
41};
42
43static const char * const main_usb1_refclk_sel_out0_parents[] = {
44 "gluelogic_hfosc0_clkout",
45 "postdiv4_16ff_main_0_hsdivout8_clk",
46};
47
48static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
49 "gluelogic_hfosc0_clkout",
50 "hsdiv4_16fft_main_0_hsdivout0_clk",
51};
52
53static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
54 "gluelogic_hfosc0_clkout",
55 "hsdiv4_16fft_mcu_0_hsdivout0_clk",
56};
57
58static const char * const clkout0_ctrl_out0_parents[] = {
59 "hsdiv4_16fft_main_2_hsdivout1_clk",
Marcel Ziswilerac4518a2023-08-04 12:08:06 +0200[diff] [blame]60 "hsdiv4_16fft_main_2_hsdivout1_clk10",
Suman Annaa9768c92022-05-25 13:38:43 +0530[diff] [blame]61};
62
63static const char * const clk_32k_rc_sel_out0_parents[] = {
64 "gluelogic_rcosc_clk_1p0v_97p65k",
65 "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
66 "clk_32k_rc_sel_div_clkout",
67 "gluelogic_lfosc0_clkout",
68};
69
70static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
71 "postdiv4_16ff_main_2_hsdivout5_clk",
72 "postdiv4_16ff_main_0_hsdivout6_clk",
73 "board_0_cp_gemac_cpts0_rft_clk_out",
74 NULL,
75 "board_0_mcu_ext_refclk0_out",
76 "board_0_ext_refclk1_out",
77 "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
78 "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
79};
80
81static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
82 "postdiv4_16ff_main_0_hsdivout5_clk",
83 "hsdiv4_16fft_main_2_hsdivout2_clk",
84};
85
86static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
87 "postdiv4_16ff_main_0_hsdivout5_clk",
88 "hsdiv4_16fft_main_2_hsdivout2_clk",
89};
90
91static const char * const main_gtcclk_sel_out0_parents[] = {
92 "postdiv4_16ff_main_2_hsdivout5_clk",
93 "postdiv4_16ff_main_0_hsdivout6_clk",
94 "board_0_cp_gemac_cpts0_rft_clk_out",
95 NULL,
96 "board_0_mcu_ext_refclk0_out",
97 "board_0_ext_refclk1_out",
98 "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
99 "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
100};
101
102static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
103 "hsdiv4_16fft_main_0_hsdivout1_clk",
104 "postdiv1_16fft_main_1_hsdivout5_clk",
105};
106
107static const char * const wkup_clkout_sel_out0_parents[] = {
108 "gluelogic_hfosc0_clkout",
109 "gluelogic_lfosc0_clkout",
110 "hsdiv4_16fft_main_0_hsdivout2_clk",
111 "hsdiv4_16fft_main_1_hsdivout2_clk",
112 "postdiv4_16ff_main_2_hsdivout9_clk",
113 "clk_32k_rc_sel_out0",
114 "gluelogic_rcosc_clkout",
115 "gluelogic_hfosc0_clkout",
116};
117
118static const char * const wkup_clksel_out0_parents[] = {
119 "hsdiv1_16fft_main_15_hsdivout0_clk",
120 "hsdiv4_16fft_mcu_0_hsdivout0_clk",
121};
122
123static const char * const main_usart0_fclk_sel_out0_parents[] = {
124 "usart_programmable_clock_divider_out0",
125 "hsdiv4_16fft_main_1_hsdivout1_clk",
126};
127
128static const struct clk_data clk_list[] = {
129 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
130 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
131 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
132 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
133 CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
134 CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
135 CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
136 CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
137 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
138 CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
139 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
140 CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
141 CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
142 CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
143 CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
144 CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
145 CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
146 CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
147 CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
148 CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
149 CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
150 CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
151 CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
152 CLK_FIXED_RATE("board_0_tck_out", 0, 0),
153 CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
154 CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
155 CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
156 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
157 CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
158 CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
159 CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
160 CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
161 CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
162 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
163 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
164 CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
165 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
166 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
167 CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
168 CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
169 CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
170 CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
171 CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
172 CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
173 CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
174 CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
175 CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
176 CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
177 CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
178 CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
179 CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
180 CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
181 CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
182 CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
183 CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
184 CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
185 CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
186 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
187 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
188 CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
189 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
190 CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
191 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
192 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
193 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
194 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
195 CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
196 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
197 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
Marcel Ziswilerac4518a2023-08-04 12:08:06 +0200[diff] [blame]198 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
Suman Annaa9768c92022-05-25 13:38:43 +0530[diff] [blame]199 CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
200 CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
201 CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
202 CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
203 CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
204 CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
205 CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
206 CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
207 CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
208 CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
209 CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
210 CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
211 CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
212 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
213 CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
214 CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
215 CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
216 CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
217 CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
218 CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
219 CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
220};
221
222static const struct dev_clk soc_dev_clk_data[] = {
223 DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
224 DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
225 DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
226 DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
227 DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
228 DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
229 DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
230 DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
231 DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
232 DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
233 DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
234 DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
235 DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
236 DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
237 DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
238 DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
239 DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
240 DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
241 DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
242 DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
243 DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
244 DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
245 DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
246 DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
247 DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
248 DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
249 DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
250 DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
251 DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
252 DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
253 DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
254 DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
255 DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
256 DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
257 DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
258 DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
259 DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
260 DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
261 DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
262 DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
263 DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
264 DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
265 DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
266 DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
267 DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
268 DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
269 DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
270 DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
271 DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
272 DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
273 DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
274 DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
275 DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
276 DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
277 DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
278 DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
279 DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
280 DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
281 DEV_CLK(61, 9, "wkup_clksel_out0"),
282 DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
283 DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
284 DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
285 DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
286 DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
287 DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
288 DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
289 DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
290 DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
291 DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
292 DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
293 DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
294 DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
295 DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
296 DEV_CLK(95, 2, "wkup_clksel_out0"),
297 DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
298 DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
299 DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
300 DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
301 DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
302 DEV_CLK(107, 0, "wkup_clksel_out0"),
303 DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
304 DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
305 DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
306 DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
307 DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
308 DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
309 DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
310 DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
311 DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
312 DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
313 DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
314 DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
315 DEV_CLK(157, 20, "clkout0_ctrl_out0"),
316 DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
Marcel Ziswilerac4518a2023-08-04 12:08:06 +0200[diff] [blame]317 DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
Suman Annaa9768c92022-05-25 13:38:43 +0530[diff] [blame]318 DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
319 DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
320 DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
321 DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
322 DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
323 DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
324 DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
325 DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
326 DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
327 DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
328 DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
329 DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
330 DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
331 DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
332 DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
333 DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
334 DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
335 DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
336 DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
337 DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
338 DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
339 DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
340 DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
341 DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
342 DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
343 DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
344 DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
345 DEV_CLK(161, 10, "board_0_tck_out"),
346 DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
347 DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
348 DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
349 DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
350 DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
351 DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
352 DEV_CLK(162, 10, "board_0_tck_out"),
353 DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
354 DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
355 DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
356 DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
357 DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
358 DEV_CLK(170, 1, "board_0_tck_out"),
359 DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
360};
361
362const struct ti_k3_clk_platdata am62x_clk_platdata = {
363 .clk_list = clk_list,
364 .clk_list_cnt = 90,
365 .soc_dev_clk_data = soc_dev_clk_data,
366 .soc_dev_clk_data_cnt = 137,
367};