Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Sentec Cobra Board. |
| 4 | * |
| 5 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* --- |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 9 | * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 10 | * Date: 2004-03-29 |
| 11 | * Author: Florian Schlote |
| 12 | * |
| 13 | * For a description of configuration options please refer also to the |
| 14 | * general u-boot-1.x.x/README file |
| 15 | * --- |
| 16 | */ |
| 17 | |
| 18 | /* --- |
| 19 | * board/config.h - configuration options, board specific |
| 20 | * --- |
| 21 | */ |
| 22 | |
| 23 | #ifndef _CONFIG_COBRA5272_H |
| 24 | #define _CONFIG_COBRA5272_H |
| 25 | |
| 26 | /* --- |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 27 | * Defines processor clock - important for correct timings concerning serial |
| 28 | * interface etc. |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 29 | * --- |
| 30 | */ |
| 31 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | #define CONFIG_SYS_CLK 66000000 |
| 33 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 34 | |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 35 | /* Enable Dma Timer */ |
| 36 | #define CONFIG_MCFTMR |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 37 | |
| 38 | /* --- |
| 39 | * Define baudrate for UART1 (console output, tftp, ...) |
| 40 | * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 41 | * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 42 | * interface |
| 43 | * --- |
| 44 | */ |
| 45 | |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 46 | #define CONFIG_MCFUART |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_UART_PORT (0) |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 48 | |
| 49 | /* --- |
| 50 | * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change |
| 51 | * timeout acc. to your needs |
| 52 | * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 |
| 53 | * for 10 sec |
| 54 | * --- |
| 55 | */ |
| 56 | |
| 57 | #if 0 |
| 58 | #define CONFIG_WATCHDOG |
| 59 | #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ |
| 60 | #endif |
| 61 | |
| 62 | /* --- |
| 63 | * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different |
| 64 | * bootloader residing in flash ('chainloading'); if you want to use |
| 65 | * chainloading or want to compile a u-boot binary that can be loaded into |
| 66 | * RAM via BDM set |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 67 | * "#if 0" to "#if 1" |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 68 | * You will need a first stage bootloader then, e. g. colilo or a working BDM |
| 69 | * cable (Background Debug Mode) |
| 70 | * |
| 71 | * Setting #if 0: u-boot will start from flash and relocate itself to RAM |
| 72 | * |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 73 | * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 74 | * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) |
| 75 | * |
| 76 | * --- |
| 77 | */ |
| 78 | |
| 79 | #if 0 |
| 80 | #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ |
| 81 | #endif |
| 82 | |
| 83 | /* --- |
| 84 | * Configuration for environment |
| 85 | * Environment is embedded in u-boot in the second sector of the flash |
| 86 | * --- |
| 87 | */ |
| 88 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 89 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 90 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 91 | env/embedded.o(.text); |
Jon Loeliger | 37ec35e | 2007-07-04 22:31:56 -0500 | [diff] [blame] | 92 | |
| 93 | /* |
Jon Loeliger | e54e77a | 2007-07-10 09:29:01 -0500 | [diff] [blame] | 94 | * BOOTP options |
| 95 | */ |
| 96 | #define CONFIG_BOOTP_BOOTFILESIZE |
Jon Loeliger | e54e77a | 2007-07-10 09:29:01 -0500 | [diff] [blame] | 97 | |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 98 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | b316245 | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 99 | # define CONFIG_MII_INIT 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | # define CONFIG_SYS_DISCOVER_PHY |
| 101 | # define CONFIG_SYS_RX_ETH_BUFFER 8 |
| 102 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 104 | # ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 105 | # define FECDUPLEX FULL |
| 106 | # define FECSPEED _100BASET |
| 107 | # else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 109 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 110 | # endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
TsiChungLiew | cfa2b48 | 2007-08-15 19:41:06 -0500 | [diff] [blame] | 112 | #endif |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | *----------------------------------------------------------------------------- |
| 116 | * Define user parameters that have to be customized most likely |
| 117 | *----------------------------------------------------------------------------- |
| 118 | */ |
| 119 | |
| 120 | /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ |
| 121 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 122 | /* The following settings will be contained in the environment block ; if you |
| 123 | want to use a neutral environment all those settings can be manually set in |
| 124 | u-boot: 'set' command */ |
| 125 | |
| 126 | #if 0 |
| 127 | |
| 128 | #define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please |
| 129 | enter a valid image address in flash */ |
| 130 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 131 | /* User network settings */ |
| 132 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 133 | #define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ |
| 134 | #define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ |
| 135 | |
| 136 | #endif |
| 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 139 | from which user programs will be started */ |
| 140 | |
| 141 | /*---*/ |
| 142 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 143 | /* |
| 144 | *----------------------------------------------------------------------------- |
| 145 | * End of user parameters to be customized |
| 146 | *----------------------------------------------------------------------------- |
| 147 | */ |
| 148 | |
| 149 | /* --- |
| 150 | * Defines memory range for test |
| 151 | * --- |
| 152 | */ |
| 153 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 154 | /* --- |
| 155 | * Low Level Configuration Settings |
| 156 | * (address mappings, register initial values, etc.) |
| 157 | * You should know what you are doing if you make changes here. |
| 158 | * --- |
| 159 | */ |
| 160 | |
| 161 | /* --- |
| 162 | * Base register address |
| 163 | * --- |
| 164 | */ |
| 165 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 167 | |
| 168 | /* --- |
| 169 | * System Conf. Reg. & System Protection Reg. |
| 170 | * --- |
| 171 | */ |
| 172 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_SCR 0x0003 |
| 174 | #define CONFIG_SYS_SPR 0xffff |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 175 | |
| 176 | /* --- |
| 177 | * Ethernet settings |
| 178 | * --- |
| 179 | */ |
| 180 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_DISCOVER_PHY |
| 182 | #define CONFIG_SYS_ENET_BD_BASE 0x780000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 183 | |
| 184 | /*----------------------------------------------------------------------- |
| 185 | * Definitions for initial stack pointer and data area (in internal SRAM) |
| 186 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 188 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 191 | |
| 192 | /*----------------------------------------------------------------------- |
| 193 | * Start addresses for the final memory configuration |
| 194 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 196 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 198 | |
| 199 | /* |
| 200 | *------------------------------------------------------------------------- |
| 201 | * RAM SIZE (is defined above) |
| 202 | *----------------------------------------------------------------------- |
| 203 | */ |
| 204 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 205 | /* #define CONFIG_SYS_SDRAM_SIZE 16 */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 206 | |
| 207 | /* |
| 208 | *----------------------------------------------------------------------- |
| 209 | */ |
| 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 212 | |
| 213 | #ifdef CONFIG_MONITOR_IS_IN_RAM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 215 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 217 | #endif |
| 218 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
| 220 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
| 221 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 222 | |
| 223 | /* |
| 224 | * For booting Linux, the board info and command line data |
| 225 | * have to be in the first 8 MB of memory, since this is |
| 226 | * the maximum mapped by the Linux kernel during initialization ?? |
| 227 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 228 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 229 | |
| 230 | /*----------------------------------------------------------------------- |
| 231 | * FLASH organization |
| 232 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 233 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 234 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ |
| 235 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 236 | |
| 237 | /*----------------------------------------------------------------------- |
| 238 | * Cache Configuration |
| 239 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 240 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 241 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 242 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 243 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 244 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 245 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 246 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 247 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 248 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 249 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 250 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
| 251 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 252 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 253 | CF_CACR_EUSP) |
| 254 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 255 | /*----------------------------------------------------------------------- |
| 256 | * Memory bank definitions |
| 257 | * |
| 258 | * Please refer also to Motorola Coldfire user manual - Chapter XXX |
| 259 | * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf> |
| 260 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 |
| 262 | #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 263 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_BR1_PRELIM 0 |
| 265 | #define CONFIG_SYS_OR1_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 266 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_BR2_PRELIM 0 |
| 268 | #define CONFIG_SYS_OR2_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 269 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | #define CONFIG_SYS_BR3_PRELIM 0 |
| 271 | #define CONFIG_SYS_OR3_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 272 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 273 | #define CONFIG_SYS_BR4_PRELIM 0 |
| 274 | #define CONFIG_SYS_OR4_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 275 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #define CONFIG_SYS_BR5_PRELIM 0 |
| 277 | #define CONFIG_SYS_OR5_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 278 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 279 | #define CONFIG_SYS_BR6_PRELIM 0 |
| 280 | #define CONFIG_SYS_OR6_PRELIM 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 281 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_BR7_PRELIM 0x00000701 |
| 283 | #define CONFIG_SYS_OR7_PRELIM 0xFF00007C |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 284 | |
| 285 | /*----------------------------------------------------------------------- |
| 286 | * LED config |
| 287 | */ |
| 288 | #define LED_STAT_0 0xffff /*all LEDs off*/ |
| 289 | #define LED_STAT_1 0xfffe |
| 290 | #define LED_STAT_2 0xfffd |
| 291 | #define LED_STAT_3 0xfffb |
| 292 | #define LED_STAT_4 0xfff7 |
| 293 | #define LED_STAT_5 0xffef |
| 294 | #define LED_STAT_6 0xffdf |
| 295 | #define LED_STAT_7 0xff00 /*all LEDs on*/ |
| 296 | |
| 297 | /*----------------------------------------------------------------------- |
| 298 | * Port configuration (GPIO) |
| 299 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 300 | #define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 301 | GPIO*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 303 | (1^=output, 0^=input) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 304 | #define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ |
| 305 | #define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 306 | configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 307 | #define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ |
| 308 | #define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ |
| 309 | #define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 310 | |
| 311 | #endif /* _CONFIG_COBRA5272_H */ |