| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ZYNQ=y | ||||
| Michal Simek | 9254387 | 2016-12-16 11:57:17 +0100 | [diff] [blame] | 3 | CONFIG_SYS_TEXT_BASE=0x4000000 |
| Michal Simek | 96794a7 | 2017-12-13 10:35:06 +0100 | [diff] [blame] | 4 | CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011" |
| Michal Simek | c7abf8d | 2017-12-01 13:50:33 +0100 | [diff] [blame] | 5 | CONFIG_SPL_STACK_R_ADDR=0x200000 |
| Tom Rini | d8532af | 2017-06-02 11:03:50 -0400 | [diff] [blame] | 6 | # CONFIG_SPL_FAT_SUPPORT is not set |
| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 7 | CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" |
| Michal Simek | 0519701 | 2017-12-15 07:46:12 +0100 | [diff] [blame^] | 8 | CONFIG_DEBUG_UART=y |
| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 9 | CONFIG_FIT=y |
| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 10 | CONFIG_FIT_SIGNATURE=y |
| Jagan Teki | 4c57e4c | 2017-01-21 11:48:33 +0100 | [diff] [blame] | 11 | CONFIG_FIT_VERBOSE=y |
| Lokesh Vutla | fbad370 | 2016-10-08 14:41:44 -0400 | [diff] [blame] | 12 | # CONFIG_DISPLAY_CPUINFO is not set |
| Simon Glass | ffe1976 | 2016-09-12 23:18:22 -0600 | [diff] [blame] | 13 | CONFIG_SPL=y |
| Michal Simek | c7abf8d | 2017-12-01 13:50:33 +0100 | [diff] [blame] | 14 | CONFIG_SPL_STACK_R=y |
| Heiko Schocher | 1d12ba2 | 2016-10-06 07:55:15 +0200 | [diff] [blame] | 15 | CONFIG_SPL_OS_BOOT=y |
| Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 16 | CONFIG_HUSH_PARSER=y |
| Siva Durga Prasad Paladugu | 59d461e | 2016-01-11 12:01:10 +0530 | [diff] [blame] | 17 | CONFIG_SYS_PROMPT="Zynq> " |
| Michal Simek | 12e30a6 | 2017-11-02 10:38:16 +0100 | [diff] [blame] | 18 | CONFIG_CMD_BOOTZ=y |
| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 19 | # CONFIG_CMD_FLASH is not set |
| Simon Glass | 80cb189 | 2017-05-17 03:25:21 -0600 | [diff] [blame] | 20 | CONFIG_CMD_FPGA_LOADBP=y |
| 21 | CONFIG_CMD_FPGA_LOADFS=y | ||||
| 22 | CONFIG_CMD_FPGA_LOADMK=y | ||||
| 23 | CONFIG_CMD_FPGA_LOADP=y | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 24 | CONFIG_CMD_GPIO=y |
| Tom Rini | 78873cd | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 25 | CONFIG_CMD_NAND_LOCK_UNLOCK=y |
| Michal Simek | b40e5b6 | 2015-07-22 11:39:04 +0200 | [diff] [blame] | 26 | # CONFIG_CMD_SETEXPR is not set |
| Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 27 | CONFIG_CMD_TFTPPUT=y |
| 28 | CONFIG_CMD_DHCP=y | ||||
| Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 29 | CONFIG_CMD_MII=y |
| Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 30 | CONFIG_CMD_PING=y |
| Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 31 | CONFIG_CMD_CACHE=y |
| Masahiro Yamada | 88e2e36 | 2015-07-17 20:26:06 +0900 | [diff] [blame] | 32 | CONFIG_NET_RANDOM_ETHADDR=y |
| Nathan Rossi | dd71c8a | 2016-01-08 03:00:46 +1000 | [diff] [blame] | 33 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| Michal Simek | 216f637 | 2017-11-03 15:53:56 +0100 | [diff] [blame] | 34 | CONFIG_FPGA_XILINX=y |
| Jagan Teki | 4c57e4c | 2017-01-21 11:48:33 +0100 | [diff] [blame] | 35 | # CONFIG_MMC is not set |
| Adam Ford | 42efb61 | 2017-08-07 17:37:18 -0400 | [diff] [blame] | 36 | CONFIG_NAND=y |
| Siva Durga Prasad Paladugu | ddb9f06 | 2016-09-27 10:55:47 +0530 | [diff] [blame] | 37 | CONFIG_NAND_ZYNQ=y |
| Michal Simek | 3d7285f | 2015-11-30 14:34:52 +0100 | [diff] [blame] | 38 | CONFIG_ZYNQ_GEM=y |
| Michal Simek | 0519701 | 2017-12-15 07:46:12 +0100 | [diff] [blame^] | 39 | CONFIG_DEBUG_UART_ZYNQ=y |
| 40 | CONFIG_DEBUG_UART_BASE=0xe0001000 | ||||
| 41 | CONFIG_DEBUG_UART_CLOCK=50000000 | ||||
| 42 | CONFIG_DEBUG_UART_ANNOUNCE=y | ||||
| Michal Simek | ab75453 | 2017-11-06 09:16:05 +0100 | [diff] [blame] | 43 | CONFIG_ZYNQ_SERIAL=y |