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git01.mediatek.com / filogic / uboot / 05154a270d8352597ba74fcf6c85eb61c549c2be / . / arch / arm / cpu / armv7 / uniphier / Kconfig
blob: 36b7f11fbeb7fb28db48ed8257d05b1294115843 [file] [log] [blame]
Masahiro Yamada82069432014-10-03 19:21:07 +0900[diff] [blame]1menu "Panasonic UniPhier platform"
2 depends on ARCH_UNIPHIER
3
Masahiro Yamada82069432014-10-03 19:21:07 +0900[diff] [blame]4config SYS_SOC
Masahiro Yamada82069432014-10-03 19:21:07 +0900[diff] [blame]5 default "uniphier"
6
7config SYS_CONFIG_NAME
Masahiro Yamada82069432014-10-03 19:21:07 +0900[diff] [blame]8 default "ph1_pro4" if MACH_PH1_PRO4
9 default "ph1_ld4" if MACH_PH1_LD4
10 default "ph1_sld8" if MACH_PH1_SLD8
11
12choice
13 prompt "UniPhier SoC select"
14
15config MACH_PH1_PRO4
16 bool "PH1-Pro4"
17
18config MACH_PH1_LD4
19 bool "PH1-LD4"
20
21config MACH_PH1_SLD8
22 bool "PH1-sLD8"
23
24endchoice
25
Masahiro Yamada4b5e7e32014-10-20 20:45:22 +0900[diff] [blame]26config CMD_PINMON
27 bool "Enable boot mode pins monitor command"
28 depends on !SPL_BUILD
29 default y
30 help
31 The command "pinmon" shows the state of the boot mode pins.
32 The boot mode pins are latched when the system reset is deasserted
33 and determine which device the system should load a boot image from.
34
Masahiro Yamada05154a22014-11-11 22:18:22 +0900[diff] [blame^]35config SOC_INIT
36 bool
37 default SPL_BUILD
38
Masahiro Yamadab0c79042014-11-06 20:16:42 +0900[diff] [blame]39config DRAM_INIT
40 bool
41 default SPL_BUILD
42
43choice
44 prompt "DDR3 Frequency select"
45 depends on DRAM_INIT
46
47config DDR_FREQ_1600
48 bool "DDR3 1600"
49 depends on MACH_PH1_PRO4 || MACH_PH1_LD4
50
51config DDR_FREQ_1333
52 bool "DDR3 1333"
53 depends on MACH_PH1_LD4 || MACH_PH1_SLD8
54
55endchoice
56
57config DDR_FREQ
58 int
59 default 1333 if DDR_FREQ_1333
60 default 1600 if DDR_FREQ_1600
61
Masahiro Yamada82069432014-10-03 19:21:07 +0900[diff] [blame]62endmenu