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git01.mediatek.com / filogic / uboot / 04e97e091c6d5b6fc80fd8469326849f7aca5bb3 / . / board / zpc1900 / zpc1900.c
blob: 103ef714fd19ba105ed77a303bdccd02c1dec80b [file] [log] [blame]
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]1/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]5 * (C) Copyright 2003-2005 Arabella Software Ltd.
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]6 * Yuli Barcohen <yuli@arabellasw.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <ioports.h>
29#include <mpc8260.h>
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]30#include <miiphy.h>
31
32/*
33 * I/O Port configuration table
34 *
35 * if conf is 1, then that port pin will be configured at boot time
36 * according to the five values podr/pdir/ppar/psor/pdat for that entry
37 */
38
39const iop_conf_t iop_conf_tab[4][32] = {
40
41 /* Port A */
42 { /* conf ppar psor pdir podr pdat */
43 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
44 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
45 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
46 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
47 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
48 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
49 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
50 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
51 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
52 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
53 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
54 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
55 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
56 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
57 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
58 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
59 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
60 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
61 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
62 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
63 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
64 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
65 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */
66 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
67 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
68 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
69 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
70 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
71 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
72 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
73 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
74 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
75 },
76
77 /* Port B */
78 { /* conf ppar psor pdir podr pdat */
79 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
80 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
81 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
82 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
83 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
84 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
85 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
86 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
87 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
88 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
89 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
90 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
91 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
92 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
93 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
94 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
95 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
96 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
97 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
98 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
99 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
100 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
101 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
102 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
103 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
104 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
105 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
106 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
107 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
108 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
109 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
111 },
112
113 /* Port C */
114 { /* conf ppar psor pdir podr pdat */
115 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
116 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
117 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */
118 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
119 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
120 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
121 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
122 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
123 /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
124 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
125 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
126 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
127 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
128 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
129 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
130 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
131 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
132 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */
133 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
134 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
135 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
136 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */
137 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */
138 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
139 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
140 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
141 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
142 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
143 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
144 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
145 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
146 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
147 },
148
149 /* Port D */
150 { /* conf ppar psor pdir podr pdat */
151 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
152 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
153 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
154 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
155 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
156 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
157 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
158 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
159 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
160 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
161 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
162 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
163 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
164 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
165 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
166 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]167 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
168 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]169 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
170 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
171 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
172 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
173 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
174 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
175 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
176 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
177 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
178 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
179 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
181 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
182 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
183 }
184};
185
186#ifdef CFG_NVRAM_ACCESS_ROUTINE
187void *nvram_read(void *dest, long src, size_t count)
188{
189 return memcpy(dest, (const void *)src, count);
190}
191
192void nvram_write(long dest, const void *src, size_t count)
193{
194 vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555);
195 vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA);
196 vu_char *d = (vu_char *)dest;
197 const uchar *s = (const uchar *)src;
198
199 /* Unprotect the EEPROM */
200 *p1 = 0xAA;
201 *p2 = 0x55;
202 *p1 = 0x80;
203 *p1 = 0xAA;
204 *p2 = 0x55;
205 *p1 = 0x20;
206 udelay(10000);
207
208 /* Write the data to the EEPROM */
209 while (count--) {
210 *d++ = *s++;
211 while (*(d - 1) != *(s - 1))
212 /* wait */;
213 }
214
215 /* Protect the EEPROM */
216 *p1 = 0xAA;
217 *p2 = 0x55;
218 *p1 = 0xA0;
219 udelay(10000);
220}
221#endif /* CFG_NVRAM_ACCESS_ROUTINE */
222
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]223phys_size_t initdram(int board_type)
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]224{
225 vu_char *bcsr = (vu_char *)CFG_BCSR;
226 volatile immap_t *immap = (immap_t *)CFG_IMMR;
227 volatile memctl8260_t *memctl = &immap->im_memctl;
228 vu_char *ramaddr;
229 uchar c = 0xFF;
230 long int msize = CFG_SDRAM_SIZE;
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]231 int i;
232
233 if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]234 immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]235 immap->im_siu_conf.sc_siumcr =
236 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
237 | SIUMCR_LBPC01;
238 }
239
240#ifndef CFG_RAMBOOT
241 immap->im_siu_conf.sc_ppc_acr = 0x03;
242 immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
243 immap->im_siu_conf.sc_tescr1 = 0x00004000;
244
245 memctl->memc_mptpr = CFG_MPTPR;
246
247#ifdef CFG_LSDRAM_BASE
248 /*
249 Initialise local bus SDRAM only if the pins
250 are configured as local bus pins and not as PCI.
251 */
252 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
253 memctl->memc_lsrt = CFG_LSRT;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]254 memctl->memc_or4 = CFG_LSDRAM_OR;
255 memctl->memc_br4 = CFG_LSDRAM_BR;
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]256 ramaddr = (vu_char *)CFG_LSDRAM_BASE;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]257 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]258 *ramaddr = c;
259 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
260 for (i = 0; i < 8; i++)
261 *ramaddr = c;
262 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW;
263 *ramaddr = c;
264 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN;
265 }
266#endif /* CFG_LSDRAM_BASE */
267
268 /* Initialise 60x bus SDRAM */
269 memctl->memc_psrt = CFG_PSRT;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]270 memctl->memc_or2 = CFG_PSDRAM_OR;
271 memctl->memc_br2 = CFG_PSDRAM_BR;
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]272 /*
273 * The mode data for Mode Register Write command must appear on
274 * the address lines during a mode-set cycle. It is driven by
275 * the memory controller, in single PowerQUICC II mode,
276 * according to PSDMR[CL] and PSDMR[BL] fields. In
277 * 60x-compatible mode, software must drive the correct value on
278 * the address lines. BL=0 because for 64-bit port size burst
279 * length must be 4.
280 */
281 ramaddr = (vu_char *)(CFG_SDRAM_BASE |
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]282 ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
283 memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]284 *ramaddr = c;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]285 memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]286 for (i = 0; i < 8; i++)
287 *ramaddr = c;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]288 memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]289 *ramaddr = c;
Wolfgang Denk4c15d702006-03-12 01:45:44 +0100[diff] [blame]290 memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]291 *ramaddr = c;
292#endif /* CFG_RAMBOOT */
293
294 /* Return total 60x bus SDRAM size */
295 return msize * 1024 * 1024;
296}
297
298int checkboard(void)
299{
300 vu_char *bcsr = (vu_char *)CFG_BCSR;
301
302 printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
303 return 0;
304}