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git01.mediatek.com / filogic / uboot / 04e97e091c6d5b6fc80fd8469326849f7aca5bb3 / . / board / netta / dsp.c
blob: 3739e16d6f8eb41bd5c995f7707c995f6f75fcdf [file] [log] [blame]
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1/*
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]2 * Intracom TI6711/TI6412 DSP
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]3 */
4
5#include <common.h>
6#include <post.h>
7
8#include "mpc8xx.h"
9
10struct ram_range {
11 u32 start;
12 u32 size;
13};
14
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]15#if defined(CONFIG_NETTA_6412)
16
17static const struct ram_range int_ram[] = {
18 { 0x00000000U, 0x00040000U },
19};
20
21static const struct ram_range ext_ram[] = {
22 { 0x80000000U, 0x00100000U },
23};
24
25static const struct ram_range ranges[] = {
26 { 0x00000000U, 0x00040000U },
27 { 0x80000000U, 0x00100000U },
28};
29
30static inline u16 bit_invert(u16 d)
31{
32 register u8 i;
33 register u16 r;
34 register u16 bit;
35
36 r = 0;
37 for (i = 0; i < 16; i++) {
38 bit = d & (1 << i);
39 if (bit != 0)
40 r |= 1 << (15 - i);
41 }
42 return r;
43}
44
45#else
46
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]47static const struct ram_range int_ram[] = {
48 { 0x00000000U, 0x00010000U },
49};
50
51static const struct ram_range ext_ram[] = {
52 { 0x80000000U, 0x00100000U },
53};
54
55static const struct ram_range ranges[] = {
56 { 0x00000000U, 0x00010000U },
57 { 0x80000000U, 0x00100000U },
58};
59
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]60#endif
61
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]62/*******************************************************************************************************/
63
64static inline int addr_in_int_ram(u32 addr)
65{
66 int i;
67
68 for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
69 if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
70 return 1;
71
72 return 0;
73}
74
75static inline int addr_in_ext_ram(u32 addr)
76{
77 int i;
78
79 for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
80 if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
81 return 1;
82
83 return 0;
84}
85
86/*******************************************************************************************************/
87
88#define DSP_HPIC 0x0
89#define DSP_HPIA 0x4
90#define DSP_HPID1 0x8
91#define DSP_HPID2 0xC
92
93static u32 dummy_delay;
94static volatile u32 *ti6711_delay = &dummy_delay;
95
96static inline void dsp_go_slow(void)
97{
98 volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]99#if defined(CONFIG_NETTA_6412)
100 memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
101#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]102 memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]103#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]104 memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
105
106 ti6711_delay = (u32 *)DUMMY_BASE;
107}
108
109static inline void dsp_go_fast(void)
110{
111 volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]112#if defined(CONFIG_NETTA_6412)
113 memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
114#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]115 memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]116#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]117 memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
118
119 ti6711_delay = &dummy_delay;
120}
121
122/*******************************************************************************************************/
123
124static inline void dsp_delay(void)
125{
126 /* perform ti6711_delay chip select read to have a small delay */
127 (void) *(volatile u32 *)ti6711_delay;
128}
129
130static inline u16 dsp_read_hpic(void)
131{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]132#if defined(CONFIG_NETTA_6412)
133 return bit_invert(*((volatile u16 *)DSP_BASE));
134#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]135 return *((volatile u16 *)DSP_BASE);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]136#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]137}
138
139static inline void dsp_write_hpic(u16 val)
140{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]141#if defined(CONFIG_NETTA_6412)
142 *((volatile u16 *)DSP_BASE) = bit_invert(val);
143#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]144 *((volatile u16 *)DSP_BASE) = val;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]145#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]146}
147
148static inline void dsp_reset(void)
149{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]150#if defined(CONFIG_NETTA_6412)
151 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
152 udelay(500);
153 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15));
154 udelay(500);
155#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]156 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
157 udelay(250);
158 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7));
159 udelay(250);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]160#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]161}
162
163static inline u32 dsp_read_hpic_word(u32 addr)
164{
165 u32 val;
166 volatile u16 *p;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]167#if defined(CONFIG_NETTA_6412)
168 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
169
170 val = ((u32) bit_invert(p[0]) << 16);
171 /* dsp_delay(); */
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]172
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]173 val |= bit_invert(p[1]);
174 /* dsp_delay(); */
175#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]176 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
177
178 val = ((u32) p[0] << 16);
179 dsp_delay();
180
181 val |= p[1];
182 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]183#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]184 return val;
185}
186
187static inline u16 dsp_read_hpic_hi_hword(u32 addr)
188{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]189#if defined(CONFIG_NETTA_6412)
190 return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
191#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]192 return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]193#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]194}
195
196static inline u16 dsp_read_hpic_lo_hword(u32 addr)
197{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]198#if defined(CONFIG_NETTA_6412)
199 return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
200#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]201 return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]202#endif
203}
204
205static inline void dsp_wait_hrdy(void)
206{
207 int i;
208
209 i = 0;
210#if defined(CONFIG_NETTA_6412)
211 while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
212#else
213 while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
214#endif
215 dsp_delay();
216 i++;
217 }
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]218}
219
220static inline void dsp_write_hpic_word(u32 addr, u32 val)
221{
222 volatile u16 *p;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]223#if defined(CONFIG_NETTA_6412)
224 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
225 p[0] = bit_invert((u16)(val >> 16));
226 /* dsp_delay(); */
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]227
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]228 p[1] = bit_invert((u16)val);
229 /* dsp_delay(); */
230#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]231 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
232 p[0] = (u16)(val >> 16);
233 dsp_delay();
234
235 p[1] = (u16)val;
236 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]237#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]238}
239
240static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
241{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]242#if defined(CONFIG_NETTA_6412)
243 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
244#else
245
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]246 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]247#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]248}
249
250static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
251{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]252#if defined(CONFIG_NETTA_6412)
253 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
254#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]255 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]256#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]257}
258
259/********************************************************************/
260
261static inline void c62_write_word(u32 addr, u32 val)
262{
263 dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]264#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]265 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]266#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]267 dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]268#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]269 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]270#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]271
272 dsp_wait_hrdy();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]273#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]274 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]275#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]276 dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]277#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]278 dsp_delay();
279
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]280 /* dsp_wait_hrdy();
281 dsp_delay(); */
282#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]283 dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]284#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]285 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]286#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]287}
288
289static u32 c62_read_word(u32 addr)
290{
291 u32 val;
292
293 dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]294#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]295 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]296#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]297 dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]298#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]299 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]300#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]301
302 /* FETCH */
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]303#if defined(CONFIG_NETTA_6412)
304 dsp_write_hpic_word(DSP_HPIC, 0x00100010);
305#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]306 dsp_write_hpic(0x10);
307 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]308#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]309 dsp_wait_hrdy();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]310#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]311 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]312#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]313 val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]314#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]315 dsp_delay();
316
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]317 /* dsp_wait_hrdy();
318 dsp_delay(); */
319#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]320 val |= dsp_read_hpic_lo_hword(DSP_HPID2);
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]321#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]322 dsp_delay();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]323#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]324 return val;
325}
326
327static inline void c62_read(u32 addr, u32 *buffer, int numdata)
328{
329 int i;
330
331 if (numdata <= 0)
332 return;
333
334 for (i = 0; i < numdata; i++) {
335 *buffer++ = c62_read_word(addr);
336 addr += 4;
337 }
338}
339
340static inline u32 c62_checksum(u32 addr, int numdata)
341{
342 int i;
343 u32 chksum;
344
345 chksum = 0;
346 for (i = 0; i < numdata; i++) {
347 chksum += c62_read_word(addr);
348 addr += 4;
349 }
350
351 return chksum;
352}
353
354static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
355{
356 int i;
357
358 if (numdata <= 0)
359 return;
360
361 for (i = 0; i < numdata; i++) {
362 c62_write_word(addr, *buffer++);
363 addr += 4;
364 }
365}
366
367static inline int c62_write_word_validated(u32 addr, u32 val)
368{
369 c62_write_word(addr, val);
370 return c62_read_word(addr) == val ? 0 : -1;
371}
372
373static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
374{
375 int i, r;
376
377 if (numdata <= 0)
378 return 0;
379
380 for (i = 0; i < numdata; i++) {
381 r = c62_write_word_validated(addr, *buffer++);
382 if (r < 0)
383 return r;
384 addr += 4;
385 }
386 return 0;
387}
388
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]389#if defined(CONFIG_NETTA_6412)
390
391#define DRAM_REGS_BASE 0x1800000
392
393#define GBLCTL DRAM_REGS_BASE
394#define CECTL1 (DRAM_REGS_BASE + 0x4)
395#define CECTL0 (DRAM_REGS_BASE + 0x8)
396#define CECTL2 (DRAM_REGS_BASE + 0x10)
397#define CECTL3 (DRAM_REGS_BASE + 0x14)
398#define SDCTL (DRAM_REGS_BASE + 0x18)
399#define SDTIM (DRAM_REGS_BASE + 0x1C)
400#define SDEXT (DRAM_REGS_BASE + 0x20)
401#define SESEC1 (DRAM_REGS_BASE + 0x44)
402#define SESEC0 (DRAM_REGS_BASE + 0x48)
403#define SESEC2 (DRAM_REGS_BASE + 0x50)
404#define SESEC3 (DRAM_REGS_BASE + 0x54)
405
406#define MAR128 0x1848200
407#define MAR129 0x1848204
408
409void dsp_dram_initialize(void)
410{
411 c62_write_word(GBLCTL, 0x120E4);
412 c62_write_word(CECTL1, 0x18);
413 c62_write_word(CECTL0, 0xD0);
414 c62_write_word(CECTL2, 0x18);
415 c62_write_word(CECTL3, 0x18);
416 c62_write_word(SDCTL, 0x47115000);
417 c62_write_word(SDTIM, 1536);
418 c62_write_word(SDEXT, 0x534A9);
419#if 0
420 c62_write_word(SESEC1, 0);
421 c62_write_word(SESEC0, 0);
422 c62_write_word(SESEC2, 0);
423 c62_write_word(SESEC3, 0);
424#endif
425 c62_write_word(MAR128, 1);
426 c62_write_word(MAR129, 0);
427}
428
429#endif
430
431static inline void dsp_init_hpic(void)
432{
433 int i;
434 volatile u16 *p;
435#if defined(CONFIG_NETTA_6412)
436 dsp_go_fast();
437#else
438 dsp_go_slow();
439#endif
440 i = 0;
441#if defined(CONFIG_NETTA_6412)
442 while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
443#else
444 while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
445#endif
446 dsp_delay();
447 i++;
448 }
449
450 if (i == 1000)
451 printf("HRDY stuck\n");
452
453 dsp_delay();
454
455 /* write control register */
456 p = (volatile u16 *)DSP_BASE;
457 p[0] = 0x0000;
458 dsp_delay();
459 p[1] = 0x0000;
460 dsp_delay();
461
462#if !defined(CONFIG_NETTA_6412)
463 dsp_go_fast();
464#endif
465}
466
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]467/***********************************************************************************************************/
468
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]469#if !defined(CONFIG_NETTA_6412)
470
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]471static const u8 bootstrap_rbin[5084] = {
472 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
473 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
474 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
475 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
476 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
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788 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8,
789 0x00, 0x02, 0x17, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28,
790 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a,
791 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00,
792 0x01, 0x82, 0x22, 0x64, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68,
793 0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa,
794 0x02, 0x00, 0x02, 0x76, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
795 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58,
796 0x03, 0x00, 0x10, 0x2a, 0x02, 0x04, 0x03, 0xe3, 0x00, 0x00, 0x00, 0x00,
797 0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a, 0x00, 0x94, 0x03, 0xa2,
798 0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x00, 0x02, 0x98, 0x56, 0x15,
799 0x00, 0x90, 0x2a, 0x58, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59,
800 0x00, 0x00, 0x04, 0x12, 0x00, 0x90, 0x2a, 0x59, 0x02, 0x98, 0x56, 0x14,
801 0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9,
802 0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1,
803 0x20, 0x00, 0x00, 0x12, 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x94, 0x2a, 0x59,
804 0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
805 0xa3, 0x9c, 0x0f, 0xf9, 0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14,
806 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x2a, 0x59,
807 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x9c, 0x0f, 0xf9,
808 0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
809 0x00, 0x94, 0x2a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf9,
810 0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
811 0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1, 0xa3, 0x9c, 0x0f, 0xf8,
812 0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf8,
813 0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0xc6, 0x6b,
814 0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0e, 0x2a,
815 0x02, 0x00, 0xc6, 0x6a, 0x03, 0x90, 0x02, 0xf4, 0x00, 0x00, 0x10, 0x28,
816 0x00, 0x00, 0xc6, 0x68, 0x03, 0x80, 0x02, 0x74, 0x00, 0x0c, 0x03, 0x62,
817 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc0, 0x69,
819 0x02, 0x00, 0x10, 0x2a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x0c, 0x03, 0x62,
820 0x00, 0x00, 0x80, 0x00, 0x01, 0xbc, 0x54, 0xf6, 0x02, 0x04, 0x03, 0xe2,
821 0x02, 0x13, 0xcf, 0x5a, 0x00, 0x90, 0x03, 0xa2, 0x02, 0x18, 0x50, 0x2a,
822 0x02, 0x00, 0x00, 0x6a, 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x30, 0x2a,
823 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x17, 0xb4, 0x28,
824 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x3c, 0x2a,
825 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x04, 0x29,
826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x69, 0x02, 0x00, 0x10, 0x2a,
827 0x02, 0x00, 0x02, 0x76, 0x00, 0x14, 0x4e, 0x28, 0x00, 0x00, 0x00, 0x68,
828 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x52, 0x2a, 0x01, 0x80, 0x00, 0x6a,
829 0x00, 0x00, 0x40, 0x00, 0x00, 0x11, 0x94, 0x28, 0x00, 0x00, 0x00, 0x68,
830 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x5e, 0x2a, 0x01, 0x80, 0x00, 0x6a,
831 0x00, 0x00, 0x40, 0x00, 0x02, 0x11, 0x4c, 0x2a, 0x02, 0x00, 0x00, 0x6a,
832 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x6c, 0x2a, 0x01, 0x80, 0x00, 0x6a,
833 0x02, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x20, 0x00, 0x00, 0x11, 0x4c, 0x28,
834 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x7a, 0x2a,
835 0x01, 0x80, 0x00, 0x6a, 0x02, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x20, 0x00,
836 0x02, 0x04, 0x03, 0xe2, 0x00, 0x12, 0x00, 0x28, 0x02, 0x00, 0x9f, 0xfa,
837 0x00, 0x90, 0x03, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
839 0x01, 0xbc, 0x52, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0c, 0x03, 0x62,
840 0x00, 0x00, 0x80, 0x00, 0x07, 0xae, 0xfe, 0x2a, 0x07, 0x80, 0x00, 0x6a,
841 0x00, 0x10, 0x00, 0x28, 0x02, 0x80, 0x13, 0xa2, 0x0f, 0xff, 0xe3, 0x12,
842 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x30, 0x28,
846 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
847 0x00, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x20, 0x90,
848 0x01, 0x04, 0x2a, 0x58, 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x0a, 0x10,
849 0x00, 0x00, 0x80, 0x00, 0x02, 0x00, 0x00, 0xfa, 0x02, 0x00, 0xc0, 0x6a,
850 0x02, 0x90, 0x02, 0xe6, 0x03, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x40, 0x00,
851 0x02, 0x94, 0xcd, 0xfa, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x00, 0xf8,
852 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
853 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, 0x0f, 0xff, 0xfa, 0x90,
854 0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb,
855 0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a,
856 0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4,
857 0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8,
858 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66,
859 0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00,
860 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28,
861 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76,
862 0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea,
863 0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66,
864 0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00,
865 0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a,
866 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4,
867 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4,
868 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8,
869 0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a,
872 0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6,
873 0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b,
874 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a,
875 0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa,
876 0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68,
877 0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12,
878 0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
879 0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
880 0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
881 0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
882 0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
883 0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
884 0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
885 0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
886 0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
887 0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
888 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
889 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
890 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
891 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
892 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
893 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
894 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
896};
897
898static int load_bootstrap(void)
899{
900 const u8 *s = bootstrap_rbin;
901 u32 l = sizeof(bootstrap_rbin);
902 const u8 *data, *hdr, *h;
903 u32 chksum, chksum2;
904 int i, j, rangenr;
905 u32 start, length;
906
907 if (l < 12) {
908 printf("bootstrap image corrupted. (too short header)\n");
909 return -1;
910 }
911
912 chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7];
913 rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11];
914 s += 12; l -= 12;
915
916 hdr = s;
917 s += 8 * rangenr; l -= 8 * rangenr;
918 data = s;
919
920 /* validate bootstrap image */
921 h = hdr; s = data; chksum2 = 0;
922 for (i = 0; i < rangenr; i++) {
923 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
924 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
925 h += 8;
926
927 /* too short */
928 if (l < length) {
929 printf("bootstrap image corrupted. (too short data)\n");
930 return -1;
931 }
932 l -= length;
933
934 j = (int)length / 4;
935 while (j-- > 0) {
936 chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3];
937 s += 4;
938 }
939 }
940
941 /* checksum must match */
942 if (chksum != chksum2) {
943 printf("bootstrap image corrupted. (checksum error)\n");
944 return -1;
945 }
946
947 /* nothing must be left */
948 if (l != 0) {
949 printf("bootstrap image corrupted. (garbage at the end)\n");
950 return -1;
951 }
952
953 /* write the image */
954 h = hdr;
955 s = data;
956 for (i = 0; i < rangenr; i++) {
957 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
958 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
959 h += 8;
960 c62_write(start, (u32 *)s, length / 4);
961 s += length;
962 }
963
964 /* and now validate checksum */
965 h = hdr;
966 s = data;
967 chksum2 = 0;
968 for (i = 0; i < rangenr; i++) {
969 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
970 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
971 h += 8;
972 chksum2 += c62_checksum(start, length / 4);
973 s += length;
974 }
975
976 /* checksum must match */
977 if (chksum != chksum2) {
978 printf("bootstrap in DSP memory is corrupted\n");
979 return -1;
980 }
981
982 return 0;
983}
984
985struct host_init {
986 u32 master_mode;
987 struct {
988 u8 port_id;
989 u8 slot_id;
990 } ch_serial_map[32];
991 u32 clk_divider[2];
992 /* pll */
993 u32 initmode;
994 u32 pllm;
995 u32 div[4];
996 u32 oscdiv1;
997 u32 unused[10];
998};
999
1000const struct host_init hi_default = {
1001 .master_mode =
1002#if !defined(CONFIG_NETTA_ISDN)
1003 -1,
1004#else
1005 0,
1006#endif
1007
1008 .ch_serial_map = {
1009 [ 0] = { .port_id = 2, .slot_id = 16 },
1010 [ 1] = { .port_id = 2, .slot_id = 17 },
1011 [ 2] = { .port_id = 2, .slot_id = 18 },
1012 [ 3] = { .port_id = 2, .slot_id = 19 },
1013 [ 4] = { .port_id = 2, .slot_id = 20 },
1014 [ 5] = { .port_id = 2, .slot_id = 21 },
1015 [ 6] = { .port_id = 2, .slot_id = 22 },
1016 [ 7] = { .port_id = 2, .slot_id = 23 },
1017 [ 8] = { .port_id = 2, .slot_id = 24 },
1018 [ 9] = { .port_id = 2, .slot_id = 25 },
1019 [10] = { .port_id = 2, .slot_id = 26 },
1020 [11] = { .port_id = 2, .slot_id = 27 },
1021 [12] = { .port_id = 2, .slot_id = 28 },
1022 [13] = { .port_id = 2, .slot_id = 29 },
1023 [14] = { .port_id = 2, .slot_id = 30 },
1024 [15] = { .port_id = 2, .slot_id = 31 },
1025 },
1026
1027 /*
1028 dsp_clk(xin, pllm) = xin * pllm
1029 serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
1030 */
1031
1032 .clk_divider = {
1033 [0] = 47, /* must be 2048Hz */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]1034 [1] = 47,
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1035 },
1036
1037 .initmode = 1,
1038 .pllm =
1039#if !defined(CONFIG_NETTA_ISDN)
1040 8, /* for =~ 25MHz 8 */
1041#else
1042 4,
1043#endif
1044 .div = {
1045 [0] = 0x8000,
1046 [1] = 0x8000, /* for =~ 25MHz 0x8000 */
1047 [2] = 0x8001, /* for =~ 25MHz 0x8001 */
1048 [3] = 0x8001, /* for =~ 25MHz 0x8001 */
1049 },
1050
1051 .oscdiv1 = 0,
1052};
1053
1054static void hi_write(const struct host_init *hi)
1055{
1056 u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
1057 u32 *s;
1058 u32 chksum;
1059 int i;
1060
1061 memset(hi_buf, 0, sizeof(hi_buf));
1062
1063 s = hi_buf;
1064 s++;
1065 *s++ = hi->master_mode;
1066 for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
1067 *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
1068 ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
1069
1070 for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
1071 *s++ = hi->clk_divider[i];
1072
1073 *s++ = hi->initmode;
1074 *s++ = hi->pllm;
1075 for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
1076 *s++ = hi->div[i];
1077 *s++ = hi->oscdiv1;
1078
1079 chksum = 0;
1080 for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
1081 chksum += hi_buf[i];
1082 hi_buf[0] = -chksum;
1083
1084 c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
1085}
1086
1087static void run_bootstrap(void)
1088{
1089 dsp_go_slow();
1090
1091 hi_write(&hi_default);
1092
1093 /* signal interrupt */
1094 dsp_write_hpic(0x0002);
1095 dsp_delay();
1096
1097 dsp_go_fast();
1098}
1099
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1100#endif
1101
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1102/***********************************************************************************************************/
1103
1104int board_post_dsp(int flags)
1105{
1106 u32 ramS, ramE;
1107 u32 data, data2;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1108 int i, j, k;
1109#if !defined(CONFIG_NETTA_6412)
1110 int r;
1111#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1112 dsp_reset();
1113 dsp_init_hpic();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1114#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1115 dsp_go_slow();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1116#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1117 data = 0x11223344;
1118 dsp_write_hpic_word(DSP_HPIA, data);
1119 data2 = dsp_read_hpic_word(DSP_HPIA);
1120 if (data2 != 0x11223344) {
1121 printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
1122 goto err;
1123 }
1124
1125 data = 0xFFEEDDCC;
1126 dsp_write_hpic_word(DSP_HPIA, data);
1127 data2 = dsp_read_hpic_word(DSP_HPIA);
1128 if (data2 != 0xFFEEDDCC) {
1129 printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
1130 goto err;
1131 }
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1132#if defined(CONFIG_NETTA_6412)
1133 dsp_dram_initialize();
1134#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1135 r = load_bootstrap();
1136 if (r < 0) {
1137 printf("BOOTSTRAP: ** ERROR ** failed to load\n");
1138 goto err;
1139 }
1140
1141 run_bootstrap();
1142
1143 dsp_go_fast();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1144#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1145 printf(" ");
1146
1147 /* test RAMs */
1148 for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
1149
1150 ramS = ranges[k].start;
1151 ramE = ranges[k].start + ranges[k].size;
1152
1153 for (j = 0; j < 3; j++) {
1154
1155 printf("\b\b\b\bR%d.%d", k, j);
1156
1157 for (i = ramS; i < ramE; i += 4) {
1158
1159 data = 0;
1160 switch (j) {
1161 case 0: data = 0xAA55AA55; break;
1162 case 1: data = 0x55AA55AA; break;
1163 case 2: data = (u32)i; break;
1164 }
1165
1166 c62_write_word(i, data);
1167 data2 = c62_read_word(i);
1168 if (data != data2) {
1169 printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
1170 goto err;
1171 }
1172 }
1173 }
1174 }
1175
1176 printf("\b\b\b\b \b\b\b\bOK\n");
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1177#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1178 /* XXX assume that this works */
1179 load_bootstrap();
1180 run_bootstrap();
1181 dsp_go_fast();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1182#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1183 return 0;
1184
1185err:
1186 return -1;
1187}
1188
1189int board_dsp_reset(void)
1190{
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1191#if !defined(CONFIG_NETTA_6412)
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1192 int r;
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1193#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1194 dsp_reset();
1195 dsp_init_hpic();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1196#if defined(CONFIG_NETTA_6412)
1197 dsp_dram_initialize();
1198#else
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1199 dsp_go_slow();
1200 r = load_bootstrap();
1201 if (r < 0)
1202 return r;
1203
1204 run_bootstrap();
1205 dsp_go_fast();
wdenkc4e854f2004-06-07 23:46:25 +0000[diff] [blame]1206#endif
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1207 return 0;
1208}