| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010-2012 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| Tom Warren | df45095 | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 7 | #ifndef _TEGRA_COMMON_H_ |
| 8 | #define _TEGRA_COMMON_H_ |
| Alexey Brodkin | 267d8e2 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 9 | #include <linux/sizes.h> |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 10 | #include <linux/stringify.h> |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | */ |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 15 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 16 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
| 17 | |
| Thierry Reding | 2674871 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 18 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
| 19 | #ifndef CONFIG_ARM64 |
| Rob Herring | 741a0bd | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 20 | #define CONFIG_SYS_TIMER_RATE 1000000 |
| 21 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE |
| Thierry Reding | 2674871 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 22 | #endif |
| Rob Herring | 741a0bd | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 23 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 24 | /* Environment */ |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 25 | |
| 26 | /* |
| Tom Warren | df45095 | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 27 | * NS16550 Configuration |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 28 | */ |
| Thomas Chou | e3b9026 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 29 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 30 | |
| 31 | /* |
| Stephen Warren | 2c0ea60 | 2014-04-18 10:56:11 -0600 | [diff] [blame] | 32 | * Common HW configuration. |
| 33 | * If this varies between SoCs later, move to tegraNN-common.h |
| 34 | * Note: This is number of devices, not max device ID. |
| 35 | */ |
| 36 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
| 37 | |
| Peter Robinson | 637ac01 | 2020-04-02 00:28:54 +0100 | [diff] [blame] | 38 | #ifdef CONFIG_ARM64 |
| 39 | #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" |
| 40 | #else |
| 41 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" |
| 42 | #endif |
| 43 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 44 | /*----------------------------------------------------------------------- |
| 45 | * Physical Memory Map |
| 46 | */ |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 47 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
| 48 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
| 49 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 50 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 51 | |
| 52 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ |
| 53 | |
| Stephen Warren | f599a03 | 2017-12-19 18:30:37 -0700 | [diff] [blame] | 54 | #ifndef CONFIG_ARM64 |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 55 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 56 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 57 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 58 | /* Defines for SPL */ |
| Stephen Warren | ef2a115 | 2017-12-19 18:30:35 -0700 | [diff] [blame] | 59 | #endif |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 60 | |
| Tom Warren | 23d7fe9 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 61 | #endif /* _TEGRA_COMMON_H_ */ |