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git01.mediatek.com / filogic / uboot / 04c640c109945c929a71dd3daf04789ca2115461 / . / include / configs / aspeed-common.h
blob: 5c9005805e1f97cdb9e4fb49f11d42a7a695195d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]2/*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Ryan Chen <ryan_chen@aspeedtech.com>
5 *
6 * Copyright 2016 IBM Corporation
7 * (C) Copyright 2016 Google, Inc
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]8 */
9
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +0800[diff] [blame]10#ifndef _ASPEED_COMMON_CONFIG_H
11#define _ASPEED_COMMON_CONFIG_H
12
13#include <asm/arch/platform.h>
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]14
15/* Misc CPU related */
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]16
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +0800[diff] [blame]17#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]18
19#ifdef CONFIG_PRE_CON_BUF_SZ
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +0800[diff] [blame]20#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
21#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]22#else
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +0800[diff] [blame]23#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
24#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]25#endif
26
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]27/*
28 * NS16550 Configuration
29 */
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]30
maxims@google.com899b40f2017-01-18 13:44:57 -0800[diff] [blame]31#endif /* __AST_COMMON_CONFIG_H */