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git01.mediatek.com / filogic / uboot / 04a75f96905c94dfbe31c1a2d69210f8e839b30d / . / arch / arm / dts / k3-am625-verdin-wifi-dev-u-boot.dtsi
blob: 02f34c90c6d7741eccea74fce3656b13ea9ab566 [file] [log] [blame]
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2023 Toradex
4 */
5
6#include "k3-am625-verdin-wifi-dev-binman.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
15 chosen {
16 tick-timer = &main_timer0;
17 };
18
19 memory@80000000 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]20 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]21 };
22};
23
Nishanth Menon947dc7d2023-11-14 21:28:55 -0600[diff] [blame]24&main_timer0 {
25 clock-frequency = <25000000>;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]26};
27
Roger Quadros74f59242023-10-28 20:36:02 +0300[diff] [blame]28&main_bcdma {
29 reg = <0x00 0x485c0100 0x00 0x100>,
30 <0x00 0x4c000000 0x00 0x20000>,
31 <0x00 0x4a820000 0x00 0x20000>,
32 <0x00 0x4aa40000 0x00 0x20000>,
33 <0x00 0x4bc00000 0x00 0x100000>,
34 <0x00 0x48600000 0x00 0x8000>,
35 <0x00 0x484a4000 0x00 0x2000>,
36 <0x00 0x484c2000 0x00 0x2000>;
37 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
38 "ringrt" , "cfg", "tchan", "rchan";
Roger Quadros88a6b0a2023-11-14 22:28:56 +0200[diff] [blame]39 bootph-all;
Roger Quadros74f59242023-10-28 20:36:02 +0300[diff] [blame]40};
41
42&main_pktdma {
43 reg = <0x00 0x485c0000 0x00 0x100>,
44 <0x00 0x4a800000 0x00 0x20000>,
45 <0x00 0x4aa00000 0x00 0x20000>,
46 <0x00 0x4b800000 0x00 0x200000>,
47 <0x00 0x485e0000 0x00 0x10000>,
48 <0x00 0x484a0000 0x00 0x2000>,
49 <0x00 0x484c0000 0x00 0x2000>,
50 <0x00 0x48430000 0x00 0x1000>;
51 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
52 "cfg", "tchan", "rchan", "rflow";
53 bootph-all;
54};
55
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]56&cpsw3g {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]57 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]58};
59
60&cpsw3g_phy0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]61 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]62};
63
64&cpsw3g_phy1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]65 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]66};
67
68&cpsw_port1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]69 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]70};
71
72&cpsw_port2 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]73 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]74};
75
76/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
77&cpsw3g_mdio {
78 /delete-property/ assigned-clocks;
79 /delete-property/ assigned-clock-parents;
80 /delete-property/ assigned-clock-rates;
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]81 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]82};
83
84&dmsc {
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]85 k3_sysreset: sysreset-controller {
86 compatible = "ti,sci-sysreset";
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]87 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]88 };
89};
90
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]91&fss {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]92 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]93};
94
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]95&main_gpio0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]96 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]97};
98
99/* On-module I2C - PMIC_I2C */
100&main_i2c0 {
101 eeprom_module: eeprom@50 {
102 compatible = "i2c-eeprom";
103 pagesize = <16>;
104 reg = <0x50>;
105 };
106};
107
108/* Verdin I2C_1 */
109&main_i2c1 {
110 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
111 eeprom_display_adapter: eeprom@50 {
112 compatible = "i2c-eeprom";
113 reg = <0x50>;
114 pagesize = <16>;
115 };
116
117 /* EEPROM on carrier board */
118 eeprom_carrier_board: eeprom@57 {
119 compatible = "i2c-eeprom";
120 reg = <0x57>;
121 pagesize = <16>;
122 };
123};
124
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]125/* Verdin UART_3, used as the Linux console */
126&main_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]127 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]128};
129
130/* Verdin UART_1 */
131&main_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]132 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]133};
134
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]135&pinctrl_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]136 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]137};
138
139&pinctrl_i2c0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]140 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]141};
142
143&pinctrl_i2c1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]144 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]145};
146
147&pinctrl_sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]148 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]149};
150
151&pinctrl_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]152 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]153};
154
155&pinctrl_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]156 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]157};
158
159&pinctrl_wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]160 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]161};
162
163&sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]164 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]165};
166
167&sdhci2 {
168 status = "disabled";
169};
170
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]171&verdin_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]172 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]173};
174
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]175/* Verdin UART_2 */
176&wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200[diff] [blame]177 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200[diff] [blame]178};