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git01.mediatek.com / filogic / uboot / 04a75f96905c94dfbe31c1a2d69210f8e839b30d / . / arch / arm / dts / imx8mm-kontron-bl-common-u-boot.dtsi
blob: ae542fdcffad96a21b3d6d0a592809846bd9c7ff [file] [log] [blame]
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 usb0 = &usbotg1;
11 usb1 = &usbotg2;
12 };
13
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]18 };
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]19};
20
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]21&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
23 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]24};
25
26&i2c2 {
27 status = "okay";
Frieder Schrempf26e05b32022-08-24 15:59:20 +0200[diff] [blame]28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_i2c2>;
30};
31
32&iomuxc {
33 pinctrl_i2c2: i2c2grp {
34 fsl,pins = <
35 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
36 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
37 >;
38 };
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]39};
40
41&pinctrl_ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]43};
44
45&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]47};
48
49&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]51};
52
53&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
55 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]56};
57
58&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]60};
61
62&pinctrl_usdhc1_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]64};
65
66&pinctrl_usdhc1_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]68};
69
70&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]72};
73
74&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]76};
77
78&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]80};
81
82&ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]84};
85
86&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]88};
89
90&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]92};
93
94&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]96};
97
98&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]100};
101
102&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]104};
105
106&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
108 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]109};
110
111&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]113};
114
115&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]117};
118
119&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]121};
122
123&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]125};