blob: 4c76b4d0a803c69200e4eb402060b34e9cc76e0f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02005 */
6
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02007#include <common.h>
8#include <asm/processor.h>
9#include <asm/immap_85xx.h>
York Sunf0626592013-09-30 09:22:09 -070010#include <fsl_ddr_sdram.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020011#include <asm/processor.h>
12#include <asm/mmu.h>
13#include <spd_sdram.h>
14
15
16#if !defined(CONFIG_SPD_EEPROM)
17/*
18 * Autodetect onboard DDR SDRAM on 85xx platforms
19 *
20 * NOTE: Some of the hardcoded values are hardware dependant,
21 * so this should be extended for other future boards
22 * using this routine!
23 */
Becky Bruce5e35d8a2010-12-17 17:17:56 -060024phys_size_t fixed_sdram(void)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020025{
York Suna21803d2013-11-18 10:29:32 -080026 struct ccsr_ddr __iomem *ddr =
27 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020028
29 /*
30 * Disable memory controller.
31 */
32 ddr->cs0_config = 0;
33 ddr->sdram_cfg = 0;
34
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
36 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
40 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
41 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
42 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
43 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020044
45 asm ("sync;isync;msync");
46 udelay(1000);
47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048 ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020049 asm ("sync; isync; msync");
50 udelay(1000);
51
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052 if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020053 /*
54 * OK, size detected -> all done
55 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056 return CONFIG_SYS_SDRAM_SIZE<<20;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020057 }
58
59 return 0; /* nothing found ! */
60}
61#endif
62
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#if defined(CONFIG_SYS_DRAM_TEST)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020064int testdram (void)
65{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
67 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020068 uint *p;
69
70 printf ("SDRAM test phase 1:\n");
71 for (p = pstart; p < pend; p++)
72 *p = 0xaaaaaaaa;
73
74 for (p = pstart; p < pend; p++) {
75 if (*p != 0xaaaaaaaa) {
76 printf ("SDRAM test fails at: %08x\n", (uint) p);
77 return 1;
78 }
79 }
80
81 printf ("SDRAM test phase 2:\n");
82 for (p = pstart; p < pend; p++)
83 *p = 0x55555555;
84
85 for (p = pstart; p < pend; p++) {
86 if (*p != 0x55555555) {
87 printf ("SDRAM test fails at: %08x\n", (uint) p);
88 return 1;
89 }
90 }
91
92 printf ("SDRAM test passed.\n");
93 return 0;
94}
95#endif