liu hao | 1c4a2c4 | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2019 |
| 4 | * shuyiqi <shuyiqi@phytium.com.cn> |
| 5 | * liuhao <liuhao@phytium.com.cn> |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 9 | #include <command.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 11 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
liu hao | 1c4a2c4 | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 13 | #include <asm/armv8/mmu.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <asm/cache.h> |
liu hao | 1c4a2c4 | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 15 | #include <asm/system.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <linux/arm-smccc.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <scsi.h> |
| 20 | #include "cpu.h" |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | int dram_init(void) |
| 25 | { |
| 26 | gd->mem_clk = 0; |
| 27 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 28 | return 0; |
| 29 | } |
| 30 | |
| 31 | int dram_init_banksize(void) |
| 32 | { |
| 33 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 34 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 35 | |
| 36 | return 0; |
| 37 | } |
| 38 | |
| 39 | int board_init(void) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | void reset_cpu(ulong addr) |
| 45 | { |
| 46 | struct arm_smccc_res res; |
| 47 | |
| 48 | arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); |
| 49 | debug("reset cpu error, %lx\n", res.a0); |
| 50 | } |
| 51 | |
| 52 | static struct mm_region durian_mem_map[] = { |
| 53 | { |
| 54 | .virt = 0x0UL, |
| 55 | .phys = 0x0UL, |
| 56 | .size = 0x80000000UL, |
| 57 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 58 | PTE_BLOCK_NON_SHARE | |
| 59 | PTE_BLOCK_PXN | |
| 60 | PTE_BLOCK_UXN |
| 61 | }, |
| 62 | { |
| 63 | .virt = (u64)PHYS_SDRAM_1, |
| 64 | .phys = (u64)PHYS_SDRAM_1, |
| 65 | .size = (u64)PHYS_SDRAM_1_SIZE, |
| 66 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 67 | PTE_BLOCK_NS | |
| 68 | PTE_BLOCK_INNER_SHARE |
| 69 | }, |
| 70 | { |
| 71 | 0, |
| 72 | } |
| 73 | }; |
| 74 | |
| 75 | struct mm_region *mem_map = durian_mem_map; |
| 76 | |
| 77 | int print_cpuinfo(void) |
| 78 | { |
| 79 | printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk); |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | int __asm_flush_l3_dcache(void) |
| 84 | { |
| 85 | int i, pstate; |
| 86 | |
| 87 | for (i = 0; i < HNF_COUNT; i++) |
| 88 | writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); |
| 89 | for (i = 0; i < HNF_COUNT; i++) { |
| 90 | do { |
| 91 | pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); |
| 92 | } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
| 93 | } |
| 94 | |
| 95 | for (i = 0; i < HNF_COUNT; i++) |
| 96 | writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | int last_stage_init(void) |
| 102 | { |
| 103 | int ret; |
| 104 | |
| 105 | /* pci e */ |
| 106 | pci_init(); |
| 107 | /* scsi scan */ |
| 108 | ret = scsi_scan(true); |
| 109 | if (ret) { |
| 110 | printf("scsi scan failed\n"); |
| 111 | return CMD_RET_FAILURE; |
| 112 | } |
| 113 | return ret; |
| 114 | } |
| 115 | |