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git01.mediatek.com / filogic / uboot / 044f1a02935dda0f79c7121424fafab79f3d19c4 / . / arch / x86 / cpu / qemu / dsdt.asl
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Saket Sinhaaf8d55f2015-08-22 12:20:57 +0530[diff] [blame]1/*
2 * QEMU ACPI DSDT ASL definition
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Copyright (c) 2010 Isaku Yamahata
7 * yamahata at valinux co jp
8 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
9 */
10
11DefinitionBlock (
12 "dsdt.aml", /* Output Filename */
13 "DSDT", /* Signature */
14 0x01, /* DSDT Compliance Revision */
15 "UBOO", /* OEMID */
16 "UBOOT ", /* TABLE ID */
17 0x2 /* OEM Revision */
18 )
19{
20
21#include "acpi/dbug.asl"
22
23 Scope(\_SB) {
24 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
25 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
26 Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
27 PCIB, 8,
28 }
29 }
30
31
32/* PCI Bus definition */
33
34 Scope(\_SB) {
35 Device(PCI0) {
36 Name(_HID, EisaId("PNP0A08"))
37 Name(_CID, EisaId("PNP0A03"))
38 Name(_ADR, 0x00)
39 Name(_UID, 1)
40
41 /* _OSC: based on sample of ACPI3.0b spec */
42 Name(SUPP, 0) /* PCI _OSC Support Field value */
43 Name(CTRL, 0) /* PCI _OSC Control Field value */
44 Method(_OSC, 4) {
45 /* Create DWORD-addressable fields from Capabilities Buffer */
46 CreateDWordField(Arg3, 0, CDW1)
47
48 /* Check for proper UUID */
49 If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
50 {
51 /* Create DWORD-addressable fields from Capabilities Buffer */
52 CreateDWordField(Arg3, 4, CDW2)
53 CreateDWordField(Arg3, 8, CDW3)
54
55 /* Save Capabilities DWORD2 & 3 */
56 Store(CDW2, SUPP)
57 Store(CDW3, CTRL)
58
59 /*
60 * Always allow native PME, AER (no dependencies)
61 * Never allow SHPC (no SHPC controller in this system)
62 */
63 And(CTRL, 0x1d, CTRL)
64
65 If (LNotEqual(Arg1, One)) {
66 /* Unknown revision */
67 Or(CDW1, 0x08, CDW1)
68 }
69 If (LNotEqual(CDW3, CTRL)) {
70 /* Capabilities bits were masked */
71 Or(CDW1, 0x10, CDW1)
72 }
73 /* Update DWORD3 in the buffer */
74 Store(CTRL, CDW3)
75 } Else {
76 Or(CDW1, 4, CDW1) /* Unrecognized UUID */
77 }
78 Return (Arg3)
79 }
80 }
81 }
82
83#include "acpi/pci-crs.asl"
84#include "acpi/hpet.asl"
85
86
87/* VGA */
88
89 Scope(\_SB.PCI0) {
90 Device(VGA) {
91 Name(_ADR, 0x00010000)
92 Method(_S1D, 0, NotSerialized) {
93 Return (0x00)
94 }
95 Method(_S2D, 0, NotSerialized) {
96 Return (0x00)
97 }
98 Method(_S3D, 0, NotSerialized) {
99 Return (0x00)
100 }
101 }
102 }
103
104
105/* LPC ISA bridge */
106
107 Scope(\_SB.PCI0) {
108 /* PCI D31:f0 LPC ISA bridge */
109 Device(ISA) {
110 /* PCI D31:f0 */
111 Name(_ADR, 0x001f0000)
112
113 /* ICH9 PCI to ISA irq remapping */
114 OperationRegion(PIRQ, PCI_Config, 0x60, 0x0c)
115
116 OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
117 Field(LPCD, AnyAcc, NoLock, Preserve) {
118 COMA, 3,
119 , 1,
120 COMB, 3,
121
122 Offset(0x01),
123 LPTD, 2,
124 , 2,
125 FDCD, 2
126 }
127 OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
128 Field(LPCE, AnyAcc, NoLock, Preserve) {
129 CAEN, 1,
130 CBEN, 1,
131 LPEN, 1,
132 FDEN, 1
133 }
134 }
135 }
136
137#include "acpi/isa.asl"
138
139
140/* PCI IRQs */
141
142 /* Zero => PIC mode, One => APIC Mode */
143 Name(\PICF, Zero)
144 Method(\_PIC, 1, NotSerialized) {
145 Store(Arg0, \PICF)
146 }
147
148 Scope(\_SB) {
149 Scope(PCI0) {
150#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
151 Package() { nr##ffff, 0, lnk0, 0 }, \
152 Package() { nr##ffff, 1, lnk1, 0 }, \
153 Package() { nr##ffff, 2, lnk2, 0 }, \
154 Package() { nr##ffff, 3, lnk3, 0 }
155
156#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
157#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
158#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
159#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
160
161#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
162#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
163#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
164#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
165
166 Name(PRTP, Package() {
167 prt_slot_lnkE(0x0000),
168 prt_slot_lnkF(0x0001),
169 prt_slot_lnkG(0x0002),
170 prt_slot_lnkH(0x0003),
171 prt_slot_lnkE(0x0004),
172 prt_slot_lnkF(0x0005),
173 prt_slot_lnkG(0x0006),
174 prt_slot_lnkH(0x0007),
175 prt_slot_lnkE(0x0008),
176 prt_slot_lnkF(0x0009),
177 prt_slot_lnkG(0x000a),
178 prt_slot_lnkH(0x000b),
179 prt_slot_lnkE(0x000c),
180 prt_slot_lnkF(0x000d),
181 prt_slot_lnkG(0x000e),
182 prt_slot_lnkH(0x000f),
183 prt_slot_lnkE(0x0010),
184 prt_slot_lnkF(0x0011),
185 prt_slot_lnkG(0x0012),
186 prt_slot_lnkH(0x0013),
187 prt_slot_lnkE(0x0014),
188 prt_slot_lnkF(0x0015),
189 prt_slot_lnkG(0x0016),
190 prt_slot_lnkH(0x0017),
191 prt_slot_lnkE(0x0018),
192
193 /* INTA -> PIRQA for slot 25 - 31
194 see the default value of D<N>IR */
195 prt_slot_lnkA(0x0019),
196 prt_slot_lnkA(0x001a),
197 prt_slot_lnkA(0x001b),
198 prt_slot_lnkA(0x001c),
199 prt_slot_lnkA(0x001d),
200
201 /* PCIe->PCI bridge. use PIRQ[E-H] */
202 prt_slot_lnkE(0x001e),
203
204 prt_slot_lnkA(0x001f)
205 })
206
207#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
208 Package() { nr##ffff, 0, gsi0, 0 }, \
209 Package() { nr##ffff, 1, gsi1, 0 }, \
210 Package() { nr##ffff, 2, gsi2, 0 }, \
211 Package() { nr##ffff, 3, gsi3, 0 }
212
213#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
214#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
215#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
216#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
217
218#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
219#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
220#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
221#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
222
223 Name(PRTA, Package() {
224 prt_slot_gsiE(0x0000),
225 prt_slot_gsiF(0x0001),
226 prt_slot_gsiG(0x0002),
227 prt_slot_gsiH(0x0003),
228 prt_slot_gsiE(0x0004),
229 prt_slot_gsiF(0x0005),
230 prt_slot_gsiG(0x0006),
231 prt_slot_gsiH(0x0007),
232 prt_slot_gsiE(0x0008),
233 prt_slot_gsiF(0x0009),
234 prt_slot_gsiG(0x000a),
235 prt_slot_gsiH(0x000b),
236 prt_slot_gsiE(0x000c),
237 prt_slot_gsiF(0x000d),
238 prt_slot_gsiG(0x000e),
239 prt_slot_gsiH(0x000f),
240 prt_slot_gsiE(0x0010),
241 prt_slot_gsiF(0x0011),
242 prt_slot_gsiG(0x0012),
243 prt_slot_gsiH(0x0013),
244 prt_slot_gsiE(0x0014),
245 prt_slot_gsiF(0x0015),
246 prt_slot_gsiG(0x0016),
247 prt_slot_gsiH(0x0017),
248 prt_slot_gsiE(0x0018),
249
250 /*
251 * INTA -> PIRQA for slot 25 - 31, but 30
252 * see the default value of D<N>IR
253 */
254 prt_slot_gsiA(0x0019),
255 prt_slot_gsiA(0x001a),
256 prt_slot_gsiA(0x001b),
257 prt_slot_gsiA(0x001c),
258 prt_slot_gsiA(0x001d),
259
260 /* PCIe->PCI bridge. use PIRQ[E-H] */
261 prt_slot_gsiE(0x001e),
262
263 prt_slot_gsiA(0x001f)
264 })
265
266 Method(_PRT, 0, NotSerialized) {
267 /*
268 * PCI IRQ routing table,
269 * example from ACPI 2.0a
270 * specification, section 6.2.8.1
271 * Note: we provide the same info
272 * as the PCI routing table
273 * of the Bochs BIOS
274 */
275 If (LEqual(\PICF, Zero)) {
276 Return (PRTP)
277 } Else {
278 Return (PRTA)
279 }
280 }
281 }
282
283 Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
284 PRQA, 8,
285 PRQB, 8,
286 PRQC, 8,
287 PRQD, 8,
288
289 Offset(0x08),
290 PRQE, 8,
291 PRQF, 8,
292 PRQG, 8,
293 PRQH, 8
294 }
295
296 Method(IQST, 1, NotSerialized) {
297 /* _STA method - get status */
298 If (And(0x80, Arg0)) {
299 Return (0x09)
300 }
301 Return (0x0b)
302 }
303 Method(IQCR, 1, NotSerialized) {
304 /* _CRS method - get current settings */
305 Name(PRR0, ResourceTemplate() {
306 Interrupt(, Level, ActiveHigh, Shared) { 0 }
307 })
308 CreateDWordField(PRR0, 0x05, PRRI)
309 Store(And(Arg0, 0x0f), PRRI)
310 Return (PRR0)
311 }
312
313#define define_link(link, uid, reg) \
314 Device(link) { \
315 Name(_HID, EISAID("PNP0C0F")) \
316 Name(_UID, uid) \
317 Name(_PRS, ResourceTemplate() { \
318 Interrupt(, Level, ActiveHigh, Shared) { \
319 5, 10, 11 \
320 } \
321 }) \
322 Method(_STA, 0, NotSerialized) { \
323 Return (IQST(reg)) \
324 } \
325 Method(_DIS, 0, NotSerialized) { \
326 Or(reg, 0x80, reg) \
327 } \
328 Method(_CRS, 0, NotSerialized) { \
329 Return (IQCR(reg)) \
330 } \
331 Method(_SRS, 1, NotSerialized) { \
332 CreateDWordField(Arg0, 0x05, PRRI) \
333 Store(PRRI, reg) \
334 } \
335 }
336
337 define_link(LNKA, 0, PRQA)
338 define_link(LNKB, 1, PRQB)
339 define_link(LNKC, 2, PRQC)
340 define_link(LNKD, 3, PRQD)
341 define_link(LNKE, 4, PRQE)
342 define_link(LNKF, 5, PRQF)
343 define_link(LNKG, 6, PRQG)
344 define_link(LNKH, 7, PRQH)
345
346#define define_gsi_link(link, uid, gsi) \
347 Device(link) { \
348 Name(_HID, EISAID("PNP0C0F")) \
349 Name(_UID, uid) \
350 Name(_PRS, ResourceTemplate() { \
351 Interrupt(, Level, ActiveHigh, Shared) { \
352 gsi \
353 } \
354 }) \
355 Name(_CRS, ResourceTemplate() { \
356 Interrupt(, Level, ActiveHigh, Shared) { \
357 gsi \
358 } \
359 }) \
360 Method(_SRS, 1, NotSerialized) { \
361 } \
362 }
363
364 define_gsi_link(GSIA, 0, 0x10)
365 define_gsi_link(GSIB, 0, 0x11)
366 define_gsi_link(GSIC, 0, 0x12)
367 define_gsi_link(GSID, 0, 0x13)
368 define_gsi_link(GSIE, 0, 0x14)
369 define_gsi_link(GSIF, 0, 0x15)
370 define_gsi_link(GSIG, 0, 0x16)
371 define_gsi_link(GSIH, 0, 0x17)
372 }
373
374/* General purpose events */
375
376 Scope(\_GPE) {
377 Name(_HID, "ACPI0006")
378
379 Method(_L00) {
380 }
381 Method(_L01) {
382 }
383 Method(_L02) {
384 }
385 Method(_L03) {
386 }
387 Method(_L04) {
388 }
389 Method(_L05) {
390 }
391 Method(_L06) {
392 }
393 Method(_L07) {
394 }
395 Method(_L08) {
396 }
397 Method(_L09) {
398 }
399 Method(_L0A) {
400 }
401 Method(_L0B) {
402 }
403 Method(_L0C) {
404 }
405 Method(_L0D) {
406 }
407 Method(_L0E) {
408 }
409 Method(_L0F) {
410 }
411 }
412}