| Andreas Dannenberg | ebc6879 | 2018-08-27 15:57:46 +0530 | [diff] [blame] | 1 | Texas Instruments TI SCI System Reset Controller |
| 2 | ================================================ |
| 3 | |
| 4 | Some TI SoCs contain a system controller (like the SYSFW, etc...) that is |
| 5 | responsible for controlling the state of the IPs that are present. |
| 6 | Communication between the host processor running an OS and the system |
| 7 | controller happens through a protocol known as TI SCI [1]. |
| 8 | |
| 9 | [1] http://processors.wiki.ti.com/index.php/TISCI |
| 10 | |
| 11 | System Reset Controller Node |
| 12 | ============================ |
| 13 | The sysreset controller node represents the reset for the overall SoC |
| 14 | which is managed by the SYSFW. Because this relies on the TI SCI protocol |
| 15 | to communicate with the SYSFW it must be a child of the sysfw node. |
| 16 | |
| 17 | Required Properties: |
| 18 | -------------------- |
| 19 | - compatible: Must be "ti,sci-sysreset" |
| 20 | |
| 21 | Example (AM65x): |
| 22 | ---------------- |
| 23 | sysfw: sysfw { |
| 24 | compatible = "ti,am654-system-controller"; |
| 25 | ... |
| 26 | k3_sysreset: sysreset-controller { |
| 27 | compatible = "ti,sci-sysreset"; |
| 28 | }; |
| 29 | }; |