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git01.mediatek.com / filogic / uboot / 044725febbdf584bfd26ef03d12343a93ab83128 / . / arch / arm / dts / stih407-family.dtsi
blob: 6c6de58029cfed66aca9ddc482a0c6adaca8eb72 [file] [log] [blame]
Patrice Chotardcdf6b572017-02-21 13:37:11 +0100[diff] [blame]1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-pinctrl.dtsi"
10#include <dt-bindings/mfd/st-lpc.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/reset/stih407-resets.h>
13#include <dt-bindings/interrupt-controller/irq-st.h>
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 dmu_reserved: rproc@44000000 {
24 compatible = "shared-dma-pool";
25 reg = <0x44000000 0x01000000>;
26 no-map;
27 };
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a9";
36 reg = <0>;
37
38 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
39 cpu-release-addr = <0x94100A4>;
40
41 /* kHz uV */
42 operating-points = <1500000 0
43 1200000 0
44 800000 0
45 500000 0>;
46
47 clocks = <&clk_m_a9>;
48 clock-names = "cpu";
49 clock-latency = <100000>;
50 st,syscfg = <&syscfg_core 0x8e0>;
51 };
52 cpu@1 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <1>;
56
57 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
58 cpu-release-addr = <0x94100A4>;
59
60 /* kHz uV */
61 operating-points = <1500000 0
62 1200000 0
63 800000 0
64 500000 0>;
65 };
66 };
67
68 intc: interrupt-controller@08761000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 interrupt-controller;
72 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
73 };
74
75 scu@08760000 {
76 compatible = "arm,cortex-a9-scu";
77 reg = <0x08760000 0x1000>;
78 };
79
80 timer@08760200 {
81 interrupt-parent = <&intc>;
82 compatible = "arm,cortex-a9-global-timer";
83 reg = <0x08760200 0x100>;
84 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&arm_periph_clk>;
86 };
87
88 l2: cache-controller {
89 compatible = "arm,pl310-cache";
90 reg = <0x08762000 0x1000>;
91 arm,data-latency = <3 3 3>;
92 arm,tag-latency = <2 2 2>;
93 cache-unified;
94 cache-level = <2>;
95 };
96
97 arm-pmu {
98 interrupt-parent = <&intc>;
99 compatible = "arm,cortex-a9-pmu";
100 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
101 };
102
103 pwm_regulator: pwm-regulator {
104 compatible = "pwm-regulator";
105 pwms = <&pwm1 3 8448>;
106 regulator-name = "CPU_1V0_AVS";
107 regulator-min-microvolt = <784000>;
108 regulator-max-microvolt = <1299000>;
109 regulator-always-on;
110 max-duty-cycle = <255>;
111 status = "okay";
112 };
113
114 soc {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 interrupt-parent = <&intc>;
118 ranges;
119 compatible = "simple-bus";
120
121 restart {
122 compatible = "st,stih407-restart";
123 st,syscfg = <&syscfg_sbc_reg>;
124 status = "okay";
125 };
126
127 powerdown: powerdown-controller {
128 compatible = "st,stih407-powerdown";
129 #reset-cells = <1>;
130 };
131
132 softreset: softreset-controller {
133 compatible = "st,stih407-softreset";
134 #reset-cells = <1>;
135 };
136
137 picophyreset: picophyreset-controller {
138 compatible = "st,stih407-picophyreset";
139 #reset-cells = <1>;
140 };
141
142 syscfg_sbc: sbc-syscfg@9620000 {
143 compatible = "st,stih407-sbc-syscfg", "syscon";
144 reg = <0x9620000 0x1000>;
145 };
146
147 syscfg_front: front-syscfg@9280000 {
148 compatible = "st,stih407-front-syscfg", "syscon";
149 reg = <0x9280000 0x1000>;
150 };
151
152 syscfg_rear: rear-syscfg@9290000 {
153 compatible = "st,stih407-rear-syscfg", "syscon";
154 reg = <0x9290000 0x1000>;
155 };
156
157 syscfg_flash: flash-syscfg@92a0000 {
158 compatible = "st,stih407-flash-syscfg", "syscon";
159 reg = <0x92a0000 0x1000>;
160 };
161
162 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
163 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
164 reg = <0x9600000 0x1000>;
165 };
166
167 syscfg_core: core-syscfg@92b0000 {
168 compatible = "st,stih407-core-syscfg", "syscon";
169 reg = <0x92b0000 0x1000>;
170 };
171
172 syscfg_lpm: lpm-syscfg@94b5100 {
173 compatible = "st,stih407-lpm-syscfg", "syscon";
174 reg = <0x94b5100 0x1000>;
175 };
176
177 irq-syscfg {
178 compatible = "st,stih407-irq-syscfg";
179 st,syscfg = <&syscfg_core>;
180 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
181 <ST_IRQ_SYSCFG_PMU_1>;
182 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
183 <ST_IRQ_SYSCFG_DISABLED>;
184 };
185
186 /* Display */
187 vtg_main: sti-vtg-main@8d02800 {
188 compatible = "st,vtg";
189 reg = <0x8d02800 0x200>;
190 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
191 };
192
193 vtg_aux: sti-vtg-aux@8d00200 {
194 compatible = "st,vtg";
195 reg = <0x8d00200 0x100>;
196 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
197 };
198
199 serial@9830000 {
200 compatible = "st,asc";
201 reg = <0x9830000 0x2c>;
202 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_serial0>;
205 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
206
207 status = "disabled";
208 };
209
210 serial@9831000 {
211 compatible = "st,asc";
212 reg = <0x9831000 0x2c>;
213 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_serial1>;
216 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
217
218 status = "disabled";
219 };
220
221 serial@9832000 {
222 compatible = "st,asc";
223 reg = <0x9832000 0x2c>;
224 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_serial2>;
227 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228
229 status = "disabled";
230 };
231
232 /* SBC_ASC0 - UART10 */
233 sbc_serial0: serial@9530000 {
234 compatible = "st,asc";
235 reg = <0x9530000 0x2c>;
236 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_sbc_serial0>;
239 clocks = <&clk_sysin>;
240
241 status = "disabled";
242 };
243
244 serial@9531000 {
245 compatible = "st,asc";
246 reg = <0x9531000 0x2c>;
247 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_sbc_serial1>;
250 clocks = <&clk_sysin>;
251
252 status = "disabled";
253 };
254
255 i2c@9840000 {
256 compatible = "st,comms-ssc4-i2c";
257 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0x9840000 0x110>;
259 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
260 clock-names = "ssc";
261 clock-frequency = <400000>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_i2c0_default>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266
267 status = "disabled";
268 };
269
270 i2c@9841000 {
271 compatible = "st,comms-ssc4-i2c";
272 reg = <0x9841000 0x110>;
273 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
275 clock-names = "ssc";
276 clock-frequency = <400000>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_i2c1_default>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281
282 status = "disabled";
283 };
284
285 i2c@9842000 {
286 compatible = "st,comms-ssc4-i2c";
287 reg = <0x9842000 0x110>;
288 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
290 clock-names = "ssc";
291 clock-frequency = <400000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c2_default>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 status = "disabled";
298 };
299
300 i2c@9843000 {
301 compatible = "st,comms-ssc4-i2c";
302 reg = <0x9843000 0x110>;
303 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
305 clock-names = "ssc";
306 clock-frequency = <400000>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c3_default>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311
312 status = "disabled";
313 };
314
315 i2c@9844000 {
316 compatible = "st,comms-ssc4-i2c";
317 reg = <0x9844000 0x110>;
318 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
320 clock-names = "ssc";
321 clock-frequency = <400000>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c4_default>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326
327 status = "disabled";
328 };
329
330 i2c@9845000 {
331 compatible = "st,comms-ssc4-i2c";
332 reg = <0x9845000 0x110>;
333 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
335 clock-names = "ssc";
336 clock-frequency = <400000>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_i2c5_default>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 status = "disabled";
343 };
344
345
346 /* SSCs on SBC */
347 i2c@9540000 {
348 compatible = "st,comms-ssc4-i2c";
349 reg = <0x9540000 0x110>;
350 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clk_sysin>;
352 clock-names = "ssc";
353 clock-frequency = <400000>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_i2c10_default>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 status = "disabled";
360 };
361
362 i2c@9541000 {
363 compatible = "st,comms-ssc4-i2c";
364 reg = <0x9541000 0x110>;
365 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clk_sysin>;
367 clock-names = "ssc";
368 clock-frequency = <400000>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_i2c11_default>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373
374 status = "disabled";
375 };
376
377 usb2_picophy0: phy1 {
378 compatible = "st,stih407-usb2-phy";
379 #phy-cells = <0>;
380 st,syscfg = <&syscfg_core 0x100 0xf4>;
381 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
382 <&picophyreset STIH407_PICOPHY2_RESET>;
383 reset-names = "global", "port";
384 };
385
386 miphy28lp_phy: miphy28lp@9b22000 {
387 compatible = "st,miphy28lp-phy";
388 st,syscfg = <&syscfg_core>;
389 #address-cells = <1>;
390 #size-cells = <1>;
391 ranges;
392
393 phy_port0: port@9b22000 {
394 reg = <0x9b22000 0xff>,
395 <0x9b09000 0xff>,
396 <0x9b04000 0xff>;
397 reg-names = "sata-up",
398 "pcie-up",
399 "pipew";
400
401 st,syscfg = <0x114 0x818 0xe0 0xec>;
402 #phy-cells = <1>;
403
404 reset-names = "miphy-sw-rst";
405 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
406 };
407
408 phy_port1: port@9b2a000 {
409 reg = <0x9b2a000 0xff>,
410 <0x9b19000 0xff>,
411 <0x9b14000 0xff>;
412 reg-names = "sata-up",
413 "pcie-up",
414 "pipew";
415
416 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
417
418 #phy-cells = <1>;
419
420 reset-names = "miphy-sw-rst";
421 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
422 };
423
424 phy_port2: port@8f95000 {
425 reg = <0x8f95000 0xff>,
426 <0x8f90000 0xff>;
427 reg-names = "pipew",
428 "usb3-up";
429
430 st,syscfg = <0x11c 0x820>;
431
432 #phy-cells = <1>;
433
434 reset-names = "miphy-sw-rst";
435 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
436 };
437 };
438
439 spi@9840000 {
440 compatible = "st,comms-ssc4-spi";
441 reg = <0x9840000 0x110>;
442 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
444 clock-names = "ssc";
445 pinctrl-0 = <&pinctrl_spi0_default>;
446 pinctrl-names = "default";
447 #address-cells = <1>;
448 #size-cells = <0>;
449
450 status = "disabled";
451 };
452
453 spi@9841000 {
454 compatible = "st,comms-ssc4-spi";
455 reg = <0x9841000 0x110>;
456 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
458 clock-names = "ssc";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_spi1_default>;
461
462 status = "disabled";
463 };
464
465 spi@9842000 {
466 compatible = "st,comms-ssc4-spi";
467 reg = <0x9842000 0x110>;
468 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
470 clock-names = "ssc";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_spi2_default>;
473
474 status = "disabled";
475 };
476
477 spi@9843000 {
478 compatible = "st,comms-ssc4-spi";
479 reg = <0x9843000 0x110>;
480 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
482 clock-names = "ssc";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_spi3_default>;
485
486 status = "disabled";
487 };
488
489 spi@9844000 {
490 compatible = "st,comms-ssc4-spi";
491 reg = <0x9844000 0x110>;
492 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
494 clock-names = "ssc";
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_spi4_default>;
497
498 status = "disabled";
499 };
500
501 /* SBC SSC */
502 spi@9540000 {
503 compatible = "st,comms-ssc4-spi";
504 reg = <0x9540000 0x110>;
505 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk_sysin>;
507 clock-names = "ssc";
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_spi10_default>;
510
511 status = "disabled";
512 };
513
514 spi@9541000 {
515 compatible = "st,comms-ssc4-spi";
516 reg = <0x9541000 0x110>;
517 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk_sysin>;
519 clock-names = "ssc";
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_spi11_default>;
522
523 status = "disabled";
524 };
525
526 spi@9542000 {
527 compatible = "st,comms-ssc4-spi";
528 reg = <0x9542000 0x110>;
529 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clk_sysin>;
531 clock-names = "ssc";
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_spi12_default>;
534
535 status = "disabled";
536 };
537
538 mmc0: sdhci@09060000 {
539 compatible = "st,sdhci-stih407", "st,sdhci";
540 status = "disabled";
541 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
542 reg-names = "mmc", "top-mmc-delay";
543 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
544 interrupt-names = "mmcirq";
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_mmc0>;
547 clock-names = "mmc", "icn";
548 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
549 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
550 bus-width = <8>;
551 };
552
553 mmc1: sdhci@09080000 {
554 compatible = "st,sdhci-stih407", "st,sdhci";
555 status = "disabled";
556 reg = <0x09080000 0x7ff>;
557 reg-names = "mmc";
558 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
559 interrupt-names = "mmcirq";
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_sd1>;
562 clock-names = "mmc", "icn";
563 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
564 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
565 resets = <&softreset STIH407_MMC1_SOFTRESET>;
Patrice Chotard61bafb32017-09-05 11:04:19 +0200[diff] [blame]566 reset-names = "softreset";
Patrice Chotardcdf6b572017-02-21 13:37:11 +0100[diff] [blame]567 bus-width = <4>;
568 };
569
570 /* Watchdog and Real-Time Clock */
571 lpc@8787000 {
572 compatible = "st,stih407-lpc";
573 reg = <0x8787000 0x1000>;
574 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
575 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
576 timeout-sec = <120>;
577 st,syscfg = <&syscfg_core>;
578 st,lpc-mode = <ST_LPC_MODE_WDT>;
579 };
580
581 lpc@8788000 {
582 compatible = "st,stih407-lpc";
583 reg = <0x8788000 0x1000>;
584 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
585 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
586 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
587 };
588
589 sata0: sata@9b20000 {
590 compatible = "st,ahci";
591 reg = <0x9b20000 0x1000>;
592
593 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
594 interrupt-names = "hostc";
595
596 phys = <&phy_port0 PHY_TYPE_SATA>;
597 phy-names = "ahci_phy";
598
599 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
600 <&softreset STIH407_SATA0_SOFTRESET>,
601 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
602 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
603
604 clock-names = "ahci_clk";
605 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
606
607 ports-implemented = <0x1>;
608
609 status = "disabled";
610 };
611
612 sata1: sata@9b28000 {
613 compatible = "st,ahci";
614 reg = <0x9b28000 0x1000>;
615
616 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
617 interrupt-names = "hostc";
618
619 phys = <&phy_port1 PHY_TYPE_SATA>;
620 phy-names = "ahci_phy";
621
622 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
623 <&softreset STIH407_SATA1_SOFTRESET>,
624 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
625 reset-names = "pwr-dwn",
626 "sw-rst",
627 "pwr-rst";
628
629 clock-names = "ahci_clk";
630 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
631
632 ports-implemented = <0x1>;
633
634 status = "disabled";
635 };
636
637
638 st_dwc3: dwc3@8f94000 {
639 compatible = "st,stih407-dwc3";
640 reg = <0x08f94000 0x1000>, <0x110 0x4>;
641 reg-names = "reg-glue", "syscfg-reg";
642 st,syscfg = <&syscfg_core>;
643 resets = <&powerdown STIH407_USB3_POWERDOWN>,
644 <&softreset STIH407_MIPHY2_SOFTRESET>;
645 reset-names = "powerdown", "softreset";
646 #address-cells = <1>;
647 #size-cells = <1>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_usb3>;
650 ranges;
651
652 status = "disabled";
653
654 dwc3: dwc3@9900000 {
655 compatible = "snps,dwc3";
656 reg = <0x09900000 0x100000>;
657 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
Patrice Chotard3f09a662017-09-05 11:04:25 +0200[diff] [blame]658 dr_mode = "peripheral";
Patrice Chotardcdf6b572017-02-21 13:37:11 +0100[diff] [blame]659 phy-names = "usb2-phy", "usb3-phy";
660 phys = <&usb2_picophy0>,
661 <&phy_port2 PHY_TYPE_USB3>;
662 };
663 };
664
665 /* COMMS PWM Module */
666 pwm0: pwm@9810000 {
667 compatible = "st,sti-pwm";
668 #pwm-cells = <2>;
669 reg = <0x9810000 0x68>;
670 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
673 clock-names = "pwm";
674 clocks = <&clk_sysin>;
675 st,pwm-num-chan = <1>;
676
677 status = "disabled";
678 };
679
680 /* SBC PWM Module */
681 pwm1: pwm@9510000 {
682 compatible = "st,sti-pwm";
683 #pwm-cells = <2>;
684 reg = <0x9510000 0x68>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&pinctrl_pwm1_chan0_default
687 &pinctrl_pwm1_chan1_default
688 &pinctrl_pwm1_chan2_default
689 &pinctrl_pwm1_chan3_default>;
690 clock-names = "pwm";
691 clocks = <&clk_sysin>;
692 st,pwm-num-chan = <4>;
693
694 status = "disabled";
695 };
696
697 rng10: rng@08a89000 {
698 compatible = "st,rng";
699 reg = <0x08a89000 0x1000>;
700 clocks = <&clk_sysin>;
701 status = "okay";
702 };
703
704 rng11: rng@08a8a000 {
705 compatible = "st,rng";
706 reg = <0x08a8a000 0x1000>;
707 clocks = <&clk_sysin>;
708 status = "okay";
709 };
710
711 ethernet0: dwmac@9630000 {
712 device_type = "network";
713 status = "disabled";
714 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
715 reg = <0x9630000 0x8000>, <0x80 0x4>;
716 reg-names = "stmmaceth", "sti-ethconf";
717
718 st,syscon = <&syscfg_sbc_reg 0x80>;
719 st,gmac_en;
720 resets = <&softreset STIH407_ETH1_SOFTRESET>;
721 reset-names = "stmmaceth";
722
723 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
724 <GIC_SPI 99 IRQ_TYPE_NONE>;
725 interrupt-names = "macirq", "eth_wake_irq";
726
727 /* DMA Bus Mode */
728 snps,pbl = <8>;
729
730 pinctrl-names = "default";
731 pinctrl-0 = <&pinctrl_rgmii1>;
732
733 clock-names = "stmmaceth", "sti-ethclk";
734 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
735 <&clk_s_c0_flexgen CLK_ETH_PHY>;
736 };
737
738 cec: sti-cec@094a087c {
739 compatible = "st,stih-cec";
740 reg = <0x94a087c 0x64>;
741 clocks = <&clk_sysin>;
742 clock-names = "cec-clk";
743 interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
744 interrupt-names = "cec-irq";
745 pinctrl-names = "default";
746 pinctrl-0 = <&pinctrl_cec0_default>;
747 resets = <&softreset STIH407_LPM_SOFTRESET>;
748 };
749
750 rng10: rng@08a89000 {
751 compatible = "st,rng";
752 reg = <0x08a89000 0x1000>;
753 clocks = <&clk_sysin>;
754 status = "okay";
755 };
756
757 rng11: rng@08a8a000 {
758 compatible = "st,rng";
759 reg = <0x08a8a000 0x1000>;
760 clocks = <&clk_sysin>;
761 status = "okay";
762 };
763
764 mailbox0: mailbox@8f00000 {
765 compatible = "st,stih407-mailbox";
766 reg = <0x8f00000 0x1000>;
767 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
768 #mbox-cells = <2>;
769 mbox-name = "a9";
770 status = "okay";
771 };
772
773 mailbox1: mailbox@8f01000 {
774 compatible = "st,stih407-mailbox";
775 reg = <0x8f01000 0x1000>;
776 #mbox-cells = <2>;
777 mbox-name = "st231_gp_1";
778 status = "okay";
779 };
780
781 mailbox2: mailbox@8f02000 {
782 compatible = "st,stih407-mailbox";
783 reg = <0x8f02000 0x1000>;
784 #mbox-cells = <2>;
785 mbox-name = "st231_gp_0";
786 status = "okay";
787 };
788
789 mailbox3: mailbox@8f03000 {
790 compatible = "st,stih407-mailbox";
791 reg = <0x8f03000 0x1000>;
792 #mbox-cells = <2>;
793 mbox-name = "st231_audio_video";
794 status = "okay";
795 };
796
797 st231_delta: st231-delta@44000000 {
798 compatible = "st,st231-rproc";
799 memory-region = <&dmu_reserved>;
800 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
801 reset-names = "sw_reset";
802 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
803 clock-frequency = <600000000>;
804 st,syscfg = <&syscfg_core 0x224>;
805 #mbox-cells = <1>;
806 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
807 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
808 };
809
810 /* fdma audio */
811 fdma0: dma-controller@8e20000 {
812 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
813 reg = <0x8e20000 0x8000>,
814 <0x8e30000 0x3000>,
815 <0x8e37000 0x1000>,
816 <0x8e38000 0x8000>;
817 reg-names = "slimcore", "dmem", "peripherals", "imem";
818 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
819 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
820 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
821 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
822 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
823 dma-channels = <16>;
824 #dma-cells = <3>;
825 };
826
827 /* fdma app */
828 fdma1: dma-controller@8e40000 {
829 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
830 reg = <0x8e40000 0x8000>,
831 <0x8e50000 0x3000>,
832 <0x8e57000 0x1000>,
833 <0x8e58000 0x8000>;
834 reg-names = "slimcore", "dmem", "peripherals", "imem";
835 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
836 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
837 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
838 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
839
840 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
841 dma-channels = <16>;
842 #dma-cells = <3>;
843 };
844
845 /* fdma free running */
846 fdma2: dma-controller@8e60000 {
847 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
848 reg = <0x8e60000 0x8000>,
849 <0x8e70000 0x3000>,
850 <0x8e77000 0x1000>,
851 <0x8e78000 0x8000>;
852 reg-names = "slimcore", "dmem", "peripherals", "imem";
853 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
854 dma-channels = <16>;
855 #dma-cells = <3>;
856 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
857 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
858 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
859 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
860 };
861
862 sti_sasg_codec: sti-sasg-codec {
863 compatible = "st,stih407-sas-codec";
864 #sound-dai-cells = <1>;
865 status = "disabled";
866 st,syscfg = <&syscfg_core>;
867 };
868
869 sti_uni_player0: sti-uni-player@8d80000 {
870 compatible = "st,stih407-uni-player-hdmi";
871 #sound-dai-cells = <0>;
872 st,syscfg = <&syscfg_core>;
873 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
874 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
875 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
876 assigned-clock-rates = <50000000>;
877 reg = <0x8d80000 0x158>;
878 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
879 dmas = <&fdma0 2 0 1>;
880 dma-names = "tx";
881
882 status = "disabled";
883 };
884
885 sti_uni_player1: sti-uni-player@8d81000 {
886 compatible = "st,stih407-uni-player-pcm-out";
887 #sound-dai-cells = <0>;
888 st,syscfg = <&syscfg_core>;
889 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
890 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
891 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
892 assigned-clock-rates = <50000000>;
893 reg = <0x8d81000 0x158>;
894 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
895 dmas = <&fdma0 3 0 1>;
896 dma-names = "tx";
897
898 status = "disabled";
899 };
900
901 sti_uni_player2: sti-uni-player@8d82000 {
902 compatible = "st,stih407-uni-player-dac";
903 #sound-dai-cells = <0>;
904 st,syscfg = <&syscfg_core>;
905 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
906 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
907 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
908 assigned-clock-rates = <50000000>;
909 reg = <0x8d82000 0x158>;
910 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
911 dmas = <&fdma0 4 0 1>;
912 dma-names = "tx";
913
914 status = "disabled";
915 };
916
917 sti_uni_player3: sti-uni-player@8d85000 {
918 compatible = "st,stih407-uni-player-spdif";
919 #sound-dai-cells = <0>;
920 st,syscfg = <&syscfg_core>;
921 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
922 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
923 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
924 assigned-clock-rates = <50000000>;
925 reg = <0x8d85000 0x158>;
926 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
927 dmas = <&fdma0 7 0 1>;
928 dma-names = "tx";
929
930 status = "disabled";
931 };
932
933 sti_uni_reader0: sti-uni-reader@8d83000 {
934 compatible = "st,stih407-uni-reader-pcm_in";
935 #sound-dai-cells = <0>;
936 st,syscfg = <&syscfg_core>;
937 reg = <0x8d83000 0x158>;
938 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
939 dmas = <&fdma0 5 0 1>;
940 dma-names = "rx";
941
942 status = "disabled";
943 };
944
945 sti_uni_reader1: sti-uni-reader@8d84000 {
946 compatible = "st,stih407-uni-reader-hdmi";
947 #sound-dai-cells = <0>;
948 st,syscfg = <&syscfg_core>;
949 reg = <0x8d84000 0x158>;
950 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
951 dmas = <&fdma0 6 0 1>;
952 dma-names = "rx";
953
954 status = "disabled";
955 };
956
957 rc: rc@09518000 {
958 compatible = "st,comms-irb";
959 reg = <0x09518000 0x234>;
960 interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>;
961 rx-mode = "infrared";
962 pinctrl-names = "default";
963 pinctrl-0 = <&pinctrl_ir
964 &pinctrl_uhf
965 &pinctrl_tx
966 &pinctrl_tx_od>;
967 clocks = <&clk_sysin>;
968 resets = <&softreset STIH407_IRB_SOFTRESET>;
969
970 status = "disabled";
971 };
972
973 socinfo {
974 compatible = "st,stih407-socinfo";
975 st,syscfg = <&syscfg_core>;
976 };
977 };
978};