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Yusuke Godacf236022008-03-11 12:55:12 +09001/*
2 * Configuation settings for the Renesas R7780MP board
3 *
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +09004 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godacf236022008-03-11 12:55:12 +09005 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __R7780RP_H
27#define __R7780RP_H
28
29#undef DEBUG
30#define CONFIG_SH 1
31#define CONFIG_SH4A 1
32#define CONFIG_CPU_SH7780 1
33#define CONFIG_R7780MP 1
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090034#define CFG_R7780MP_OLD_FLASH 1
35#define __LITTLE_ENDIAN__ 1
Yusuke Godacf236022008-03-11 12:55:12 +090036
37/*
38 * Command line configuration.
39 */
40#define CONFIG_CMD_SDRAM
41#define CONFIG_CMD_FLASH
42#define CONFIG_CMD_MEMORY
43#define CONFIG_CMD_PCI
44#define CONFIG_CMD_NET
45#define CONFIG_CMD_PING
46#define CONFIG_CMD_ENV
47#define CONFIG_CMD_NFS
48#define CONFIG_CMD_IDE
49#define CONFIG_CMD_EXT2
50#define CONFIG_DOS_PARTITION
51
52#define CFG_SCIF_CONSOLE 1
53#define CONFIG_BAUDRATE 115200
54#define CONFIG_CONS_SCIF0 1
55
56#define CONFIG_BOOTDELAY 3
57#define CONFIG_BOOTARGS "console=ttySC0,115200"
58#define CONFIG_ENV_OVERWRITE 1
59
60/* check for keypress on bootdelay==0 */
61/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
62
Yusuke Godacf236022008-03-11 12:55:12 +090063#define CFG_SDRAM_BASE (0x08000000)
64#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
65
66#define CFG_LONGHELP
67#define CFG_PROMPT "=> "
68#define CFG_CBSIZE 256
69#define CFG_PBSIZE 256
70#define CFG_MAXARGS 16
71#define CFG_BARGSIZE 512
72/* List of legal baudrate settings for this board */
73#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
74
75#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
76#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
77
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090078/* Flash board support */
Yusuke Godacf236022008-03-11 12:55:12 +090079#define CFG_FLASH_BASE (0xA0000000)
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090080#ifdef CFG_R7780MP_OLD_FLASH
81/* NOR Flash (S29PL127J60TFI130) */
82# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
83# define CFG_MAX_FLASH_BANKS (2)
84# define CFG_MAX_FLASH_SECT 270
85# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
Yusuke Godacf236022008-03-11 12:55:12 +090086 CFG_FLASH_BASE + 0x100000,\
87 CFG_FLASH_BASE + 0x400000,\
88 CFG_FLASH_BASE + 0x700000, }
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090089#else /* CFG_R7780MP_OLD_FLASH */
90/* NOR Flash (Spantion S29GL256P) */
91# define CFG_MAX_FLASH_BANKS (1)
92# define CFG_MAX_FLASH_SECT 256
93# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
94#endif /* CFG_R7780MP_OLD_FLASH */
Yusuke Godacf236022008-03-11 12:55:12 +090095
96#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
97/* Address of u-boot image in Flash */
98#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090099#define CFG_MONITOR_LEN (256 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +0900100/* Size of DRAM reserved for malloc() use */
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900101#define CFG_MALLOC_LEN (1204 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +0900102
103/* size in bytes reserved for initial data */
104#define CFG_GBL_DATA_SIZE (256)
105#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
106#define CFG_RX_ETH_BUFFER (8)
107
108#define CFG_FLASH_CFI
109#define CFG_FLASH_CFI_DRIVER
110#undef CFG_FLASH_CFI_BROKEN_TABLE
111#undef CFG_FLASH_QUIET_TEST
112/* print 'E' for empty sector on flinfo */
113#define CFG_FLASH_EMPTY_INFO
114
115#define CFG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900116#define CFG_ENV_SECT_SIZE (256 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +0900117#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
118#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
Wolfgang Denka1be4762008-05-20 16:00:29 +0200119#define CFG_FLASH_ERASE_TOUT 120000
Yusuke Godacf236022008-03-11 12:55:12 +0900120#define CFG_FLASH_WRITE_TOUT 500
121
122/* Board Clock */
123#define CONFIG_SYS_CLK_FREQ 33333333
124#define TMU_CLK_DIVIDER 4
125#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
126
127/* PCI Controller */
128#if defined(CONFIG_CMD_PCI)
129#define CONFIG_PCI
130#define CONFIG_SH4_PCI
Nobuhiro Iwamatsu5aa5d672008-03-24 02:11:26 +0900131#define CONFIG_SH7780_PCI
Yusuke Godacf236022008-03-11 12:55:12 +0900132#define CONFIG_PCI_PNP
133#define CONFIG_PCI_SCAN_SHOW 1
134#define __io
135#define __mem_pci
136
137#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
138#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
139#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
140
141#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
142#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
143#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
144#endif /* CONFIG_CMD_PCI */
145
146#if defined(CONFIG_CMD_NET)
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900147/*
148#define CONFIG_NET_MULTI
149#define CONFIG_RTL8169
150*/
Yusuke Godacf236022008-03-11 12:55:12 +0900151/* AX88696L Support(NE2000 base chip) */
152#define CONFIG_DRIVER_NE2000
153#define CONFIG_DRIVER_AX88796L
154#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
155#endif
156
157/* Compact flash Support */
158#if defined(CONFIG_CMD_IDE)
159#define CONFIG_IDE_RESET 1
160#define CFG_PIO_MODE 1
161#define CFG_IDE_MAXBUS 1 /* IDE bus */
162#define CFG_IDE_MAXDEVICE 1
163#define CFG_ATA_BASE_ADDR 0xb4000000
164#define CFG_ATA_STRIDE 2 /* 1bit shift */
165#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
166#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
167#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
168#endif /* CONFIG_CMD_IDE */
169
170#endif /* __R7780RP_H */