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git01.mediatek.com / filogic / uboot / 0440d864ca9909836f85eac188a958678a8759a4 / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 0cc7f2b392433146d00b655e0f791bcb98bf404a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]2/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]6 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]10#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]11#include <net.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]12#include <asm/global_data.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]13#include <asm/mach-types.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]14#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]15#include <asm/arch/soc.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]16#include <asm/arch/mpp.h>
17#include "sheevaplug.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]21int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]22{
23 /*
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
27 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]28 mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
29 SHEEVAPLUG_OE_VAL_HIGH,
30 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]31
32 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]33 static const u32 kwmpp_config[] = {
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]34 MPP0_NF_IO2,
35 MPP1_NF_IO3,
36 MPP2_NF_IO4,
37 MPP3_NF_IO5,
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_UART0_RTS,
43 MPP9_UART0_CTS,
44 MPP10_UART0_TXD,
45 MPP11_UART0_RXD,
46 MPP12_SD_CLK,
47 MPP13_SD_CMD,
48 MPP14_SD_D0,
49 MPP15_SD_D1,
50 MPP16_SD_D2,
51 MPP17_SD_D3,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP20_GPIO,
55 MPP21_GPIO,
56 MPP22_GPIO,
57 MPP23_GPIO,
58 MPP24_GPIO,
59 MPP25_GPIO,
60 MPP26_GPIO,
61 MPP27_GPIO,
62 MPP28_GPIO,
63 MPP29_TSMP9,
64 MPP30_GPIO,
65 MPP31_GPIO,
66 MPP32_GPIO,
67 MPP33_GPIO,
68 MPP34_GPIO,
69 MPP35_GPIO,
70 MPP36_GPIO,
71 MPP37_GPIO,
72 MPP38_GPIO,
73 MPP39_GPIO,
74 MPP40_GPIO,
75 MPP41_GPIO,
76 MPP42_GPIO,
77 MPP43_GPIO,
78 MPP44_GPIO,
79 MPP45_GPIO,
80 MPP46_GPIO,
81 MPP47_GPIO,
82 MPP48_GPIO,
83 MPP49_GPIO,
84 0
85 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]86 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]87 return 0;
88}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]89
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]90int board_init(void)
91{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]92 /*
93 * arch number of board
94 */
95 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
96
97 /* adress of boot parameters */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]98 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]99
100 return 0;
101}
102
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]103#ifdef CONFIG_RESET_PHY_R
104/* Configure and enable MV88E1116 PHY */
105void reset_phy(void)
106{
107 u16 reg;
108 u16 devadr;
109 char *name = "egiga0";
110
111 if (miiphy_set_current_dev(name))
112 return;
113
114 /* command to read PHY dev address */
115 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
116 printf("Err..%s could not read PHY dev address\n",
117 __FUNCTION__);
118 return;
119 }
120
121 /*
122 * Enable RGMII delay on Tx and Rx for CPU port
123 * Ref: sec 4.7.2 of chip datasheet
124 */
125 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
126 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
127 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
128 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
129 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
130
131 /* reset the phy */
132 miiphy_reset(name, devadr);
133
134 printf("88E1116 Initialized on %s\n", name);
135}
136#endif /* CONFIG_RESET_PHY_R */