Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 2 | /* |
| 3 | * Generic PCIE host provided by e.g. QEMU |
| 4 | * |
| 5 | * Heavily based on drivers/pci/pcie_xilinx.c |
| 6 | * |
| 7 | * Copyright (C) 2016 Imagination Technologies |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <dm.h> |
| 12 | #include <pci.h> |
| 13 | |
| 14 | #include <asm/io.h> |
| 15 | |
| 16 | /** |
| 17 | * struct generic_ecam_pcie - generic_ecam PCIe controller state |
| 18 | * @cfg_base: The base address of memory mapped configuration space |
| 19 | */ |
| 20 | struct generic_ecam_pcie { |
| 21 | void *cfg_base; |
| 22 | }; |
| 23 | |
| 24 | /** |
| 25 | * pci_generic_ecam_conf_address() - Calculate the address of a config access |
| 26 | * @bus: Pointer to the PCI bus |
| 27 | * @bdf: Identifies the PCIe device to access |
| 28 | * @offset: The offset into the device's configuration space |
| 29 | * @paddress: Pointer to the pointer to write the calculates address to |
| 30 | * |
| 31 | * Calculates the address that should be accessed to perform a PCIe |
| 32 | * configuration space access for a given device identified by the PCIe |
| 33 | * controller device @pcie and the bus, device & function numbers in @bdf. If |
| 34 | * access to the device is not valid then the function will return an error |
| 35 | * code. Otherwise the address to access will be written to the pointer pointed |
| 36 | * to by @paddress. |
| 37 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 38 | static int pci_generic_ecam_conf_address(const struct udevice *bus, |
| 39 | pci_dev_t bdf, uint offset, |
| 40 | void **paddress) |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 41 | { |
| 42 | struct generic_ecam_pcie *pcie = dev_get_priv(bus); |
| 43 | void *addr; |
| 44 | |
| 45 | addr = pcie->cfg_base; |
| 46 | addr += PCI_BUS(bdf) << 20; |
| 47 | addr += PCI_DEV(bdf) << 15; |
| 48 | addr += PCI_FUNC(bdf) << 12; |
| 49 | addr += offset; |
| 50 | *paddress = addr; |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | /** |
| 56 | * pci_generic_ecam_read_config() - Read from configuration space |
| 57 | * @bus: Pointer to the PCI bus |
| 58 | * @bdf: Identifies the PCIe device to access |
| 59 | * @offset: The offset into the device's configuration space |
| 60 | * @valuep: A pointer at which to store the read value |
| 61 | * @size: Indicates the size of access to perform |
| 62 | * |
| 63 | * Read a value of size @size from offset @offset within the configuration |
| 64 | * space of the device identified by the bus, device & function numbers in @bdf |
| 65 | * on the PCI bus @bus. |
| 66 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 67 | static int pci_generic_ecam_read_config(const struct udevice *bus, |
| 68 | pci_dev_t bdf, uint offset, |
| 69 | ulong *valuep, enum pci_size_t size) |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 70 | { |
| 71 | return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address, |
| 72 | bdf, offset, valuep, size); |
| 73 | } |
| 74 | |
| 75 | /** |
| 76 | * pci_generic_ecam_write_config() - Write to configuration space |
| 77 | * @bus: Pointer to the PCI bus |
| 78 | * @bdf: Identifies the PCIe device to access |
| 79 | * @offset: The offset into the device's configuration space |
| 80 | * @value: The value to write |
| 81 | * @size: Indicates the size of access to perform |
| 82 | * |
| 83 | * Write the value @value of size @size from offset @offset within the |
| 84 | * configuration space of the device identified by the bus, device & function |
| 85 | * numbers in @bdf on the PCI bus @bus. |
| 86 | */ |
| 87 | static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf, |
| 88 | uint offset, ulong value, |
| 89 | enum pci_size_t size) |
| 90 | { |
| 91 | return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address, |
| 92 | bdf, offset, value, size); |
| 93 | } |
| 94 | |
| 95 | /** |
| 96 | * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state |
| 97 | * @dev: A pointer to the device being operated on |
| 98 | * |
| 99 | * Translate relevant data from the device tree pertaining to device @dev into |
| 100 | * state that the driver will later make use of. This state is stored in the |
| 101 | * device's private data structure. |
| 102 | * |
| 103 | * Return: 0 on success, else -EINVAL |
| 104 | */ |
| 105 | static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev) |
| 106 | { |
| 107 | struct generic_ecam_pcie *pcie = dev_get_priv(dev); |
| 108 | struct fdt_resource reg_res; |
| 109 | DECLARE_GLOBAL_DATA_PTR; |
| 110 | int err; |
| 111 | |
| 112 | err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", |
| 113 | 0, ®_res); |
| 114 | if (err < 0) { |
| 115 | pr_err("\"reg\" resource not found\n"); |
| 116 | return err; |
| 117 | } |
| 118 | |
| 119 | pcie->cfg_base = map_physmem(reg_res.start, |
| 120 | fdt_resource_size(®_res), |
| 121 | MAP_NOCACHE); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | static const struct dm_pci_ops pci_generic_ecam_ops = { |
| 127 | .read_config = pci_generic_ecam_read_config, |
| 128 | .write_config = pci_generic_ecam_write_config, |
| 129 | }; |
| 130 | |
| 131 | static const struct udevice_id pci_generic_ecam_ids[] = { |
| 132 | { .compatible = "pci-host-ecam-generic" }, |
| 133 | { } |
| 134 | }; |
| 135 | |
| 136 | U_BOOT_DRIVER(pci_generic_ecam) = { |
| 137 | .name = "pci_generic_ecam", |
| 138 | .id = UCLASS_PCI, |
| 139 | .of_match = pci_generic_ecam_ids, |
| 140 | .ops = &pci_generic_ecam_ops, |
| 141 | .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata, |
| 142 | .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie), |
| 143 | }; |