Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <command.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 8 | #include <env.h> |
Simon Glass | 3bbe70c | 2019-12-28 10:44:54 -0700 | [diff] [blame] | 9 | #include <fdt_support.h> |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 10 | #include <i2c.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 11 | #include <init.h> |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 12 | #include <netdev.h> |
| 13 | #include <linux/compiler.h> |
| 14 | #include <asm/mmu.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/cache.h> |
| 17 | #include <asm/immap_85xx.h> |
| 18 | #include <asm/fsl_law.h> |
| 19 | #include <asm/fsl_serdes.h> |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 20 | #include <asm/fsl_liodn.h> |
| 21 | #include <fm_eth.h> |
| 22 | |
| 23 | #include "t4rdb.h" |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 24 | #include "cpld.h" |
Ying Zhang | ff77905 | 2016-01-22 12:15:13 +0800 | [diff] [blame] | 25 | #include "../common/vid.h" |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | int checkboard(void) |
| 30 | { |
| 31 | struct cpu_type *cpu = gd->arch.cpu; |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 32 | u8 sw; |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 33 | |
| 34 | printf("Board: %sRDB, ", cpu->name); |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 35 | printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", |
| 36 | CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); |
| 37 | |
| 38 | sw = CPLD_READ(vbank); |
| 39 | sw = sw & CPLD_BANK_SEL_MASK; |
| 40 | |
| 41 | if (sw <= 7) |
| 42 | printf("vBank: %d\n", sw); |
| 43 | else |
| 44 | printf("Unsupported Bank=%x\n", sw); |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 45 | |
| 46 | puts("SERDES Reference Clocks:\n"); |
| 47 | printf(" SERDES1=100MHz SERDES2=156.25MHz\n" |
| 48 | " SERDES3=100MHz SERDES4=100MHz\n"); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | int board_early_init_r(void) |
| 54 | { |
| 55 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 56 | int flash_esel = find_tlb_idx((void *)flashbase, 1); |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * Remap Boot flash + PROMJET region to caching-inhibited |
| 60 | * so that flash can be erased properly. |
| 61 | */ |
| 62 | |
| 63 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
| 64 | flush_dcache(); |
| 65 | invalidate_icache(); |
| 66 | |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 67 | if (flash_esel == -1) { |
| 68 | /* very unlikely unless something is messed up */ |
| 69 | puts("Error: Could not find TLB for FLASH BASE\n"); |
| 70 | flash_esel = 2; /* give our best effort to continue */ |
| 71 | } else { |
| 72 | /* invalidate existing TLB entry for flash + promjet */ |
| 73 | disable_tlb(flash_esel); |
| 74 | } |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 75 | |
| 76 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
| 77 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 78 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); |
| 79 | |
Ying Zhang | ff77905 | 2016-01-22 12:15:13 +0800 | [diff] [blame] | 80 | /* |
| 81 | * Adjust core voltage according to voltage ID |
| 82 | * This function changes I2C mux to channel 2. |
| 83 | */ |
| 84 | if (adjust_vdd(0)) |
| 85 | printf("Warning: Adjusting core voltage failed.\n"); |
| 86 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | int misc_init_r(void) |
| 91 | { |
| 92 | return 0; |
| 93 | } |
| 94 | |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 95 | int ft_board_setup(void *blob, bd_t *bd) |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 96 | { |
| 97 | phys_addr_t base; |
| 98 | phys_size_t size; |
| 99 | |
| 100 | ft_cpu_setup(blob, bd); |
| 101 | |
Simon Glass | da1a134 | 2017-08-03 12:22:15 -0600 | [diff] [blame] | 102 | base = env_get_bootm_low(); |
| 103 | size = env_get_bootm_size(); |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 104 | |
| 105 | fdt_fixup_memory(blob, (u64)base, (u64)size); |
| 106 | |
| 107 | #ifdef CONFIG_PCI |
| 108 | pci_of_setup(blob, bd); |
| 109 | #endif |
| 110 | |
| 111 | fdt_fixup_liodn(blob); |
Sriram Dash | 9fd465c | 2016-09-16 17:12:15 +0530 | [diff] [blame] | 112 | fsl_fdt_fixup_dr_usb(blob, bd); |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 113 | |
| 114 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 115 | fdt_fixup_fman_ethernet(blob); |
| 116 | fdt_fixup_board_enet(blob); |
| 117 | #endif |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 118 | |
| 119 | return 0; |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* |
| 123 | * This function is called by bdinfo to print detail board information. |
| 124 | * As an exmaple for future board, we organize the messages into |
| 125 | * several sections. If applicable, the message is in the format of |
| 126 | * <name> = <value> |
| 127 | * It should aligned with normal output of bdinfo command. |
| 128 | * |
| 129 | * Voltage: Core, DDR and another configurable voltages |
| 130 | * Clock : Critical clocks which are not printed already |
| 131 | * RCW : RCW source if not printed already |
| 132 | * Misc : Other important information not in above catagories |
| 133 | */ |
| 134 | void board_detail(void) |
| 135 | { |
| 136 | int rcwsrc; |
| 137 | |
| 138 | /* RCW section SW3[4] */ |
| 139 | rcwsrc = 0x0; |
| 140 | puts("RCW source = "); |
| 141 | switch (rcwsrc & 0x1) { |
| 142 | case 0x1: |
| 143 | puts("SDHC/eMMC\n"); |
| 144 | break; |
| 145 | default: |
| 146 | puts("I2C normal addressing\n"); |
| 147 | break; |
| 148 | } |
| 149 | } |