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Kim Phillipsb22fc902007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * Michael Barkowski <michael.barkowski@freescale.com>
5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <common.h>
Simon Glasseba6b8d2019-11-14 12:57:50 -070013#include <eeprom.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060014#include <env.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -070015#include <fdt_support.h>
Simon Glass18afe102019-11-14 12:57:47 -070016#include <init.h>
Kim Phillipsb22fc902007-07-25 19:25:33 -050017#include <ioports.h>
18#include <mpc83xx.h>
19#include <i2c.h>
Kim Phillipsb22fc902007-07-25 19:25:33 -050020#include <miiphy.h>
21#include <command.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090022#include <linux/libfdt.h>
Simon Glass48b6c6b2019-11-14 12:57:16 -070023#include <u-boot/crc.h>
Kim Phillipsb22fc902007-07-25 19:25:33 -050024#if defined(CONFIG_PCI)
25#include <pci.h>
26#endif
Kim Phillipsb22fc902007-07-25 19:25:33 -050027#include <asm/mmu.h>
Kim Phillipsb22fc902007-07-25 19:25:33 -050028
Simon Glass39f90ba2017-03-31 08:40:25 -060029DECLARE_GLOBAL_DATA_PTR;
30
Kim Phillipsb22fc902007-07-25 19:25:33 -050031const qe_iop_conf_t qe_iop_conf_tab[] = {
32 /* UCC3 */
33 {1, 0, 1, 0, 1}, /* TxD0 */
34 {1, 1, 1, 0, 1}, /* TxD1 */
35 {1, 2, 1, 0, 1}, /* TxD2 */
36 {1, 3, 1, 0, 1}, /* TxD3 */
37 {1, 9, 1, 0, 1}, /* TxER */
38 {1, 12, 1, 0, 1}, /* TxEN */
39 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
40
41 {1, 4, 2, 0, 1}, /* RxD0 */
42 {1, 5, 2, 0, 1}, /* RxD1 */
43 {1, 6, 2, 0, 1}, /* RxD2 */
44 {1, 7, 2, 0, 1}, /* RxD3 */
45 {1, 8, 2, 0, 1}, /* RxER */
46 {1, 10, 2, 0, 1}, /* RxDV */
47 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
48 {1, 11, 2, 0, 1}, /* COL */
49 {1, 13, 2, 0, 1}, /* CRS */
50
51 /* UCC2 */
52 {0, 18, 1, 0, 1}, /* TxD0 */
53 {0, 19, 1, 0, 1}, /* TxD1 */
54 {0, 20, 1, 0, 1}, /* TxD2 */
55 {0, 21, 1, 0, 1}, /* TxD3 */
56 {0, 27, 1, 0, 1}, /* TxER */
57 {0, 30, 1, 0, 1}, /* TxEN */
58 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
59
60 {0, 22, 2, 0, 1}, /* RxD0 */
61 {0, 23, 2, 0, 1}, /* RxD1 */
62 {0, 24, 2, 0, 1}, /* RxD2 */
63 {0, 25, 2, 0, 1}, /* RxD3 */
64 {0, 26, 1, 0, 1}, /* RxER */
65 {0, 28, 2, 0, 1}, /* Rx_DV */
66 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
67 {0, 29, 2, 0, 1}, /* COL */
68 {0, 31, 2, 0, 1}, /* CRS */
69
70 {3, 4, 3, 0, 2}, /* MDIO */
71 {3, 5, 1, 0, 2}, /* MDC */
72
73 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
74};
75
Kim Phillipsb22fc902007-07-25 19:25:33 -050076int fixed_sdram(void);
77
Simon Glassd35f3382017-04-06 12:47:05 -060078int dram_init(void)
Kim Phillipsb22fc902007-07-25 19:25:33 -050079{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Kim Phillipsb22fc902007-07-25 19:25:33 -050081 u32 msize = 0;
82
83 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Simon Glass39f90ba2017-03-31 08:40:25 -060084 return -ENXIO;
Kim Phillipsb22fc902007-07-25 19:25:33 -050085
86 /* DDR SDRAM - Main SODIMM */
Mario Sixc9f92772019-01-21 09:18:15 +010087 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
Kim Phillipsb22fc902007-07-25 19:25:33 -050088
89 msize = fixed_sdram();
90
Simon Glass39f90ba2017-03-31 08:40:25 -060091 /* set total bus SDRAM size(bytes) -- DDR */
92 gd->ram_size = msize * 1024 * 1024;
93
94 return 0;
Kim Phillipsb22fc902007-07-25 19:25:33 -050095}
96
97/*************************************************************************
98 * fixed sdram init -- doesn't use serial presence detect.
99 ************************************************************************/
100int fixed_sdram(void)
101{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500103 u32 msize = 0;
104 u32 ddr_size;
105 u32 ddr_size_log2;
106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107 msize = CONFIG_SYS_DDR_SIZE;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500108 for (ddr_size = msize << 20, ddr_size_log2 = 0;
109 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
110 if (ddr_size & 1) {
111 return -1;
112 }
113 }
114 im->sysconf.ddrlaw[0].ar =
115 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
117 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
118 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
119 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
120 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
121 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
122 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
123 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
124 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
125 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
126 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
127 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500128 __asm__ __volatile__ ("sync");
129 udelay(200);
130
131 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
132 __asm__ __volatile__ ("sync");
133 return msize;
134}
135
136int checkboard(void)
137{
138 puts("Board: Freescale MPC8323ERDB\n");
139 return 0;
140}
141
142static struct pci_region pci_regions[] = {
143 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
145 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
146 size: CONFIG_SYS_PCI1_MEM_SIZE,
Kim Phillipsb22fc902007-07-25 19:25:33 -0500147 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
148 },
149 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
151 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
152 size: CONFIG_SYS_PCI1_MMIO_SIZE,
Kim Phillipsb22fc902007-07-25 19:25:33 -0500153 flags: PCI_REGION_MEM
154 },
155 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156 bus_start: CONFIG_SYS_PCI1_IO_BASE,
157 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
158 size: CONFIG_SYS_PCI1_IO_SIZE,
Kim Phillipsb22fc902007-07-25 19:25:33 -0500159 flags: PCI_REGION_IO
160 }
161};
162
163void pci_init_board(void)
164{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500166 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
167 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
168 struct pci_region *reg[] = { pci_regions };
169
170 /* Enable all 3 PCI_CLK_OUTPUTs. */
171 clk->occr |= 0xe0000000;
172
173 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500175 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500178 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
179
Peter Tysere2283322010-09-14 19:13:50 -0500180 mpc83xx_pci_init(1, reg);
Kim Phillipsb22fc902007-07-25 19:25:33 -0500181}
182
183#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600184int ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsb22fc902007-07-25 19:25:33 -0500185{
Kim Phillipsb22fc902007-07-25 19:25:33 -0500186 ft_cpu_setup(blob, bd);
Kim Phillipsb22fc902007-07-25 19:25:33 -0500187#ifdef CONFIG_PCI
188 ft_pci_setup(blob, bd);
189#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600190
191 return 0;
Kim Phillipsb22fc902007-07-25 19:25:33 -0500192}
Kim Phillips21416812007-08-15 22:30:33 -0500193#endif
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400196int mac_read_from_eeprom(void)
197{
198 uchar buf[28];
199 char str[18];
200 int i = 0;
201 unsigned int crc = 0;
202 unsigned char enetvar[32];
203
204 /* Read MAC addresses from EEPROM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400206 printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207 CONFIG_SYS_I2C_EEPROM_ADDR);
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400208 } else {
Wolfgang Denkc950cb12013-07-14 19:42:40 +0200209 uint32_t crc_buf;
210
211 memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
212
213 if (crc32(crc, buf, 24) == crc_buf) {
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400214 printf("Reading MAC from EEPROM\n");
215 for (i = 0; i < 4; i++) {
216 if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
217 sprintf(str,
218 "%02X:%02X:%02X:%02X:%02X:%02X",
219 buf[i * 6], buf[i * 6 + 1],
220 buf[i * 6 + 2], buf[i * 6 + 3],
221 buf[i * 6 + 4], buf[i * 6 + 5]);
222 sprintf((char *)enetvar,
223 i ? "eth%daddr" : "ethaddr", i);
Simon Glass6a38e412017-08-03 12:22:09 -0600224 env_set((char *)enetvar, str);
Michael Barkowskie6c56b62008-03-27 14:34:43 -0400225 }
226 }
227 }
228 }
229 return 0;
230}
231#endif /* CONFIG_I2C_MAC_OFFSET */