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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Angelo Dureghello67c4e482017-08-07 01:17:18 +02002/*
3 * Sysam stmark2 board configuration
4 *
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
Angelo Dureghello67c4e482017-08-07 01:17:18 +02006 */
7
8#ifndef __STMARK2_CONFIG_H
9#define __STMARK2_CONFIG_H
10
Mario Six790d8442018-03-28 14:38:20 +020011#define CONFIG_HOSTNAME "stmark2"
Angelo Dureghello67c4e482017-08-07 01:17:18 +020012
Tom Rini6a5dccc2022-11-16 13:10:41 -050013#define CFG_SYS_UART_PORT 0
Angelo Dureghello67c4e482017-08-07 01:17:18 +020014
15#define LDS_BOARD_TEXT \
16 board/sysam/stmark2/sbf_dram_init.o (.text*)
17
Angelo Dureghello67c4e482017-08-07 01:17:18 +020018#define CONFIG_EXTRA_ENV_SETTINGS \
19 "kern_size=0x700000\0" \
20 "loadaddr=0x40001000\0" \
21 "-(rootfs)\0" \
22 "update_uboot=loady ${loadaddr}; " \
23 "sf probe 0:1 50000000; " \
24 "sf erase 0 0x80000; " \
25 "sf write ${loadaddr} 0 ${filesize}\0" \
26 "update_kernel=loady ${loadaddr}; " \
27 "setenv kern_size ${filesize}; saveenv; " \
28 "sf probe 0:1 50000000; " \
29 "sf erase 0x100000 0x700000; " \
30 "sf write ${loadaddr} 0x100000 ${filesize}\0" \
31 "update_rootfs=loady ${loadaddr}; " \
32 "sf probe 0:1 50000000; " \
33 "sf erase 0x00800000 0x100000; " \
34 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
35 ""
36
Tom Rini6a5dccc2022-11-16 13:10:41 -050037#define CFG_SYS_SBFHDR_SIZE 0x7
Angelo Dureghello67c4e482017-08-07 01:17:18 +020038
Angelo Dureghello67c4e482017-08-07 01:17:18 +020039/* Input, PCI, Flexbus, and VCO */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020040
41#define CONFIG_PRAM 2048 /* 2048 KB */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020042
Tom Rini6a5dccc2022-11-16 13:10:41 -050043#define CFG_SYS_MBAR 0xFC000000
Angelo Dureghello67c4e482017-08-07 01:17:18 +020044
45/*
46 * Definitions for initial stack pointer and data area (in internal SRAM)
47 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_INIT_RAM_ADDR 0x80000000
Angelo Dureghello67c4e482017-08-07 01:17:18 +020049/* End of used area in internal SRAM */
Tom Rini6a5dccc2022-11-16 13:10:41 -050050#define CFG_SYS_INIT_RAM_SIZE 0x10000
51#define CFG_SYS_INIT_RAM_CTRL 0x221
52#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020053 GENERATED_GBL_DATA_SIZE) - 32)
Tom Rini6a5dccc2022-11-16 13:10:41 -050054#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32)
Angelo Dureghello67c4e482017-08-07 01:17:18 +020055
56/*
57 * Start addresses for the final memory configuration
58 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050059 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
Angelo Dureghello67c4e482017-08-07 01:17:18 +020060 */
Tom Rinibb4dd962022-11-16 13:10:37 -050061#define CFG_SYS_SDRAM_BASE 0x40000000
62#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020063
Tom Rini6a5dccc2022-11-16 13:10:41 -050064#define CFG_SYS_DRAM_TEST
Angelo Dureghello67c4e482017-08-07 01:17:18 +020065
66#if defined(CONFIG_CF_SBF)
67#define CONFIG_SERIAL_BOOT
68#endif
69
Angelo Dureghello67c4e482017-08-07 01:17:18 +020070/* Reserve 256 kB for Monitor */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020071
72/*
73 * For booting Linux, the board info and command line data
74 * have to be in the first 8 MB of memory, since this is
75 * the maximum mapped by the Linux kernel during initialization ??
76 */
77/* Initial Memory map for Linux */
Tom Rini6a5dccc2022-11-16 13:10:41 -050078#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
Tom Rinibb4dd962022-11-16 13:10:37 -050079 (CFG_SYS_SDRAM_SIZE << 20))
Angelo Dureghello67c4e482017-08-07 01:17:18 +020080
81/* Configuration for environment
82 * Environment is embedded in u-boot in the second sector of the flash
83 */
84
Angelo Dureghello67c4e482017-08-07 01:17:18 +020085/* Cache Configuration */
Tom Rini6a5dccc2022-11-16 13:10:41 -050086#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
87 CFG_SYS_INIT_RAM_SIZE - 8)
88#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
89 CFG_SYS_INIT_RAM_SIZE - 4)
90#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
91#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA)
92#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -050093 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020094 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -050095#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020096 CF_CACR_ICINVA | CF_CACR_EUSP)
Tom Rini6a5dccc2022-11-16 13:10:41 -050097#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020098 CF_CACR_DEC | CF_CACR_DDCM_P | \
99 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
100
Tom Rini6a5dccc2022-11-16 13:10:41 -0500101#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
102 CFG_SYS_INIT_RAM_SIZE - 12)
Angelo Dureghello67c4e482017-08-07 01:17:18 +0200103
Angelo Dureghello67c4e482017-08-07 01:17:18 +0200104#endif /* __STMARK2_CONFIG_H */