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git01.mediatek.com / filogic / uboot / 0401fb6b70e3b1b4522e1eeac71fcaf2c2b53a92 / . / arch / arm / dts / imx6sx-softing-vining-2000.dts
blob: 371890ff6084412c4e9c4495063b319aaab59682 [file] [log] [blame]
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]1/*
2 * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Softing VIN|ING 2000";
17 compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
18
Marek Vasutf953c992019-05-17 22:25:24 +0200[diff] [blame]19 aliases {
20 mmc0 = &usdhc4;
21 mmc1 = &usdhc2;
22 };
23
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]24 chosen {
25 stdout-path = &uart1;
26 };
27
28 memory@80000000 {
29 device_type = "memory";
30 reg = <0x80000000 0x40000000>;
31 };
32
33 reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
34 compatible = "regulator-fixed";
35 regulator-name = "usb_otg1_vbus";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_usb_otg1>;
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 reg_peri_3v3: regulator-peri_3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "peri_3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 };
50
51 pwmleds {
52 compatible = "pwm-leds";
53
54 red {
55 label = "red";
56 max-brightness = <255>;
57 pwms = <&pwm6 0 50000>;
58 };
59
60 green {
61 label = "green";
62 max-brightness = <255>;
63 pwms = <&pwm2 0 50000>;
64 };
65
66 blue {
67 label = "blue";
68 max-brightness = <255>;
69 pwms = <&pwm1 0 50000>;
70 };
71 };
72};
73
74&adc1 {
75 vref-supply = <&reg_peri_3v3>;
76 status = "okay";
77};
78
79&cpu0 {
80 /*
81 * This board has a shared rail of reg_arm and reg_soc (supplied by
82 * sw1a_reg) which is modeled below, but still this module behaves
83 * unstable without higher voltages. Hence, set higher voltages here.
84 */
85 operating-points = <
86 /* kHz uV */
87 996000 1250000
88 792000 1175000
89 396000 1175000
90 198000 1175000
91 >;
92 fsl,soc-operating-points = <
93 /* ARM kHz SOC uV */
94 996000 1250000
95 792000 1175000
96 396000 1175000
97 198000 1175000
98 >;
99};
100
101&ecspi4 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi4>;
104 cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
105 status = "okay";
106};
107
108&fec1 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_enet1>;
111 phy-supply = <&reg_peri_3v3>;
112 phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
113 phy-reset-duration = <5>;
114 phy-mode = "rmii";
115 phy-handle = <&ethphy0>;
116 status = "okay";
117
118 mdio {
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 ethphy0: ethernet0-phy@0 {
123 reg = <0>;
124 max-speed = <100>;
125 interrupt-parent = <&gpio2>;
126 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
127 };
128 };
129};
130
131&fec2 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_enet2>;
134 phy-supply = <&reg_peri_3v3>;
135 phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
136 phy-reset-duration = <5>;
137 phy-mode = "rmii";
138 phy-handle = <&ethphy1>;
139 status = "okay";
140
141 mdio {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 ethphy1: ethernet1-phy@0 {
146 reg = <0>;
147 max-speed = <100>;
148 interrupt-parent = <&gpio2>;
149 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
150 };
151 };
152};
153
154&flexcan1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_flexcan1>;
157 status = "okay";
158};
159
160&flexcan2 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan2>;
163 status = "okay";
164};
165
166&i2c1 {
167 clock-frequency = <100000>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 status = "okay";
171
172 proximity: sx9500@28 {
173 compatible = "semtech,sx9500";
174 reg = <0x28>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_sx9500>;
177 interrupt-parent = <&gpio2>;
178 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
179 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
180 };
181
182 pmic: pfuze100@8 {
183 compatible = "fsl,pfuze200";
184 reg = <0x08>;
185
186 regulators {
187 sw1a_reg: sw1ab {
188 regulator-min-microvolt = <300000>;
189 regulator-max-microvolt = <1875000>;
190 regulator-boot-on;
191 regulator-always-on;
192 regulator-ramp-delay = <6250>;
193 };
194
195 sw2_reg: sw2 {
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-boot-on;
199 regulator-always-on;
200 };
201
202 sw3a_reg: sw3a {
203 regulator-min-microvolt = <400000>;
204 regulator-max-microvolt = <1975000>;
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 sw3b_reg: sw3b {
210 regulator-min-microvolt = <400000>;
211 regulator-max-microvolt = <1975000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 snvs_reg: vsnvs {
217 regulator-min-microvolt = <1000000>;
218 regulator-max-microvolt = <3000000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 vref_reg: vrefddr {
224 regulator-boot-on;
225 regulator-always-on;
226 };
227
228 vgen1_reg: vgen1 {
229 regulator-min-microvolt = <800000>;
230 regulator-max-microvolt = <1550000>;
231 regulator-always-on;
232 };
233
234 vgen2_reg: vgen2 {
235 regulator-min-microvolt = <800000>;
236 regulator-max-microvolt = <1550000>;
237 };
238
239 vgen3_reg: vgen3 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 vgen4_reg: vgen4 {
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 };
250
251 vgen5_reg: vgen5 {
252 regulator-min-microvolt = <1800000>;
253 regulator-max-microvolt = <3300000>;
254 regulator-always-on;
255 };
256
257 vgen6_reg: vgen6 {
258 regulator-min-microvolt = <1800000>;
259 regulator-max-microvolt = <3300000>;
260 regulator-always-on;
261 };
262 };
263 };
264};
265
266&i2c3 {
267 clock-frequency = <100000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c3>;
270 status = "okay";
271};
272
273&iomuxc {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_gpios>;
276
277 pinctrl_ecspi4: ecspi4grp {
278 fsl,pins = <
279 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
280 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
281 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
282 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
283 >;
284 };
285
286 pinctrl_enet1: enet1grp {
287 fsl,pins = <
288 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
289 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
290 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
291 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
292 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
293 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
294 MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
295 /* LAN8720 PHY Reset */
296 MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
297 /* MDIO */
298 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
299 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
300 /* IRQ from PHY */
301 MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
302 >;
303 };
304
305 pinctrl_enet2: enet2grp {
306 fsl,pins = <
307 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
308 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
309 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
310 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
311 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
312 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
313 MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
314 /* LAN8720 PHY Reset */
315 MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
316 /* MDIO */
317 MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
318 MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
319 /* IRQ from PHY */
320 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
321 >;
322 };
323
324 pinctrl_flexcan1: flexcan1grp {
325 fsl,pins = <
326 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
327 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
328 >;
329 };
330
331 pinctrl_flexcan2: flexcan2grp {
332 fsl,pins = <
333 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
334 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
335 >;
336 };
337
338 pinctrl_gpios: gpiosgrp {
339 fsl,pins = <
340 /* reset external uC */
341 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
342 /* IRQ from external uC */
343 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
344 /* overcurrent detection */
345 MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
346 >;
347 };
348
349 pinctrl_i2c1: i2c1grp {
350 fsl,pins = <
351 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
352 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
353 >;
354 };
355
356 pinctrl_i2c3: i2c3grp {
357 fsl,pins = <
358 MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
359 MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
360 >;
361 };
362
363 pinctrl_pwm1: pwm1grp-1 {
364 fsl,pins = <
365 /* blue LED */
366 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
367 >;
368 };
369
370 pinctrl_pwm2: pwm2grp-1 {
371 fsl,pins = <
372 /* green LED */
373 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
374 >;
375 };
376
377 pinctrl_pwm6: pwm6grp-1 {
378 fsl,pins = <
379 /* red LED */
380 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
381 >;
382 };
383
384 pinctrl_sx9500: sx9500grp {
385 fsl,pins = <
386 /* Reset */
387 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
388 /* IRQ */
389 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
390 >;
391 };
392
393 pinctrl_uart1: uart1grp {
394 fsl,pins = <
395 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
396 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
397 >;
398 };
399
400 pinctrl_uart2: uart2grp {
401 fsl,pins = <
402 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
403 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
404 >;
405 };
406
407 pinctrl_usb_otg1: usbotg1grp {
408 fsl,pins = <
409 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
410 >;
411 };
412
413 pinctrl_usb_otg1_id: usbotg1idgrp {
414 fsl,pins = <
415 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
416 >;
417 };
418
419 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
420 fsl,pins = <
421 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
422 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
423 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
424 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
425 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
426 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
427 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
428 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
429 >;
430 };
431
432 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
433 fsl,pins = <
434 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
435 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
436 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
437 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
438 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
439 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
440 >;
441 };
442
443 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
444 fsl,pins = <
445 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
446 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
447 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
448 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
449 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
450 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
451 >;
452 };
453
454 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
455 fsl,pins = <
456 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
457 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
458 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
459 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
460 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
461 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
462 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
463 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
464 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
465 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
466 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
467 >;
468 };
469
470 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
471 fsl,pins = <
472 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
473 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
474 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
475 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
476 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
477 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
478 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
479 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
480 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
481 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
482 >;
483 };
484
485 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
486 fsl,pins = <
487 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
488 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
489 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
490 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
491 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
492 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
493 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
494 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
495 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
496 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
497 >;
498 };
499};
500
501&pwm1 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_pwm1>;
504 status = "okay";
505};
506
507&pwm2 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_pwm2>;
510 status = "okay";
511};
512
513&pwm6 {
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_pwm6>;
516 status = "okay";
517};
518
519&reg_arm {
520 vin-supply = <&sw1a_reg>;
521};
522
523&reg_soc {
524 vin-supply = <&sw1a_reg>;
525};
526
527&snvs_poweroff {
528 status = "okay";
529};
530
531&uart1 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart1>;
534 status = "okay";
535};
536
537&uart2 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart2>;
540 status = "okay";
541};
542
543&usbotg1 {
544 vbus-supply = <&reg_usb_otg1_vbus>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_usb_otg1_id>;
547 status = "okay";
548};
549
550&usbotg2 {
551 dr_mode = "host";
552 status = "okay";
553};
554
555&usdhc2 {
556 pinctrl-names = "default", "state_100mhz", "state_200mhz";
557 pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
558 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
559 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
560 cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
561 keep-power-in-suspend;
562 status = "okay";
563};
564
565&usdhc4 {
566 /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
567 * not on necessary 1.8V.
568 */
569 pinctrl-names = "default", "state_100mhz", "state_200mhz";
570 pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
571 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
572 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
573 bus-width = <8>;
574 keep-power-in-suspend;
575 non-removable;
576 cap-mmc-hw-reset;
577 status = "okay";
578};