| Simon Glass | 803f6b5 | 2018-12-10 10:37:43 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * max98090.h -- MAX98090 ALSA SoC Audio driver |
| 4 | * |
| 5 | * Copyright 2011 Maxim Integrated Products |
| 6 | */ |
| 7 | |
| 8 | #ifndef _MAX98090_H |
| 9 | #define _MAX98090_H |
| 10 | |
| 11 | #include "maxim_codec.h" |
| 12 | |
| 13 | /* MAX98090 Registers Definition */ |
| 14 | |
| 15 | #define M98090_REG_SOFTWARE_RESET 0x00 |
| 16 | #define M98090_REG_DEVICE_STATUS 0x01 |
| 17 | |
| 18 | #define M98090_REG_QUICK_SAMPLE_RATE 0x05 |
| 19 | #define M98090_REG_DAI_INTERFACE 0x06 |
| 20 | #define M98090_REG_DAC_PATH 0x07 |
| 21 | |
| 22 | #define M98090_REG_MIC_BIAS_VOLTAGE 0x12 |
| 23 | #define M98090_REG_DIGITAL_MIC_ENABLE 0x13 |
| 24 | #define M98090_REG_DIGITAL_MIC_CONFIG 0x14 |
| 25 | #define M98090_REG_SYSTEM_CLOCK 0x1B |
| 26 | #define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D |
| 27 | #define M98090_REG_CLOCK_MODE 0x1C |
| 28 | #define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E |
| 29 | |
| 30 | #define M98090_REG_MASTER_MODE 0x21 |
| 31 | #define M98090_REG_INTERFACE_FORMAT 0x22 |
| 32 | #define M98090_REG_IO_CONFIGURATION 0x25 |
| 33 | #define M98090_REG_FILTER_CONFIG 0x26 |
| 34 | |
| 35 | #define M98090_REG_LEFT_HP_MIXER 0x29 |
| 36 | #define M98090_REG_RIGHT_HP_MIXER 0x2a |
| 37 | #define M98090_REG_HP_CONTROL 0x2b |
| 38 | #define M98090_REG_LEFT_HP_VOLUME 0x2c |
| 39 | #define M98090_REG_RIGHT_HP_VOLUME 0x2d |
| 40 | #define M98090_REG_LEFT_SPK_MIXER 0x2e |
| 41 | #define M98090_REG_RIGHT_SPK_MIXER 0x2f |
| 42 | #define M98090_REG_SPK_CONTROL 0x30 |
| 43 | #define M98090_REG_LEFT_SPK_VOLUME 0x31 |
| 44 | #define M98090_REG_RIGHT_SPK_VOLUME 0x32 |
| 45 | |
| 46 | #define M98090_REG_RCV_LOUTL_CONTROL 0x38 |
| 47 | #define M98090_REG_RCV_LOUTL_VOLUME 0x39 |
| 48 | #define M98090_REG_LOUTR_MIXER 0x3a |
| 49 | #define M98090_REG_LOUTR_CONTROL 0x3b |
| 50 | #define M98090_REG_LOUTR_VOLUME 0x3c |
| 51 | #define M98090_REG_JACK_DETECT 0x3d |
| 52 | #define M98090_REG_INPUT_ENABLE 0x3e |
| 53 | #define M98090_REG_OUTPUT_ENABLE 0x3f |
| 54 | #define M98090_REG_LEVEL_CONTROL 0x40 |
| 55 | #define M98090_REG_DSP_FILTER_ENABLE 0x41 |
| 56 | #define M98090_REG_BIAS_CONTROL 0x42 |
| 57 | #define M98090_REG_DAC_CONTROL 0x43 |
| 58 | #define M98090_REG_ADC_CONTROL 0x44 |
| 59 | #define M98090_REG_DEVICE_SHUTDOWN 0x45 |
| 60 | |
| 61 | #define M98090_REG_REVISION_ID 0xff |
| 62 | |
| 63 | #define M98090_REG_CNT (0xff + 1) |
| 64 | #define M98090_REG_MAX_CACHed 0x45 |
| 65 | |
| 66 | /* MAX98090 Registers Bit Fields */ |
| 67 | |
| 68 | /* |
| 69 | * M98090_REG_SOFTWARE_RESET 0x00 |
| 70 | */ |
| 71 | #define M98090_SWRESET_MASK BIT(7) |
| 72 | |
| 73 | /* |
| 74 | * M98090_REG_QUICK_SAMPLE_RATE 0x05 |
| 75 | */ |
| 76 | #define M98090_SR_96K_MASK BIT(5) |
| 77 | #define M98090_SR_96K_SHIFT 5 |
| 78 | #define M98090_SR_96K_WIDTH 1 |
| 79 | #define M98090_SR_32K_MASK BIT(4) |
| 80 | #define M98090_SR_32K_SHIFT 4 |
| 81 | #define M98090_SR_32K_WIDTH 1 |
| 82 | #define M98090_SR_48K_MASK BIT(3) |
| 83 | #define M98090_SR_48K_SHIFT 3 |
| 84 | #define M98090_SR_48K_WIDTH 1 |
| 85 | #define M98090_SR_44K1_MASK BIT(2) |
| 86 | #define M98090_SR_44K1_SHIFT 2 |
| 87 | #define M98090_SR_44K1_WIDTH 1 |
| 88 | #define M98090_SR_16K_MASK BIT(1) |
| 89 | #define M98090_SR_16K_SHIFT 1 |
| 90 | #define M98090_SR_16K_WIDTH 1 |
| 91 | #define M98090_SR_8K_MASK BIT(0) |
| 92 | #define M98090_SR_8K_SHIFT 0 |
| 93 | #define M98090_SR_8K_WIDTH 1 |
| 94 | #define M98090_SR_MASK 0x3F |
| 95 | #define M98090_SR_ALL_SHIFT 0 |
| 96 | #define M98090_SR_ALL_WIDTH 8 |
| 97 | #define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH) |
| 98 | |
| 99 | /* |
| 100 | * M98090_REG_DAI_INTERFACE 0x06 |
| 101 | */ |
| 102 | #define M98090_RJ_M_MASK BIT(5) |
| 103 | #define M98090_RJ_M_SHIFT 5 |
| 104 | #define M98090_RJ_M_WIDTH 1 |
| 105 | #define M98090_RJ_S_MASK BIT(4) |
| 106 | #define M98090_RJ_S_SHIFT 4 |
| 107 | #define M98090_RJ_S_WIDTH 1 |
| 108 | #define M98090_LJ_M_MASK BIT(3) |
| 109 | #define M98090_LJ_M_SHIFT 3 |
| 110 | #define M98090_LJ_M_WIDTH 1 |
| 111 | #define M98090_LJ_S_MASK BIT(2) |
| 112 | #define M98090_LJ_S_SHIFT 2 |
| 113 | #define M98090_LJ_S_WIDTH 1 |
| 114 | #define M98090_I2S_M_MASK BIT(1) |
| 115 | #define M98090_I2S_M_SHIFT 1 |
| 116 | #define M98090_I2S_M_WIDTH 1 |
| 117 | #define M98090_I2S_S_MASK BIT(0) |
| 118 | #define M98090_I2S_S_SHIFT 0 |
| 119 | #define M98090_I2S_S_WIDTH 1 |
| 120 | #define M98090_DAI_ALL_SHIFT 0 |
| 121 | #define M98090_DAI_ALL_WIDTH 8 |
| 122 | #define M98090_DAI_ALL_NUM BIT(M98090_DAI_ALL_WIDTH) |
| 123 | |
| 124 | /* |
| 125 | * M98090_REG_DAC_PATH 0x07 |
| 126 | */ |
| 127 | #define M98090_DIG2_HP_MASK BIT(7) |
| 128 | #define M98090_DIG2_HP_SHIFT 7 |
| 129 | #define M98090_DIG2_HP_WIDTH 1 |
| 130 | #define M98090_DIG2_EAR_MASK BIT(6) |
| 131 | #define M98090_DIG2_EAR_SHIFT 6 |
| 132 | #define M98090_DIG2_EAR_WIDTH 1 |
| 133 | #define M98090_DIG2_SPK_MASK BIT(5) |
| 134 | #define M98090_DIG2_SPK_SHIFT 5 |
| 135 | #define M98090_DIG2_SPK_WIDTH 1 |
| 136 | #define M98090_DIG2_LOUT_MASK BIT(4) |
| 137 | #define M98090_DIG2_LOUT_SHIFT 4 |
| 138 | #define M98090_DIG2_LOUT_WIDTH 1 |
| 139 | #define M98090_DIG2_ALL_SHIFT 0 |
| 140 | #define M98090_DIG2_ALL_WIDTH 8 |
| 141 | #define M98090_DIG2_ALL_NUM BIT(M98090_DIG2_ALL_WIDTH) |
| 142 | |
| 143 | /* |
| 144 | * M98090_REG_MIC_BIAS_VOLTAGE 0x12 |
| 145 | */ |
| 146 | #define M98090_MBVSEL_MASK (3 << 0) |
| 147 | #define M98090_MBVSEL_SHIFT 0 |
| 148 | #define M98090_MBVSEL_WIDTH 2 |
| 149 | #define M98090_MBVSEL_2V8 (3 << 0) |
| 150 | #define M98090_MBVSEL_2V55 (2 << 0) |
| 151 | #define M98090_MBVSEL_2V4 BIT(0) |
| 152 | #define M98090_MBVSEL_2V2 (0 << 0) |
| 153 | |
| 154 | /* |
| 155 | * M98090_REG_DIGITAL_MIC_ENABLE 0x13 |
| 156 | */ |
| 157 | #define M98090_MICCLK_MASK (7 << 4) |
| 158 | #define M98090_MICCLK_SHIFT 4 |
| 159 | #define M98090_MICCLK_WIDTH 3 |
| 160 | #define M98090_DIGMIC4_MASK BIT(3) |
| 161 | #define M98090_DIGMIC4_SHIFT 3 |
| 162 | #define M98090_DIGMIC4_WIDTH 1 |
| 163 | #define M98090_DIGMIC4_NUM BIT(M98090_DIGMIC4_WIDTH) |
| 164 | #define M98090_DIGMIC3_MASK BIT(2) |
| 165 | #define M98090_DIGMIC3_SHIFT 2 |
| 166 | #define M98090_DIGMIC3_WIDTH 1 |
| 167 | #define M98090_DIGMIC3_NUM BIT(M98090_DIGMIC3_WIDTH) |
| 168 | #define M98090_DIGMICR_MASK BIT(1) |
| 169 | #define M98090_DIGMICR_SHIFT 1 |
| 170 | #define M98090_DIGMICR_WIDTH 1 |
| 171 | #define M98090_DIGMICR_NUM BIT(M98090_DIGMICR_WIDTH) |
| 172 | #define M98090_DIGMICL_MASK BIT(0) |
| 173 | #define M98090_DIGMICL_SHIFT 0 |
| 174 | #define M98090_DIGMICL_WIDTH 1 |
| 175 | #define M98090_DIGMICL_NUM BIT(M98090_DIGMICL_WIDTH) |
| 176 | |
| 177 | /* |
| 178 | * M98090_REG_DIGITAL_MIC_CONFIG 0x14 |
| 179 | */ |
| 180 | #define M98090_DMIC_COMP_MASK (15 << 4) |
| 181 | #define M98090_DMIC_COMP_SHIFT 4 |
| 182 | #define M98090_DMIC_COMP_WIDTH 4 |
| 183 | #define M98090_DMIC_COMP_NUM BIT(M98090_DMIC_COMP_WIDTH) |
| 184 | #define M98090_DMIC_FREQ_MASK (3 << 0) |
| 185 | #define M98090_DMIC_FREQ_SHIFT 0 |
| 186 | #define M98090_DMIC_FREQ_WIDTH 2 |
| 187 | |
| 188 | /* |
| 189 | * M98090_REG_CLOCK_MODE 0x1B |
| 190 | */ |
| 191 | #define M98090_PSCLK_MASK (3 << 4) |
| 192 | #define M98090_PSCLK_SHIFT 4 |
| 193 | #define M98090_PSCLK_WIDTH 2 |
| 194 | #define M98090_PSCLK_DISABLED (0 << 4) |
| 195 | #define M98090_PSCLK_DIV1 BIT(4) |
| 196 | #define M98090_PSCLK_DIV2 (2 << 4) |
| 197 | #define M98090_PSCLK_DIV4 (3 << 4) |
| 198 | |
| 199 | /* |
| 200 | * M98090_REG_INTERFACE_FORMAT 0x22 |
| 201 | */ |
| 202 | #define M98090_RJ_MASK BIT(5) |
| 203 | #define M98090_RJ_SHIFT 5 |
| 204 | #define M98090_RJ_WIDTH 1 |
| 205 | #define M98090_WCI_MASK BIT(4) |
| 206 | #define M98090_WCI_SHIFT 4 |
| 207 | #define M98090_WCI_WIDTH 1 |
| 208 | #define M98090_BCI_MASK BIT(3) |
| 209 | #define M98090_BCI_SHIFT 3 |
| 210 | #define M98090_BCI_WIDTH 1 |
| 211 | #define M98090_DLY_MASK BIT(2) |
| 212 | #define M98090_DLY_SHIFT 2 |
| 213 | #define M98090_DLY_WIDTH 1 |
| 214 | #define M98090_WS_MASK (3 << 0) |
| 215 | #define M98090_WS_SHIFT 0 |
| 216 | #define M98090_WS_WIDTH 2 |
| 217 | #define M98090_WS_NUM BIT(M98090_WS_WIDTH) |
| 218 | |
| 219 | /* M98090_REG_IO_CONFIGURATION 0x25 */ |
| 220 | #define M98090_LTEN_MASK BIT(5) |
| 221 | #define M98090_LTEN_SHIFT 5 |
| 222 | #define M98090_LTEN_WIDTH 1 |
| 223 | #define M98090_LTEN_NUM BIT(M98090_LTEN_WIDTH) |
| 224 | #define M98090_LBEN_MASK BIT(4) |
| 225 | #define M98090_LBEN_SHIFT 4 |
| 226 | #define M98090_LBEN_WIDTH 1 |
| 227 | #define M98090_LBEN_NUM BIT(M98090_LBEN_WIDTH) |
| 228 | #define M98090_DMONO_MASK BIT(3) |
| 229 | #define M98090_DMONO_SHIFT 3 |
| 230 | #define M98090_DMONO_WIDTH 1 |
| 231 | #define M98090_DMONO_NUM BIT(M98090_DMONO_WIDTH) |
| 232 | #define M98090_HIZOFF_MASK BIT(2) |
| 233 | #define M98090_HIZOFF_SHIFT 2 |
| 234 | #define M98090_HIZOFF_WIDTH 1 |
| 235 | #define M98090_HIZOFF_NUM BIT(M98090_HIZOFF_WIDTH) |
| 236 | #define M98090_SDOEN_MASK BIT(1) |
| 237 | #define M98090_SDOEN_SHIFT 1 |
| 238 | #define M98090_SDOEN_WIDTH 1 |
| 239 | #define M98090_SDOEN_NUM BIT(M98090_SDOEN_WIDTH) |
| 240 | #define M98090_SDIEN_MASK BIT(0) |
| 241 | #define M98090_SDIEN_SHIFT 0 |
| 242 | #define M98090_SDIEN_WIDTH 1 |
| 243 | #define M98090_SDIEN_NUM BIT(M98090_SDIEN_WIDTH) |
| 244 | |
| 245 | /* |
| 246 | * M98090_REG_FILTER_CONFIG 0x26 |
| 247 | */ |
| 248 | #define M98090_MODE_MASK BIT(7) |
| 249 | #define M98090_MODE_SHIFT 7 |
| 250 | #define M98090_MODE_WIDTH 1 |
| 251 | #define M98090_AHPF_MASK BIT(6) |
| 252 | #define M98090_AHPF_SHIFT 6 |
| 253 | #define M98090_AHPF_WIDTH 1 |
| 254 | #define M98090_AHPF_NUM BIT(M98090_AHPF_WIDTH) |
| 255 | #define M98090_DHPF_MASK BIT(5) |
| 256 | #define M98090_DHPF_SHIFT 5 |
| 257 | #define M98090_DHPF_WIDTH 1 |
| 258 | #define M98090_DHPF_NUM BIT(M98090_DHPF_WIDTH) |
| 259 | #define M98090_DHF_MASK BIT(4) |
| 260 | #define M98090_DHF_SHIFT 4 |
| 261 | #define M98090_DHF_WIDTH 1 |
| 262 | #define M98090_FLT_DMIC34MODE_MASK BIT(3) |
| 263 | #define M98090_FLT_DMIC34MODE_SHIFT 3 |
| 264 | #define M98090_FLT_DMIC34MODE_WIDTH 1 |
| 265 | #define M98090_FLT_DMIC34HPF_MASK BIT(2) |
| 266 | #define M98090_FLT_DMIC34HPF_SHIFT 2 |
| 267 | #define M98090_FLT_DMIC34HPF_WIDTH 1 |
| 268 | #define M98090_FLT_DMIC34HPF_NUM BIT(M98090_FLT_DMIC34HPF_WIDTH) |
| 269 | |
| 270 | /* |
| 271 | * M98090_REG_CLOCK_MODE |
| 272 | */ |
| 273 | #define M98090_FREQ_MASK (15 << 4) |
| 274 | #define M98090_FREQ_SHIFT 4 |
| 275 | #define M98090_FREQ_WIDTH 4 |
| 276 | #define M98090_USE_M1_MASK BIT(0) |
| 277 | #define M98090_USE_M1_SHIFT 0 |
| 278 | #define M98090_USE_M1_WIDTH 1 |
| 279 | #define M98090_USE_M1_NUM BIT(M98090_USE_M1_WIDTH) |
| 280 | |
| 281 | /* |
| 282 | * M98090_REG_LEFT_HP_MIXER 0x29 |
| 283 | */ |
| 284 | #define M98090_MIXHPL_MIC2_MASK BIT(5) |
| 285 | #define M98090_MIXHPL_MIC2_SHIFT 5 |
| 286 | #define M98090_MIXHPL_MIC2_WIDTH 1 |
| 287 | #define M98090_MIXHPL_MIC1_MASK BIT(4) |
| 288 | #define M98090_MIXHPL_MIC1_SHIFT 4 |
| 289 | #define M98090_MIXHPL_MIC1_WIDTH 1 |
| 290 | #define M98090_MIXHPL_LINEB_MASK BIT(3) |
| 291 | #define M98090_MIXHPL_LINEB_SHIFT 3 |
| 292 | #define M98090_MIXHPL_LINEB_WIDTH 1 |
| 293 | #define M98090_MIXHPL_LINEA_MASK BIT(2) |
| 294 | #define M98090_MIXHPL_LINEA_SHIFT 2 |
| 295 | #define M98090_MIXHPL_LINEA_WIDTH 1 |
| 296 | #define M98090_MIXHPL_DACR_MASK BIT(1) |
| 297 | #define M98090_MIXHPL_DACR_SHIFT 1 |
| 298 | #define M98090_MIXHPL_DACR_WIDTH 1 |
| 299 | #define M98090_MIXHPL_DACL_MASK BIT(0) |
| 300 | #define M98090_MIXHPL_DACL_SHIFT 0 |
| 301 | #define M98090_MIXHPL_DACL_WIDTH 1 |
| 302 | #define M98090_MIXHPL_MASK (63 << 0) |
| 303 | #define M98090_MIXHPL_SHIFT 0 |
| 304 | #define M98090_MIXHPL_WIDTH 6 |
| 305 | |
| 306 | /* |
| 307 | * M98090_REG_RIGHT_HP_MIXER 0x2A |
| 308 | */ |
| 309 | #define M98090_MIXHPR_MIC2_MASK BIT(5) |
| 310 | #define M98090_MIXHPR_MIC2_SHIFT 5 |
| 311 | #define M98090_MIXHPR_MIC2_WIDTH 1 |
| 312 | #define M98090_MIXHPR_MIC1_MASK BIT(4) |
| 313 | #define M98090_MIXHPR_MIC1_SHIFT 4 |
| 314 | #define M98090_MIXHPR_MIC1_WIDTH 1 |
| 315 | #define M98090_MIXHPR_LINEB_MASK BIT(3) |
| 316 | #define M98090_MIXHPR_LINEB_SHIFT 3 |
| 317 | #define M98090_MIXHPR_LINEB_WIDTH 1 |
| 318 | #define M98090_MIXHPR_LINEA_MASK BIT(2) |
| 319 | #define M98090_MIXHPR_LINEA_SHIFT 2 |
| 320 | #define M98090_MIXHPR_LINEA_WIDTH 1 |
| 321 | #define M98090_MIXHPR_DACR_MASK BIT(1) |
| 322 | #define M98090_MIXHPR_DACR_SHIFT 1 |
| 323 | #define M98090_MIXHPR_DACR_WIDTH 1 |
| 324 | #define M98090_MIXHPR_DACL_MASK BIT(0) |
| 325 | #define M98090_MIXHPR_DACL_SHIFT 0 |
| 326 | #define M98090_MIXHPR_DACL_WIDTH 1 |
| 327 | #define M98090_MIXHPR_MASK (63 << 0) |
| 328 | #define M98090_MIXHPR_SHIFT 0 |
| 329 | #define M98090_MIXHPR_WIDTH 6 |
| 330 | |
| 331 | /* |
| 332 | * M98090_REG_LEFT_HP_VOLUME 0x2C |
| 333 | */ |
| 334 | #define M98090_HPLM_MASK BIT(7) |
| 335 | #define M98090_HPLM_SHIFT 7 |
| 336 | #define M98090_HPLM_WIDTH 1 |
| 337 | #define M98090_HPVOLL_MASK (31 << 0) |
| 338 | #define M98090_HPVOLL_SHIFT 0 |
| 339 | #define M98090_HPVOLL_WIDTH 5 |
| 340 | #define M98090_HPVOLL_NUM BIT(M98090_HPVOLL_WIDTH) |
| 341 | |
| 342 | /* |
| 343 | * M98090_REG_RIGHT_HP_VOLUME 0x2D |
| 344 | */ |
| 345 | #define M98090_HPRM_MASK BIT(7) |
| 346 | #define M98090_HPRM_SHIFT 7 |
| 347 | #define M98090_HPRM_WIDTH 1 |
| 348 | #define M98090_HPVOLR_MASK (31 << 0) |
| 349 | #define M98090_HPVOLR_SHIFT 0 |
| 350 | #define M98090_HPVOLR_WIDTH 5 |
| 351 | #define M98090_HPVOLR_NUM BIT(M98090_HPVOLR_WIDTH) |
| 352 | |
| 353 | /* |
| 354 | * M98090_REG_LEFT_SPK_MIXER 0x2E |
| 355 | */ |
| 356 | #define M98090_MIXSPL_MIC2_MASK BIT(5) |
| 357 | #define M98090_MIXSPL_MIC2_SHIFT 5 |
| 358 | #define M98090_MIXSPL_MIC2_WIDTH 1 |
| 359 | #define M98090_MIXSPL_MIC1_MASK BIT(4) |
| 360 | #define M98090_MIXSPL_MIC1_SHIFT 4 |
| 361 | #define M98090_MIXSPL_MIC1_WIDTH 1 |
| 362 | #define M98090_MIXSPL_LINEB_MASK BIT(3) |
| 363 | #define M98090_MIXSPL_LINEB_SHIFT 3 |
| 364 | #define M98090_MIXSPL_LINEB_WIDTH 1 |
| 365 | #define M98090_MIXSPL_LINEA_MASK BIT(2) |
| 366 | #define M98090_MIXSPL_LINEA_SHIFT 2 |
| 367 | #define M98090_MIXSPL_LINEA_WIDTH 1 |
| 368 | #define M98090_MIXSPL_DACR_MASK BIT(1) |
| 369 | #define M98090_MIXSPL_DACR_SHIFT 1 |
| 370 | #define M98090_MIXSPL_DACR_WIDTH 1 |
| 371 | #define M98090_MIXSPL_DACL_MASK BIT(0) |
| 372 | #define M98090_MIXSPL_DACL_SHIFT 0 |
| 373 | #define M98090_MIXSPL_DACL_WIDTH 1 |
| 374 | #define M98090_MIXSPL_MASK (63 << 0) |
| 375 | #define M98090_MIXSPL_SHIFT 0 |
| 376 | #define M98090_MIXSPL_WIDTH 6 |
| 377 | #define M98090_MIXSPR_DACR_MASK BIT(1) |
| 378 | #define M98090_MIXSPR_DACR_SHIFT 1 |
| 379 | #define M98090_MIXSPR_DACR_WIDTH 1 |
| 380 | |
| 381 | /* |
| 382 | * M98090_REG_RIGHT_SPK_MIXER 0x2F |
| 383 | */ |
| 384 | #define M98090_SPK_SLAVE_MASK BIT(6) |
| 385 | #define M98090_SPK_SLAVE_SHIFT 6 |
| 386 | #define M98090_SPK_SLAVE_WIDTH 1 |
| 387 | #define M98090_MIXSPR_MIC2_MASK BIT(5) |
| 388 | #define M98090_MIXSPR_MIC2_SHIFT 5 |
| 389 | #define M98090_MIXSPR_MIC2_WIDTH 1 |
| 390 | #define M98090_MIXSPR_MIC1_MASK BIT(4) |
| 391 | #define M98090_MIXSPR_MIC1_SHIFT 4 |
| 392 | #define M98090_MIXSPR_MIC1_WIDTH 1 |
| 393 | #define M98090_MIXSPR_LINEB_MASK BIT(3) |
| 394 | #define M98090_MIXSPR_LINEB_SHIFT 3 |
| 395 | #define M98090_MIXSPR_LINEB_WIDTH 1 |
| 396 | #define M98090_MIXSPR_LINEA_MASK BIT(2) |
| 397 | #define M98090_MIXSPR_LINEA_SHIFT 2 |
| 398 | #define M98090_MIXSPR_LINEA_WIDTH 1 |
| 399 | #define M98090_MIXSPR_DACR_MASK BIT(1) |
| 400 | #define M98090_MIXSPR_DACR_SHIFT 1 |
| 401 | #define M98090_MIXSPR_DACR_WIDTH 1 |
| 402 | #define M98090_MIXSPR_DACL_MASK BIT(0) |
| 403 | #define M98090_MIXSPR_DACL_SHIFT 0 |
| 404 | #define M98090_MIXSPR_DACL_WIDTH 1 |
| 405 | #define M98090_MIXSPR_MASK (63 << 0) |
| 406 | #define M98090_MIXSPR_SHIFT 0 |
| 407 | #define M98090_MIXSPR_WIDTH 6 |
| 408 | |
| 409 | /* |
| 410 | * M98090_REG_LEFT_SPK_VOLUME 0x31 |
| 411 | */ |
| 412 | #define M98090_SPLM_MASK BIT(7) |
| 413 | #define M98090_SPLM_SHIFT 7 |
| 414 | #define M98090_SPLM_WIDTH 1 |
| 415 | #define M98090_SPVOLL_MASK (63 << 0) |
| 416 | #define M98090_SPVOLL_SHIFT 0 |
| 417 | #define M98090_SPVOLL_WIDTH 6 |
| 418 | #define M98090_SPVOLL_NUM 40 |
| 419 | |
| 420 | /* |
| 421 | * M98090_REG_RIGHT_SPK_VOLUME 0x32 |
| 422 | */ |
| 423 | #define M98090_SPRM_MASK BIT(7) |
| 424 | #define M98090_SPRM_SHIFT 7 |
| 425 | #define M98090_SPRM_WIDTH 1 |
| 426 | #define M98090_SPVOLR_MASK (63 << 0) |
| 427 | #define M98090_SPVOLR_SHIFT 0 |
| 428 | #define M98090_SPVOLR_WIDTH 6 |
| 429 | #define M98090_SPVOLR_NUM 40 |
| 430 | |
| 431 | /* |
| 432 | * M98090_REG_RCV_LOUTL_MIXER 0x37 |
| 433 | */ |
| 434 | #define M98090_MIXRCVL_MIC2_MASK BIT(5) |
| 435 | #define M98090_MIXRCVL_MIC2_SHIFT 5 |
| 436 | #define M98090_MIXRCVL_MIC2_WIDTH 1 |
| 437 | #define M98090_MIXRCVL_MIC1_MASK BIT(4) |
| 438 | #define M98090_MIXRCVL_MIC1_SHIFT 4 |
| 439 | #define M98090_MIXRCVL_MIC1_WIDTH 1 |
| 440 | #define M98090_MIXRCVL_LINEB_MASK BIT(3) |
| 441 | #define M98090_MIXRCVL_LINEB_SHIFT 3 |
| 442 | #define M98090_MIXRCVL_LINEB_WIDTH 1 |
| 443 | #define M98090_MIXRCVL_LINEA_MASK BIT(2) |
| 444 | #define M98090_MIXRCVL_LINEA_SHIFT 2 |
| 445 | #define M98090_MIXRCVL_LINEA_WIDTH 1 |
| 446 | #define M98090_MIXRCVL_DACR_MASK BIT(1) |
| 447 | #define M98090_MIXRCVL_DACR_SHIFT 1 |
| 448 | #define M98090_MIXRCVL_DACR_WIDTH 1 |
| 449 | #define M98090_MIXRCVL_DACL_MASK BIT(0) |
| 450 | #define M98090_MIXRCVL_DACL_SHIFT 0 |
| 451 | #define M98090_MIXRCVL_DACL_WIDTH 1 |
| 452 | #define M98090_MIXRCVL_MASK (63 << 0) |
| 453 | #define M98090_MIXRCVL_SHIFT 0 |
| 454 | #define M98090_MIXRCVL_WIDTH 6 |
| 455 | |
| 456 | /* |
| 457 | * M98090_REG_RCV_LOUTL_CONTROL 0x38 |
| 458 | */ |
| 459 | #define M98090_MIXRCVLG_MASK (3 << 0) |
| 460 | #define M98090_MIXRCVLG_SHIFT 0 |
| 461 | #define M98090_MIXRCVLG_WIDTH 2 |
| 462 | #define M98090_MIXRCVLG_NUM BIT(M98090_MIXRCVLG_WIDTH) |
| 463 | |
| 464 | /* |
| 465 | * M98090_REG_RCV_LOUTL_VOLUME 0x39 |
| 466 | */ |
| 467 | #define M98090_RCVLM_MASK BIT(7) |
| 468 | #define M98090_RCVLM_SHIFT 7 |
| 469 | #define M98090_RCVLM_WIDTH 1 |
| 470 | #define M98090_RCVLVOL_MASK (31 << 0) |
| 471 | #define M98090_RCVLVOL_SHIFT 0 |
| 472 | #define M98090_RCVLVOL_WIDTH 5 |
| 473 | #define M98090_RCVLVOL_NUM BIT(M98090_RCVLVOL_WIDTH) |
| 474 | |
| 475 | /* |
| 476 | * M98090_REG_LOUTR_MIXER 0x3A |
| 477 | */ |
| 478 | #define M98090_LINMOD_MASK BIT(7) |
| 479 | #define M98090_LINMOD_SHIFT 7 |
| 480 | #define M98090_LINMOD_WIDTH 1 |
| 481 | #define M98090_MIXRCVR_MIC2_MASK BIT(5) |
| 482 | #define M98090_MIXRCVR_MIC2_SHIFT 5 |
| 483 | #define M98090_MIXRCVR_MIC2_WIDTH 1 |
| 484 | #define M98090_MIXRCVR_MIC1_MASK BIT(4) |
| 485 | #define M98090_MIXRCVR_MIC1_SHIFT 4 |
| 486 | #define M98090_MIXRCVR_MIC1_WIDTH 1 |
| 487 | #define M98090_MIXRCVR_LINEB_MASK BIT(3) |
| 488 | #define M98090_MIXRCVR_LINEB_SHIFT 3 |
| 489 | #define M98090_MIXRCVR_LINEB_WIDTH 1 |
| 490 | #define M98090_MIXRCVR_LINEA_MASK BIT(2) |
| 491 | #define M98090_MIXRCVR_LINEA_SHIFT 2 |
| 492 | #define M98090_MIXRCVR_LINEA_WIDTH 1 |
| 493 | #define M98090_MIXRCVR_DACR_MASK BIT(1) |
| 494 | #define M98090_MIXRCVR_DACR_SHIFT 1 |
| 495 | #define M98090_MIXRCVR_DACR_WIDTH 1 |
| 496 | #define M98090_MIXRCVR_DACL_MASK BIT(0) |
| 497 | #define M98090_MIXRCVR_DACL_SHIFT 0 |
| 498 | #define M98090_MIXRCVR_DACL_WIDTH 1 |
| 499 | #define M98090_MIXRCVR_MASK (63 << 0) |
| 500 | #define M98090_MIXRCVR_SHIFT 0 |
| 501 | #define M98090_MIXRCVR_WIDTH 6 |
| 502 | |
| 503 | /* |
| 504 | * M98090_REG_LOUTR_VOLUME 0x3C |
| 505 | */ |
| 506 | #define M98090_RCVRM_MASK BIT(7) |
| 507 | #define M98090_RCVRM_SHIFT 7 |
| 508 | #define M98090_RCVRM_WIDTH 1 |
| 509 | #define M98090_RCVRVOL_MASK (31 << 0) |
| 510 | #define M98090_RCVRVOL_SHIFT 0 |
| 511 | #define M98090_RCVRVOL_WIDTH 5 |
| 512 | #define M98090_RCVRVOL_NUM BIT(M98090_RCVRVOL_WIDTH) |
| 513 | |
| 514 | /* |
| 515 | * M98090_REG_JACK_DETECT 0x3D |
| 516 | */ |
| 517 | #define M98090_JDETEN_MASK BIT(7) |
| 518 | #define M98090_JDETEN_SHIFT 7 |
| 519 | #define M98090_JDETEN_WIDTH 1 |
| 520 | #define M98090_JDWK_MASK BIT(6) |
| 521 | #define M98090_JDWK_SHIFT 6 |
| 522 | #define M98090_JDWK_WIDTH 1 |
| 523 | #define M98090_JDEB_MASK (3 << 0) |
| 524 | #define M98090_JDEB_SHIFT 0 |
| 525 | #define M98090_JDEB_WIDTH 2 |
| 526 | #define M98090_JDEB_25MS (0 << 0) |
| 527 | #define M98090_JDEB_50MS BIT(0) |
| 528 | #define M98090_JDEB_100MS (2 << 0) |
| 529 | #define M98090_JDEB_200MS (3 << 0) |
| 530 | |
| 531 | /* |
| 532 | * M98090_REG_INPUT_ENABLE 0x3E |
| 533 | */ |
| 534 | #define M98090_MBEN_MASK BIT(4) |
| 535 | #define M98090_MBEN_SHIFT 4 |
| 536 | #define M98090_MBEN_WIDTH 1 |
| 537 | #define M98090_LINEAEN_MASK BIT(3) |
| 538 | #define M98090_LINEAEN_SHIFT 3 |
| 539 | #define M98090_LINEAEN_WIDTH 1 |
| 540 | #define M98090_LINEBEN_MASK BIT(2) |
| 541 | #define M98090_LINEBEN_SHIFT 2 |
| 542 | #define M98090_LINEBEN_WIDTH 1 |
| 543 | #define M98090_ADREN_MASK BIT(1) |
| 544 | #define M98090_ADREN_SHIFT 1 |
| 545 | #define M98090_ADREN_WIDTH 1 |
| 546 | #define M98090_ADLEN_MASK BIT(0) |
| 547 | #define M98090_ADLEN_SHIFT 0 |
| 548 | #define M98090_ADLEN_WIDTH 1 |
| 549 | |
| 550 | /* |
| 551 | * M98090_REG_OUTPUT_ENABLE 0x3F |
| 552 | */ |
| 553 | #define M98090_HPREN_MASK BIT(7) |
| 554 | #define M98090_HPREN_SHIFT 7 |
| 555 | #define M98090_HPREN_WIDTH 1 |
| 556 | #define M98090_HPLEN_MASK BIT(6) |
| 557 | #define M98090_HPLEN_SHIFT 6 |
| 558 | #define M98090_HPLEN_WIDTH 1 |
| 559 | #define M98090_SPREN_MASK BIT(5) |
| 560 | #define M98090_SPREN_SHIFT 5 |
| 561 | #define M98090_SPREN_WIDTH 1 |
| 562 | #define M98090_SPLEN_MASK BIT(4) |
| 563 | #define M98090_SPLEN_SHIFT 4 |
| 564 | #define M98090_SPLEN_WIDTH 1 |
| 565 | #define M98090_RCVLEN_MASK BIT(3) |
| 566 | #define M98090_RCVLEN_SHIFT 3 |
| 567 | #define M98090_RCVLEN_WIDTH 1 |
| 568 | #define M98090_RCVREN_MASK BIT(2) |
| 569 | #define M98090_RCVREN_SHIFT 2 |
| 570 | #define M98090_RCVREN_WIDTH 1 |
| 571 | #define M98090_DAREN_MASK BIT(1) |
| 572 | #define M98090_DAREN_SHIFT 1 |
| 573 | #define M98090_DAREN_WIDTH 1 |
| 574 | #define M98090_DALEN_MASK BIT(0) |
| 575 | #define M98090_DALEN_SHIFT 0 |
| 576 | #define M98090_DALEN_WIDTH 1 |
| 577 | |
| 578 | /* |
| 579 | * M98090_REG_LEVEL_CONTROL 0x40 |
| 580 | */ |
| 581 | #define M98090_ZDENN_MASK BIT(2) |
| 582 | #define M98090_ZDENN_SHIFT 2 |
| 583 | #define M98090_ZDENN_WIDTH 1 |
| 584 | #define M98090_ZDENN_NUM BIT(M98090_ZDENN_WIDTH) |
| 585 | #define M98090_VS2ENN_MASK BIT(1) |
| 586 | #define M98090_VS2ENN_SHIFT 1 |
| 587 | #define M98090_VS2ENN_WIDTH 1 |
| 588 | #define M98090_VS2ENN_NUM BIT(M98090_VS2ENN_WIDTH) |
| 589 | #define M98090_VSENN_MASK BIT(0) |
| 590 | #define M98090_VSENN_SHIFT 0 |
| 591 | #define M98090_VSENN_WIDTH 1 |
| 592 | #define M98090_VSENN_NUM BIT(M98090_VSENN_WIDTH) |
| 593 | |
| 594 | /* |
| 595 | * M98090_REG_BIAS_CONTROL 0x42 |
| 596 | */ |
| 597 | #define M98090_VCM_MODE_MASK BIT(0) |
| 598 | #define M98090_VCM_MODE_SHIFT 0 |
| 599 | #define M98090_VCM_MODE_WIDTH 1 |
| 600 | #define M98090_VCM_MODE_NUM BIT(M98090_VCM_MODE_WIDTH) |
| 601 | |
| 602 | /* |
| 603 | * M98090_REG_DAC_CONTROL 0x43 |
| 604 | */ |
| 605 | #define M98090_PERFMODE_MASK BIT(1) |
| 606 | #define M98090_PERFMODE_SHIFT 1 |
| 607 | #define M98090_PERFMODE_WIDTH 1 |
| 608 | #define M98090_PERFMODE_NUM BIT(M98090_PERFMODE_WIDTH) |
| 609 | #define M98090_DACHP_MASK BIT(0) |
| 610 | #define M98090_DACHP_SHIFT 0 |
| 611 | #define M98090_DACHP_WIDTH 1 |
| 612 | #define M98090_DACHP_NUM BIT(M98090_DACHP_WIDTH) |
| 613 | |
| 614 | /* |
| 615 | * M98090_REG_ADC_CONTROL 0x44 |
| 616 | */ |
| 617 | #define M98090_OSR128_MASK BIT(2) |
| 618 | #define M98090_OSR128_SHIFT 2 |
| 619 | #define M98090_OSR128_WIDTH 1 |
| 620 | #define M98090_ADCDITHER_MASK BIT(1) |
| 621 | #define M98090_ADCDITHER_SHIFT 1 |
| 622 | #define M98090_ADCDITHER_WIDTH 1 |
| 623 | #define M98090_ADCDITHER_NUM BIT(M98090_ADCDITHER_WIDTH) |
| 624 | #define M98090_ADCHP_MASK BIT(0) |
| 625 | #define M98090_ADCHP_SHIFT 0 |
| 626 | #define M98090_ADCHP_WIDTH 1 |
| 627 | #define M98090_ADCHP_NUM BIT(M98090_ADCHP_WIDTH) |
| 628 | |
| 629 | /* |
| 630 | * M98090_REG_DEVICE_SHUTDOWN 0x45 |
| 631 | */ |
| 632 | #define M98090_SHDNN_MASK BIT(7) |
| 633 | #define M98090_SHDNN_SHIFT 7 |
| 634 | #define M98090_SHDNN_WIDTH 1 |
| 635 | |
| 636 | /* |
| 637 | * M98090_REG_REVISION_ID 0xFF |
| 638 | */ |
| 639 | #define M98090_REVID_MASK (255 << 0) |
| 640 | #define M98090_REVID_SHIFT 0 |
| 641 | #define M98090_REVID_WIDTH 8 |
| 642 | #define M98090_REVID_NUM BIT(M98090_REVID_WIDTH) |
| 643 | |
| 644 | /* function prototype */ |
| 645 | |
| 646 | /* |
| 647 | * initialise max98090 sound codec device for the given configuration |
| 648 | * |
| 649 | * @param blob FDT node for codec values |
| 650 | * @param sampling_rate Sampling rate (Hz) |
| 651 | * @param mclk_freq MCLK Frequency (Hz) |
| 652 | * @param bits_per_sample bits per Sample (must be 16 or 24) |
| 653 | * |
| 654 | * @returns -1 for error and 0 Success. |
| 655 | */ |
| 656 | int max98090_init(const void *blob, int sampling_rate, int mclk_freq, |
| 657 | int bits_per_sample); |
| 658 | int max98090_set_sysclk(struct maxim_priv *max98090, uint freq); |
| 659 | int max98090_hw_params(struct maxim_priv *max98090, uint rate, |
| 660 | uint bits_per_sample); |
| 661 | int max98090_device_init(struct maxim_priv *max98090); |
| 662 | int max98090_set_fmt(struct maxim_priv *max98090, int fmt); |
| 663 | #endif |