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git01.mediatek.com / filogic / uboot / 03c23f103545dbbd3a79ecdc38dfce7a48512446 / . / arch / arm / mach-socfpga / include / mach / sdram_gen5.h
blob: a238d5d17fe92a1f2dbe390b33fc9f0ffc278e74 [file] [log] [blame]
Tom Rini4606fc72018-05-20 09:47:45 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tien Fong Chee38fad172017-12-05 15:58:00 +0800[diff] [blame]2/*
3 * Copyright Altera Corporation (C) 2014-2015
Tien Fong Chee38fad172017-12-05 15:58:00 +0800[diff] [blame]4 */
5#ifndef _SOCFPGA_SDRAM_GEN5_H_
6#define _SOCFPGA_SDRAM_GEN5_H_
7
8#ifndef __ASSEMBLY__
9
10unsigned long sdram_calculate_size(void);
11int sdram_mmr_init_full(unsigned int sdr_phy_reg);
12int sdram_calibration_full(void);
13
14const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
15
16void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
17void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
18const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
19const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
20const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
21
22#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
23
24struct socfpga_sdr_ctrl {
25 u32 ctrl_cfg;
26 u32 dram_timing1;
27 u32 dram_timing2;
28 u32 dram_timing3;
29 u32 dram_timing4; /* 0x10 */
30 u32 lowpwr_timing;
31 u32 dram_odt;
32 u32 extratime1;
33 u32 __padding0[3];
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
36 u32 dram_dev_width;
37 u32 dram_sts;
38 u32 dram_intr;
39 u32 sbe_count; /* 0x40 */
40 u32 dbe_count;
41 u32 err_addr;
42 u32 drop_count;
43 u32 drop_addr; /* 0x50 */
44 u32 lowpwr_eq;
45 u32 lowpwr_ack;
46 u32 static_cfg;
47 u32 ctrl_width; /* 0x60 */
48 u32 cport_width;
49 u32 cport_wmap;
50 u32 cport_rmap;
51 u32 rfifo_cmap; /* 0x70 */
52 u32 wfifo_cmap;
53 u32 cport_rdwr;
54 u32 port_cfg;
55 u32 fpgaport_rst; /* 0x80 */
56 u32 __padding1;
57 u32 fifo_cfg;
58 u32 protport_default;
59 u32 prot_rule_addr; /* 0x90 */
60 u32 prot_rule_id;
61 u32 prot_rule_data;
62 u32 prot_rule_rdwr;
63 u32 __padding2[3];
64 u32 mp_priority; /* 0xac */
65 u32 mp_weight0; /* 0xb0 */
66 u32 mp_weight1;
67 u32 mp_weight2;
68 u32 mp_weight3;
69 u32 mp_pacing0; /* 0xc0 */
70 u32 mp_pacing1;
71 u32 mp_pacing2;
72 u32 mp_pacing3;
73 u32 mp_threshold0; /* 0xd0 */
74 u32 mp_threshold1;
75 u32 mp_threshold2;
76 u32 __padding3[29];
77 u32 phy_ctrl0; /* 0x150 */
78 u32 phy_ctrl1;
79 u32 phy_ctrl2;
80};
81
82/* SDRAM configuration structure for the SPL. */
83struct socfpga_sdram_config {
84 u32 ctrl_cfg;
85 u32 dram_timing1;
86 u32 dram_timing2;
87 u32 dram_timing3;
88 u32 dram_timing4;
89 u32 lowpwr_timing;
90 u32 dram_odt;
91 u32 extratime1;
92 u32 dram_addrw;
93 u32 dram_if_width;
94 u32 dram_dev_width;
95 u32 dram_intr;
96 u32 lowpwr_eq;
97 u32 static_cfg;
98 u32 ctrl_width;
99 u32 cport_width;
100 u32 cport_wmap;
101 u32 cport_rmap;
102 u32 rfifo_cmap;
103 u32 wfifo_cmap;
104 u32 cport_rdwr;
105 u32 port_cfg;
106 u32 fpgaport_rst;
107 u32 fifo_cfg;
108 u32 mp_priority;
109 u32 mp_weight0;
110 u32 mp_weight1;
111 u32 mp_weight2;
112 u32 mp_weight3;
113 u32 mp_pacing0;
114 u32 mp_pacing1;
115 u32 mp_pacing2;
116 u32 mp_pacing3;
117 u32 mp_threshold0;
118 u32 mp_threshold1;
119 u32 mp_threshold2;
120 u32 phy_ctrl0;
121};
122
123struct socfpga_sdram_rw_mgr_config {
124 u8 activate_0_and_1;
125 u8 activate_0_and_1_wait1;
126 u8 activate_0_and_1_wait2;
127 u8 activate_1;
128 u8 clear_dqs_enable;
129 u8 guaranteed_read;
130 u8 guaranteed_read_cont;
131 u8 guaranteed_write;
132 u8 guaranteed_write_wait0;
133 u8 guaranteed_write_wait1;
134 u8 guaranteed_write_wait2;
135 u8 guaranteed_write_wait3;
136 u8 idle;
137 u8 idle_loop1;
138 u8 idle_loop2;
139 u8 init_reset_0_cke_0;
140 u8 init_reset_1_cke_0;
141 u8 lfsr_wr_rd_bank_0;
142 u8 lfsr_wr_rd_bank_0_data;
143 u8 lfsr_wr_rd_bank_0_dqs;
144 u8 lfsr_wr_rd_bank_0_nop;
145 u8 lfsr_wr_rd_bank_0_wait;
146 u8 lfsr_wr_rd_bank_0_wl_1;
147 u8 lfsr_wr_rd_dm_bank_0;
148 u8 lfsr_wr_rd_dm_bank_0_data;
149 u8 lfsr_wr_rd_dm_bank_0_dqs;
150 u8 lfsr_wr_rd_dm_bank_0_nop;
151 u8 lfsr_wr_rd_dm_bank_0_wait;
152 u8 lfsr_wr_rd_dm_bank_0_wl_1;
153 u8 mrs0_dll_reset;
154 u8 mrs0_dll_reset_mirr;
155 u8 mrs0_user;
156 u8 mrs0_user_mirr;
157 u8 mrs1;
158 u8 mrs1_mirr;
159 u8 mrs2;
160 u8 mrs2_mirr;
161 u8 mrs3;
162 u8 mrs3_mirr;
163 u8 precharge_all;
164 u8 read_b2b;
165 u8 read_b2b_wait1;
166 u8 read_b2b_wait2;
167 u8 refresh_all;
168 u8 rreturn;
169 u8 sgle_read;
170 u8 zqcl;
171
172 u8 true_mem_data_mask_width;
173 u8 mem_address_mirroring;
174 u8 mem_data_mask_width;
175 u8 mem_data_width;
176 u8 mem_dq_per_read_dqs;
177 u8 mem_dq_per_write_dqs;
178 u8 mem_if_read_dqs_width;
179 u8 mem_if_write_dqs_width;
180 u8 mem_number_of_cs_per_dimm;
181 u8 mem_number_of_ranks;
182 u8 mem_virtual_groups_per_read_dqs;
183 u8 mem_virtual_groups_per_write_dqs;
184};
185
186struct socfpga_sdram_io_config {
187 u16 delay_per_opa_tap;
188 u8 delay_per_dchain_tap;
189 u8 delay_per_dqs_en_dchain_tap;
190 u8 dll_chain_length;
191 u8 dqdqs_out_phase_max;
192 u8 dqs_en_delay_max;
193 u8 dqs_en_delay_offset;
194 u8 dqs_en_phase_max;
195 u8 dqs_in_delay_max;
196 u8 dqs_in_reserve;
197 u8 dqs_out_reserve;
198 u8 io_in_delay_max;
199 u8 io_out1_delay_max;
200 u8 io_out2_delay_max;
201 u8 shift_dqs_en_when_shift_dqs;
202};
203
204struct socfpga_sdram_misc_config {
205 u32 reg_file_init_seq_signature;
206 u8 afi_rate_ratio;
207 u8 calib_lfifo_offset;
208 u8 calib_vfifo_offset;
209 u8 enable_super_quick_calibration;
210 u8 max_latency_count_width;
211 u8 read_valid_fifo_size;
212 u8 tinit_cntr0_val;
213 u8 tinit_cntr1_val;
214 u8 tinit_cntr2_val;
215 u8 treset_cntr0_val;
216 u8 treset_cntr1_val;
217 u8 treset_cntr2_val;
218};
219
220#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
221#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
222#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
223#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
224#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
225#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
226#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
227#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
228#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
229#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
230#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
231#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
232#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
233#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
234#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
235#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
236#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
237#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
238/* Register template: sdr::ctrlgrp::dramtiming1 */
239#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
240#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
241#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
242#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
243#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
244#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
245#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
246#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
247#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
248#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
249#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
250#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
251/* Register template: sdr::ctrlgrp::dramtiming2 */
252#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
253#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
254#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
255#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
256#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
257#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
258#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
259#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
260#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
261#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
262/* Register template: sdr::ctrlgrp::dramtiming3 */
263#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
264#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
265#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
266#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
267#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
268#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
269#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
270#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
271#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
272#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
273/* Register template: sdr::ctrlgrp::dramtiming4 */
274#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
275#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
276#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
277#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
278#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
279#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
280/* Register template: sdr::ctrlgrp::lowpwrtiming */
281#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
282#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
283#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
284#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
285/* Register template: sdr::ctrlgrp::dramaddrw */
286#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
287#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
288#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
289#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
290#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
291#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
292#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
293#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
294/* Register template: sdr::ctrlgrp::dramifwidth */
295#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
296#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
297/* Register template: sdr::ctrlgrp::dramdevwidth */
298#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
299#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
300/* Register template: sdr::ctrlgrp::dramintr */
301#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
302#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
303#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
304#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
305/* Register template: sdr::ctrlgrp::staticcfg */
306#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
307#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
308#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
309#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
310#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
311#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
312/* Register template: sdr::ctrlgrp::ctrlwidth */
313#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
314#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
315/* Register template: sdr::ctrlgrp::cportwidth */
316#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
317#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
318/* Register template: sdr::ctrlgrp::cportwmap */
319#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
320#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
321/* Register template: sdr::ctrlgrp::cportrmap */
322#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
323#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
324/* Register template: sdr::ctrlgrp::rfifocmap */
325#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
326#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
327/* Register template: sdr::ctrlgrp::wfifocmap */
328#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
329#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
330/* Register template: sdr::ctrlgrp::cportrdwr */
331#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
332#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
333/* Register template: sdr::ctrlgrp::portcfg */
334#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
335#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
336#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
337#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
338/* Register template: sdr::ctrlgrp::fifocfg */
339#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
340#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
341#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
342#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
343/* Register template: sdr::ctrlgrp::mppriority */
344#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
345#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
346/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
347#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
348#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
349/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
350#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
351#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
352#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
353#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
354/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
355#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
356#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
357/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
358#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
359#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
360/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
361#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
362#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
363/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
364#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
365#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
366#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
367#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
368/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
369#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
370#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
371/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
372#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
373#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
374/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
375#define \
376SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
377#define \
378SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
3790xffffffff
380/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
381#define \
382SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
383#define \
384SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
3850xffffffff
386/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
387#define \
388SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
389#define \
390SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
3910x0000ffff
392/* Register template: sdr::ctrlgrp::remappriority */
393#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
394#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
395/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
396#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
397#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
398#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
399 (((x) << 12) & 0xfffff000)
400#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
401 (((x) << 10) & 0x00000c00)
402#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
403 (((x) << 6) & 0x000000c0)
404#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
405 (((x) << 8) & 0x00000100)
406#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
407 (((x) << 9) & 0x00000200)
408#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
409 (((x) << 4) & 0x00000030)
410#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
411 (((x) << 2) & 0x0000000c)
412#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
413 (((x) << 0) & 0x00000003)
414/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
415#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
416#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
417 (((x) << 12) & 0xfffff000)
418#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
419 (((x) << 0) & 0x00000fff)
420/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
421#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
422 (((x) << 0) & 0x00000fff)
423/* Register template: sdr::ctrlgrp::dramodt */
424#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
425#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
426#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
427#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
428/* Field instance: sdr::ctrlgrp::dramsts */
429#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
430#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
431/* Register template: sdr::ctrlgrp::extratime1 */
432#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
433#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
434#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
435
436/* SDRAM width macro for configuration with ECC */
437#define SDRAM_WIDTH_32BIT_WITH_ECC 40
438#define SDRAM_WIDTH_16BIT_WITH_ECC 24
439
440#endif
441#endif /* _SOCFPGA_SDRAM_GEN5_H_ */