wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Startup Code for S3C44B0 CPU-core |
| 3 | * |
| 4 | * (C) Copyright 2004 |
| 5 | * DAVE Srl |
| 6 | * |
| 7 | * http://www.dave-tech.it |
| 8 | * http://www.wawnet.biz |
| 9 | * mailto:info@wawnet.biz |
| 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | */ |
| 29 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 30 | #include <asm-offsets.h> |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 31 | #include <config.h> |
| 32 | #include <version.h> |
| 33 | |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 34 | /* |
| 35 | * Jump vector table |
| 36 | */ |
| 37 | |
| 38 | |
| 39 | .globl _start |
| 40 | _start: b reset |
| 41 | add pc, pc, #0x0c000000 |
| 42 | add pc, pc, #0x0c000000 |
| 43 | add pc, pc, #0x0c000000 |
| 44 | add pc, pc, #0x0c000000 |
| 45 | add pc, pc, #0x0c000000 |
| 46 | add pc, pc, #0x0c000000 |
| 47 | add pc, pc, #0x0c000000 |
| 48 | |
| 49 | .balignl 16,0xdeadbeef |
| 50 | |
| 51 | |
| 52 | /* |
| 53 | ************************************************************************* |
| 54 | * |
| 55 | * Startup Code (reset vector) |
| 56 | * |
| 57 | * do important init only if we don't start from memory! |
| 58 | * relocate u-boot to ram |
| 59 | * setup stack |
| 60 | * jump to second stage |
| 61 | * |
| 62 | ************************************************************************* |
| 63 | */ |
| 64 | |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 65 | .globl _TEXT_BASE |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 66 | _TEXT_BASE: |
Benoît Thébaudeau | a402da3 | 2013-04-11 09:35:42 +0000 | [diff] [blame] | 67 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) |
| 68 | .word CONFIG_SPL_TEXT_BASE |
| 69 | #else |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 70 | .word CONFIG_SYS_TEXT_BASE |
Benoît Thébaudeau | a402da3 | 2013-04-11 09:35:42 +0000 | [diff] [blame] | 71 | #endif |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 72 | |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 73 | /* |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 74 | * These are defined in the board-specific linker script. |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 75 | * Subtracting _start from them lets the linker put their |
| 76 | * relative position in the executable instead of leaving |
| 77 | * them null. |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 78 | */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 79 | .globl _bss_start_ofs |
| 80 | _bss_start_ofs: |
| 81 | .word __bss_start - _start |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 82 | |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 83 | .globl _bss_end_ofs |
| 84 | _bss_end_ofs: |
Simon Glass | ed70c8f | 2013-03-14 06:54:53 +0000 | [diff] [blame] | 85 | .word __bss_end - _start |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 86 | |
Po-Yu Chuang | 1864b00 | 2011-03-01 23:02:04 +0000 | [diff] [blame] | 87 | .globl _end_ofs |
| 88 | _end_ofs: |
| 89 | .word _end - _start |
| 90 | |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 91 | #ifdef CONFIG_USE_IRQ |
| 92 | /* IRQ stack memory (calculated at run-time) */ |
| 93 | .globl IRQ_STACK_START |
| 94 | IRQ_STACK_START: |
| 95 | .word 0x0badc0de |
| 96 | |
| 97 | /* IRQ stack memory (calculated at run-time) */ |
| 98 | .globl FIQ_STACK_START |
| 99 | FIQ_STACK_START: |
| 100 | .word 0x0badc0de |
| 101 | #endif |
| 102 | |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 103 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ |
| 104 | .globl IRQ_STACK_START_IN |
| 105 | IRQ_STACK_START_IN: |
| 106 | .word 0x0badc0de |
| 107 | |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 108 | /* |
| 109 | * the actual reset code |
| 110 | */ |
| 111 | |
| 112 | reset: |
| 113 | /* |
| 114 | * set the cpu to SVC32 mode |
| 115 | */ |
| 116 | mrs r0,cpsr |
| 117 | bic r0,r0,#0x1f |
| 118 | orr r0,r0,#0xd3 |
| 119 | msr cpsr,r0 |
| 120 | |
| 121 | /* |
| 122 | * we do sys-critical inits only at reboot, |
| 123 | * not when booting from ram! |
| 124 | */ |
| 125 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 126 | bl cpu_init_crit |
| 127 | /* |
| 128 | * before relocating, we have to setup RAM timing |
| 129 | * because memory timing is board-dependend, you will |
| 130 | * find a lowlevel_init.S in your board directory. |
| 131 | */ |
| 132 | bl lowlevel_init |
| 133 | #endif |
| 134 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 135 | bl _main |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 136 | |
| 137 | /*------------------------------------------------------------------------------*/ |
| 138 | |
| 139 | /* |
| 140 | * void relocate_code (addr_sp, gd, addr_moni) |
| 141 | * |
Benoît Thébaudeau | 9039c10 | 2013-04-11 09:35:43 +0000 | [diff] [blame] | 142 | * This function relocates the monitor code. |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 143 | */ |
| 144 | .globl relocate_code |
| 145 | relocate_code: |
| 146 | mov r4, r0 /* save addr_sp */ |
| 147 | mov r5, r1 /* save addr of gd */ |
| 148 | mov r6, r2 /* save addr of destination */ |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 149 | |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 150 | adr r0, _start |
Benoît Thébaudeau | a18f323 | 2013-04-11 09:35:45 +0000 | [diff] [blame^] | 151 | subs r9, r6, r0 /* r9 <- relocation offset */ |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 152 | beq relocate_done /* skip relocation */ |
Andreas Bießmann | 8cfbda9 | 2010-12-01 00:58:33 +0100 | [diff] [blame] | 153 | mov r1, r6 /* r1 <- scratch for copy_loop */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 154 | ldr r3, _bss_start_ofs |
| 155 | add r2, r0, r3 /* r2 <- source end address */ |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 156 | |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 157 | copy_loop: |
Benoît Thébaudeau | a18f323 | 2013-04-11 09:35:45 +0000 | [diff] [blame^] | 158 | ldmia r0!, {r10-r11} /* copy from source address [r0] */ |
| 159 | stmia r1!, {r10-r11} /* copy to target address [r1] */ |
Albert Aribaud | 0668d16 | 2010-10-05 16:06:39 +0200 | [diff] [blame] | 160 | cmp r0, r2 /* until source end address [r2] */ |
| 161 | blo copy_loop |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 162 | |
Aneesh V | 552a319 | 2011-07-13 05:11:07 +0000 | [diff] [blame] | 163 | #ifndef CONFIG_SPL_BUILD |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 164 | /* |
| 165 | * fix .rel.dyn relocations |
| 166 | */ |
| 167 | ldr r0, _TEXT_BASE /* r0 <- Text base */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 168 | ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ |
| 169 | add r10, r10, r0 /* r10 <- sym table in FLASH */ |
| 170 | ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ |
| 171 | add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ |
| 172 | ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ |
| 173 | add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 174 | fixloop: |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 175 | ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ |
| 176 | add r0, r0, r9 /* r0 <- location to fix up in RAM */ |
| 177 | ldr r1, [r2, #4] |
Andreas Bießmann | 318cea1 | 2010-12-01 00:58:35 +0100 | [diff] [blame] | 178 | and r7, r1, #0xff |
| 179 | cmp r7, #23 /* relative fixup? */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 180 | beq fixrel |
Andreas Bießmann | 318cea1 | 2010-12-01 00:58:35 +0100 | [diff] [blame] | 181 | cmp r7, #2 /* absolute fixup? */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 182 | beq fixabs |
| 183 | /* ignore unknown type of fixup */ |
| 184 | b fixnext |
| 185 | fixabs: |
| 186 | /* absolute fix: set location to (offset) symbol value */ |
| 187 | mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ |
| 188 | add r1, r10, r1 /* r1 <- address of symbol in table */ |
| 189 | ldr r1, [r1, #4] /* r1 <- symbol value */ |
Wolfgang Denk | 899cdd1 | 2010-12-09 11:26:24 +0100 | [diff] [blame] | 190 | add r1, r1, r9 /* r1 <- relocated sym addr */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 191 | b fixnext |
| 192 | fixrel: |
| 193 | /* relative fix: increase location by offset */ |
| 194 | ldr r1, [r0] |
| 195 | add r1, r1, r9 |
| 196 | fixnext: |
| 197 | str r1, [r0] |
| 198 | add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 199 | cmp r2, r3 |
Wolfgang Denk | 98dd07c | 2010-10-23 23:22:38 +0200 | [diff] [blame] | 200 | blo fixloop |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 201 | #endif |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 202 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 203 | relocate_done: |
Heiko Schocher | 296c3ee | 2010-09-17 13:10:49 +0200 | [diff] [blame] | 204 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 205 | bx lr |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 206 | |
| 207 | _rel_dyn_start_ofs: |
| 208 | .word __rel_dyn_start - _start |
| 209 | _rel_dyn_end_ofs: |
| 210 | .word __rel_dyn_end - _start |
| 211 | _dynsym_start_ofs: |
| 212 | .word __dynsym_start - _start |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 213 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 214 | .globl c_runtime_cpu_setup |
| 215 | c_runtime_cpu_setup: |
| 216 | |
| 217 | bx lr |
| 218 | |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 219 | /* |
| 220 | ************************************************************************* |
| 221 | * |
| 222 | * CPU_init_critical registers |
| 223 | * |
| 224 | * setup important registers |
| 225 | * setup memory timing |
| 226 | * |
| 227 | ************************************************************************* |
| 228 | */ |
| 229 | |
| 230 | #define INTCON (0x01c00000+0x200000) |
| 231 | #define INTMSK (0x01c00000+0x20000c) |
| 232 | #define LOCKTIME (0x01c00000+0x18000c) |
| 233 | #define PLLCON (0x01c00000+0x180000) |
| 234 | #define CLKCON (0x01c00000+0x180004) |
| 235 | #define WTCON (0x01c00000+0x130000) |
| 236 | cpu_init_crit: |
| 237 | /* disable watch dog */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 238 | ldr r0, =WTCON |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 239 | ldr r1, =0x0 |
| 240 | str r1, [r0] |
| 241 | |
| 242 | /* |
| 243 | * mask all IRQs by clearing all bits in the INTMRs |
| 244 | */ |
| 245 | ldr r1,=INTMSK |
| 246 | ldr r0, =0x03fffeff |
| 247 | str r0, [r1] |
| 248 | |
| 249 | ldr r1, =INTCON |
| 250 | ldr r0, =0x05 |
| 251 | str r0, [r1] |
| 252 | |
| 253 | /* Set Clock Control Register */ |
| 254 | ldr r1, =LOCKTIME |
| 255 | ldrb r0, =800 |
| 256 | strb r0, [r1] |
| 257 | |
| 258 | ldr r1, =PLLCON |
| 259 | |
| 260 | #if CONFIG_S3C44B0_CLOCK_SPEED==66 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 261 | ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ |
wdenk | b98ac28 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 262 | #elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
| 263 | ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ |
| 264 | #else |
| 265 | # error CONFIG_S3C44B0_CLOCK_SPEED undefined |
| 266 | #endif |
| 267 | |
| 268 | str r0, [r1] |
| 269 | |
| 270 | ldr r1,=CLKCON |
| 271 | ldr r0, =0x7ff8 |
| 272 | str r0, [r1] |
| 273 | |
| 274 | mov pc, lr |
| 275 | |
| 276 | |
| 277 | /*************************************************/ |
| 278 | /* interrupt vectors */ |
| 279 | /*************************************************/ |
| 280 | real_vectors: |
| 281 | b reset |
| 282 | b undefined_instruction |
| 283 | b software_interrupt |
| 284 | b prefetch_abort |
| 285 | b data_abort |
| 286 | b not_used |
| 287 | b irq |
| 288 | b fiq |
| 289 | |
| 290 | /*************************************************/ |
| 291 | |
| 292 | undefined_instruction: |
| 293 | mov r6, #3 |
| 294 | b reset |
| 295 | |
| 296 | software_interrupt: |
| 297 | mov r6, #4 |
| 298 | b reset |
| 299 | |
| 300 | prefetch_abort: |
| 301 | mov r6, #5 |
| 302 | b reset |
| 303 | |
| 304 | data_abort: |
| 305 | mov r6, #6 |
| 306 | b reset |
| 307 | |
| 308 | not_used: |
| 309 | /* we *should* never reach this */ |
| 310 | mov r6, #7 |
| 311 | b reset |
| 312 | |
| 313 | irq: |
| 314 | mov r6, #8 |
| 315 | b reset |
| 316 | |
| 317 | fiq: |
| 318 | mov r6, #9 |
| 319 | b reset |