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git01.mediatek.com / filogic / uboot / 03836942b412415379651f656e7d33fe02e408de / . / board / amcc / redwood / init.S
blob: 363d7932aca1357af25d8ad6f67f5942c45fd60b [file] [log] [blame]
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <ppc_asm.tmpl>
25#include <config.h>
26#include <asm-ppc/mmu.h>
27
28/**************************************************************************
29 * TLB TABLE
30 *
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
34 *
35 * Pointer to the table is returned in r1
36 *
37 *************************************************************************/
38
39 .section .bootpg,"ax"
40 .globl tlbtab
41tlbtab:
42 tlbtab_start
43
44 /*
45 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
46 * speed up boot process. It is patched after relocation to enable SA_I
47 */
48 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
49
50 /*
51 * TLB entries for SDRAM are not needed on this platform.
52 * They are dynamically generated in the SPD DDR(2) detection
53 * routine.
54 */
55
56 /* Although 512 KB, map 256k at a time */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]57 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
58 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]59
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]60 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]61
62 /*
63 * Peripheral base
64 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]65 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]66
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]67 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
68 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]70
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]71 tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
72 tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame^]74 tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
75 tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
76 tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]77 tlbtab_end