| Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 1 | Work_92105 from Work Microwave is an LPC3250- based board with the |
| 2 | following features: |
| 3 | |
| 4 | - 64MB SDR DRAM |
| 5 | - 1 GB SLC NAND, managed through MLC controller. |
| 6 | - Ethernet |
| 7 | - Ethernet + PHY SMSC8710 |
| 8 | - I2C: |
| 9 | - EEPROM (24M01-compatible) |
| 10 | - RTC (DS1374-compatible) |
| 11 | - Temperature sensor (DS620) |
| 12 | - DACs (2 x MAX518) |
| 13 | - SPI (through SSP interface) |
| 14 | - Port expander MAX6957 |
| 15 | - LCD display (HD44780-compatible), controlled |
| 16 | through the port expander and DACs |
| 17 | |
| 18 | Standard SPL and U-Boot binaries |
| 19 | -------------------------------- |
| 20 | |
| 21 | The default 'make' (or the 'make all') command will produce the |
| 22 | following files: |
| 23 | |
| 24 | 1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0. |
| 25 | This file can be loaded in SRAM through a JTAG |
| 26 | debugger or through the LPC32XX Service Boot |
| 27 | mechanism. |
| 28 | |
| 29 | 2. u-boot.bin The raw U-Boot image, which can be loaded in |
| 30 | DDR through a JTAG debugger (for instance by |
| 31 | breaking SPL after DDR init), or by a running |
| 32 | U-Boot through e.g. 'loady' or 'tftp' and then |
| 33 | executed with 'go'. |
| 34 | |
| 35 | 3. u-boot.img A U-Boot image with a mkimage header prepended. |
| 36 | SPL assumes (even when loaded through JTAG or |
| 37 | Service Boot) that such an image will be found |
| 38 | at offset 0x00040000 in NAND. |
| 39 | |
| 40 | NAND cold-boot binaries |
| 41 | ----------------------- |
| 42 | |
| 43 | The board can boot entirely from power-on with only SPL and U-Boot in |
| 44 | NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce |
| 45 | (in addition to spl/u-boot-spl.bin and u-boot.img if they were not made |
| 46 | already) the following files: |
| 47 | |
| 48 | 4. lpc32xx-spl.img spl/u-boot-spl.bin, with a LPC32XX boot header |
| 49 | prepended. This header is required for the ROM |
| 50 | code to load SPL into SRAM and branch into it. |
| 51 | The content of this file is expected to reside |
| 52 | in NAND at addresses 0x00000000 and 0x00020000 |
| 53 | (two copies). |
| 54 | |
| 55 | 5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a |
| 56 | size of 0x20000 bytes. This file covers exactly |
| 57 | the reserved area for the first bootloader copy |
| 58 | in NAND. |
| 59 | |
| 60 | 6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to |
| 61 | be used as the second bootloader copy. |
| 62 | |
| 63 | 7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and |
| 64 | u-boot.img concatenated. This file represents |
| 65 | the content of whole bootloader as present in |
| 66 | NAND at offset 00x00000000. |
| 67 | |
| 68 | Flashing instructions |
| 69 | --------------------- |
| 70 | |
| 71 | The following assumes a working U-Boot on the target, with the ability |
| 72 | to load files into DDR. |
| 73 | |
| 74 | To update the whole bootloader: |
| 75 | |
| 76 | nand erase 0x00000000 0x80000 |
| 77 | (load lpc32xx-full.bin at location $loadaddr) |
| 78 | nand write $loadaddr 0x00000000 $filesize |
| 79 | |
| 80 | To update SPL only (note the double nand write) : |
| 81 | |
| 82 | nand erase 0x00000000 0x40000 |
| 83 | (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr) |
| 84 | nand write $loadaddr 0x00000000 $filesize |
| 85 | nand write $loadaddr 0x00020000 $filesize |
| 86 | |
| 87 | To update U-Boot only: |
| 88 | |
| 89 | nand erase 0x00040000 0x40000 |
| 90 | (load u-boot.img at location $loadaddr) |
| 91 | nand write $loadaddr 0x00040000 $filesize |