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git01.mediatek.com / filogic / uboot / 0333e3bb665555163711173cadecbac8046d5105 / . / dts / upstream / src / arm / ti / keystone / keystone-k2g-ice.dts
blob: 6ceb0d5c6388bf4b3d150d39861fad085efe2c20 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for K2G Industrial Communication Engine EVM
4 *
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7/dts-v1/;
8
9#include "keystone-k2g.dtsi"
10#include <dt-bindings/net/ti-dp83867.h>
11
12/ {
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
14 model = "Texas Instruments K2G Industrial Communication EVM";
15
16 memory@800000000 {
17 device_type = "memory";
18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
19 };
20
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
24 ranges;
25
26 dsp_common_memory: dsp-common-memory@81f800000 {
27 compatible = "shared-dma-pool";
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
29 reusable;
30 status = "okay";
31 };
32 };
33
34 vmain: fixedregulator-vmain {
35 compatible = "regulator-fixed";
36 regulator-name = "vmain_fixed";
37 regulator-min-microvolt = <24000000>;
38 regulator-max-microvolt = <24000000>;
39 regulator-always-on;
40 };
41
42 v5_0: fixedregulator-v5_0 {
43 /* TPS54531 */
44 compatible = "regulator-fixed";
45 regulator-name = "v5_0_fixed";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 vin-supply = <&vmain>;
49 regulator-always-on;
50 };
51
52 vdd_3v3: fixedregulator-vdd_3v3 {
53 /* TLV62084 */
54 compatible = "regulator-fixed";
55 regulator-name = "vdd_3v3_fixed";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 vin-supply = <&v5_0>;
59 regulator-always-on;
60 };
61
62 vdd_1v8: fixedregulator-vdd_1v8 {
63 /* TLV62084 */
64 compatible = "regulator-fixed";
65 regulator-name = "vdd_1v8_fixed";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <1800000>;
68 vin-supply = <&v5_0>;
69 regulator-always-on;
70 };
71
72 vdds_ddr: fixedregulator-vdds_ddr {
73 /* TLV62080 */
74 compatible = "regulator-fixed";
75 regulator-name = "vdds_ddr_fixed";
76 regulator-min-microvolt = <1350000>;
77 regulator-max-microvolt = <1350000>;
78 vin-supply = <&v5_0>;
79 regulator-always-on;
80 };
81
82 vref_ddr: fixedregulator-vref_ddr {
83 /* LP2996A */
84 compatible = "regulator-fixed";
85 regulator-name = "vref_ddr_fixed";
86 regulator-min-microvolt = <675000>;
87 regulator-max-microvolt = <675000>;
88 vin-supply = <&vdd_3v3>;
89 regulator-always-on;
90 };
91
92 vtt_ddr: fixedregulator-vtt_ddr {
93 /* LP2996A */
94 compatible = "regulator-fixed";
95 regulator-name = "vtt_ddr_fixed";
96 regulator-min-microvolt = <675000>;
97 regulator-max-microvolt = <675000>;
98 vin-supply = <&vdd_3v3>;
99 regulator-always-on;
100 };
101
102 vdd_0v9: fixedregulator-vdd_0v9 {
103 /* TPS62180 */
104 compatible = "regulator-fixed";
105 regulator-name = "vdd_0v9_fixed";
106 regulator-min-microvolt = <900000>;
107 regulator-max-microvolt = <900000>;
108 vin-supply = <&v5_0>;
109 regulator-always-on;
110 };
111
112 vddb: fixedregulator-vddb {
113 /* TPS22945 */
114 compatible = "regulator-fixed";
115 regulator-name = "vddb_fixed";
116 regulator-min-microvolt = <3300000>;
117 regulator-max-microvolt = <3300000>;
118
119 gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 };
122
123 gpio-decoder {
124 compatible = "gpio-decoder";
125 gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
126 <&pca9536 2 GPIO_ACTIVE_HIGH>,
127 <&pca9536 1 GPIO_ACTIVE_HIGH>,
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
130 decoder-max-value = <9>;
131 };
132
133 leds1 {
134 compatible = "gpio-leds";
135 pinctrl-names = "default";
136 pinctrl-0 = <&user_leds>;
137
138 led0 {
139 label = "status0:red:cpu0";
140 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
141 default-state = "off";
142 linux,default-trigger = "cpu0";
143 };
144
145 led1 {
146 label = "status0:green:usr";
147 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
148 default-state = "off";
149 };
150
151 led2 {
152 label = "status0:yellow:usr";
153 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
154 default-state = "off";
155 };
156
157 led3 {
158 label = "status1:red:mmc0";
159 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
160 default-state = "off";
161 linux,default-trigger = "mmc0";
162 };
163
164 led4 {
165 label = "status1:green:usr";
166 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
167 default-state = "off";
168 };
169
170 led5 {
171 label = "status1:yellow:usr";
172 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
173 default-state = "off";
174 };
175
176 led6 {
177 label = "status2:red:usr";
178 gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>;
179 default-state = "off";
180 };
181
182 led7 {
183 label = "status2:green:usr";
184 gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
185 default-state = "off";
186 };
187
188 led8 {
189 label = "status2:yellow:usr";
190 gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>;
191 default-state = "off";
192 };
193
194 led9 {
195 label = "status3:red:usr";
196 gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>;
197 default-state = "off";
198 };
199
200 led10 {
201 label = "status3:green:usr";
202 gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>;
203 default-state = "off";
204 };
205
206 led11 {
207 label = "status3:yellow:usr";
208 gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>;
209 default-state = "off";
210 };
211
212 led12 {
213 label = "status4:green:heartbeat";
214 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
215 linux,default-trigger = "heartbeat";
216 };
217 };
218};
219
220&k2g_pinctrl {
221 uart0_pins: uart0-pins {
222 pinctrl-single,pins = <
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
225 >;
226 };
227
228 qspi_pins: qspi-pins {
229 pinctrl-single,pins = <
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
233 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
234 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
235 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
236 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
237 >;
238 };
239
240 mmc1_pins: mmc1-pins {
241 pinctrl-single,pins = <
242 K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
243 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
244 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
245 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
246 K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
247 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
248 K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */
249 K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */
250 K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */
251 >;
252 };
253
254 i2c0_pins: i2c0-pins {
255 pinctrl-single,pins = <
256 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
257 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
258 >;
259 };
260
261 i2c1_pins: i2c1-pins {
262 pinctrl-single,pins = <
263 K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
264 K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
265 >;
266 };
267
268 user_leds: user-leds-pins {
269 pinctrl-single,pins = <
270 K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */
271 K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */
272 K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */
273 K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */
274 K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */
275 K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */
276 K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */
277 K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */
278 K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */
279 K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */
280 K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */
281 K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */
282 K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */
283 >;
284 };
285
286 emac_pins: emac-pins {
287 pinctrl-single,pins = <
288 K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
289 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
290 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
291 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
292 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
293 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
294 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
295 K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
296 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
297 K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
298 K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
299 K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
300 >;
301 };
302
303 mdio_pins: mdio-pins {
304 pinctrl-single,pins = <
305 K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
306 K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
307 >;
308 };
309};
310
311&uart0 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&uart0_pins>;
314 status = "okay";
315};
316
317&dsp0 {
318 memory-region = <&dsp_common_memory>;
319 status = "okay";
320};
321
322&qspi {
323 pinctrl-names = "default";
324 pinctrl-0 = <&qspi_pins>;
325 cdns,rclk-en;
326 status = "okay";
327
328 flash0: flash@0 {
329 compatible = "s25fl256s1", "jedec,spi-nor";
330 reg = <0>;
331 spi-tx-bus-width = <1>;
332 spi-rx-bus-width = <4>;
333 spi-max-frequency = <96000000>;
334 #address-cells = <1>;
335 #size-cells = <1>;
336 cdns,read-delay = <5>;
337 cdns,tshsl-ns = <500>;
338 cdns,tsd2d-ns = <500>;
339 cdns,tchsh-ns = <119>;
340 cdns,tslch-ns = <119>;
341
342 partition@0 {
343 label = "QSPI.u-boot";
344 reg = <0x00000000 0x00100000>;
345 };
346 partition@1 {
347 label = "QSPI.u-boot-env";
348 reg = <0x00100000 0x00040000>;
349 };
350 partition@2 {
351 label = "QSPI.skern";
352 reg = <0x00140000 0x0040000>;
353 };
354 partition@3 {
355 label = "QSPI.pmmc-firmware";
356 reg = <0x00180000 0x0040000>;
357 };
358 partition@4 {
359 label = "QSPI.kernel";
360 reg = <0x001c0000 0x0800000>;
361 };
362 partition@5 {
363 label = "QSPI.u-boot-spl-os";
364 reg = <0x009c0000 0x0040000>;
365 };
366 partition@6 {
367 label = "QSPI.file-system";
368 reg = <0x00a00000 0x1600000>;
369 };
370 };
371};
372
373&gpio0 {
374 status = "okay";
375};
376
377&gpio1 {
378 status = "okay";
379};
380
381&mmc1 {
382 pinctrl-names = "default";
383 pinctrl-0 = <&mmc1_pins>;
384 vmmc-supply = <&vdd_3v3>;
385 cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>;
386 status = "okay";
387};
388
389&i2c0 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c0_pins>;
392 status = "okay";
393
394 eeprom@50 {
395 compatible = "atmel,24c256";
396 reg = <0x50>;
397 };
398};
399
400&i2c1 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c1_pins>;
403 status = "okay";
404 clock-frequency = <400000>;
405
406 pca9536: gpio@41 {
407 compatible = "ti,pca9536";
408 reg = <0x41>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 vcc-supply = <&vdd_3v3>;
412 };
413};
414
415&qmss {
416 status = "okay";
417};
418
419&knav_dmas {
420 status = "okay";
421};
422
423&netcp {
424 pinctrl-names = "default";
425 pinctrl-0 = <&emac_pins>;
426 status = "okay";
427};
428
429&mdio {
430 pinctrl-names = "default";
431 pinctrl-0 = <&mdio_pins>;
432 status = "okay";
433 ethphy0: ethernet-phy@0 {
434 reg = <0>;
435 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
436 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
437 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
438 ti,min-output-impedance;
439 ti,dp83867-rxctrl-strap-quirk;
440 };
441};
442
443&gbe0 {
444 phy-handle = <&ethphy0>;
445 phy-mode = "rgmii-id";
446 status = "okay";
447};