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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop0bf5cad2008-05-08 18:52:25 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9RLEK board.
Stelian Pop0bf5cad2008-05-08 18:52:25 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Xu, Hong0c0fb212011-08-01 03:56:53 +000013#include <asm/hardware.h>
14
Stelian Pop0bf5cad2008-05-08 18:52:25 +020015/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +000016#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
17#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020018
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020019#define CONFIG_ARCH_CPU_INIT
Xu, Hong0c0fb212011-08-01 03:56:53 +000020#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Pop0bf5cad2008-05-08 18:52:25 +020021
Xu, Hong0c0fb212011-08-01 03:56:53 +000022#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS 1
24#define CONFIG_INITRD_TAG 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020025
Xu, Hong0c0fb212011-08-01 03:56:53 +000026#define CONFIG_ATMEL_LEGACY
Stelian Pop0bf5cad2008-05-08 18:52:25 +020027
28/*
29 * Hardware drivers
30 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000031
Stelian Popcea5c532008-05-08 14:52:32 +020032/* LCD */
Stelian Popcea5c532008-05-08 14:52:32 +020033#define LCD_BPP LCD_COLOR8
34#define CONFIG_LCD_LOGO 1
35#undef LCD_TEST_PATTERN
36#define CONFIG_LCD_INFO 1
37#define CONFIG_LCD_INFO_BELOW_LOGO 1
Stelian Popcea5c532008-05-08 14:52:32 +020038#define CONFIG_ATMEL_LCD 1
39#define CONFIG_ATMEL_LCD_RGB565 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000040/* Let board_init_f handle the framebuffer allocation */
41#undef CONFIG_FB_ADDR
Xu, Hong0c0fb212011-08-01 03:56:53 +000042
Stelian Pop0bf5cad2008-05-08 18:52:25 +020043/* SDRAM */
44#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000045#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
46#define CONFIG_SYS_SDRAM_SIZE 0x04000000
47
48#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang3cbbeb12017-04-18 15:28:27 +080049 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +020050
Stelian Pop0bf5cad2008-05-08 18:52:25 +020051/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010052#ifdef CONFIG_CMD_NAND
53#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000055#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010057/* our ALE is AD21 */
58#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
59/* our CLE is AD22 */
60#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
61#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
62#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +020063
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010064#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +020065
66/* Ethernet - not present */
67
68/* USB - not supported */
69
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020071
Xu, Hong0c0fb212011-08-01 03:56:53 +000072#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop0bf5cad2008-05-08 18:52:25 +020074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +020076
77/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +080078#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020079#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +080080#define CONFIG_ENV_SECT_SIZE 0x210
81#define CONFIG_ENV_SPI_MAX_HZ 15000000
82#define CONFIG_BOOTCOMMAND "sf probe 0; " \
83 "sf read 0x22000000 0x84000 0x294000; " \
84 "bootm 0x22000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +020085
Wu, Josh7ff194f2015-02-02 17:51:01 +080086#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +020087
88/* bootstrap + u-boot + env + linux in nandflash */
Nicolas Ferre64922442018-05-09 10:30:25 +030089#define CONFIG_ENV_OFFSET 0x140000
Wu, Joshf8e70d92015-02-03 11:38:30 +080090#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020091#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Wu, Joshf8e70d92015-02-03 11:38:30 +080092#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \
93 "nand read 0x21000000 0x180000 0x80000; " \
94 "bootz 0x22000000 - 0x21000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +020095
Wu, Josh7ff194f2015-02-02 17:51:01 +080096#else /* CONFIG_SYS_USE_MMC */
97
98/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh7ff194f2015-02-02 17:51:01 +080099#define CONFIG_ENV_SIZE 0x4000
100#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
101 "fatload mmc 0:1 0x22000000 zImage; " \
102 "bootz 0x22000000 - 0x21000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200103#endif
104
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200105/*
106 * Size of malloc() pool
107 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000108#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200109
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200110#endif