Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 030672130b78d4606aa4517dda5bdd6ae52bc0ee / . / configs / rock_defconfig
blob: ac533d5985a60892cab502ea58d7b940c0260dcd [file] [log] [blame]
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]1CONFIG_ARM=y
2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
3# CONFIG_SPL_USE_ARCH_MEMSET is not set
4CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]5CONFIG_SYS_TEXT_BASE=0x60000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]6CONFIG_SYS_MALLOC_F_LEN=0x2000
7CONFIG_ROCKCHIP_RK3188=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]8CONFIG_TARGET_ROCK=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
10CONFIG_SPL_STACK_R_ADDR=0x60080000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_DEBUG_UART_BASE=0x20064000
12CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]14CONFIG_SPL_TEXT_BASE=0x10080800
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]15CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]16CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]17# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]18CONFIG_DISPLAY_BOARDINFO_LATE=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]19CONFIG_SPL_STACK_R=y
20CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Maxime Ripard24336442017-08-24 11:52:32 +0200[diff] [blame]21CONFIG_RANDOM_UUID=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]22CONFIG_CMD_I2C=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]23CONFIG_CMD_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]24CONFIG_CMD_SPI=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]25# CONFIG_CMD_SETEXPR is not set
26CONFIG_CMD_CACHE=y
27CONFIG_CMD_TIME=y
28CONFIG_CMD_REGULATOR=y
29CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]30CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]31CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
32CONFIG_SPL_OF_PLATDATA=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]33CONFIG_ENV_IS_IN_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]34CONFIG_REGMAP=y
35CONFIG_SYSCON=y
36# CONFIG_SPL_SIMPLE_BUS is not set
37CONFIG_CLK=y
38CONFIG_ROCKCHIP_GPIO=y
39CONFIG_SYS_I2C_ROCKCHIP=y
40CONFIG_LED=y
41CONFIG_MMC_DW=y
42CONFIG_MMC_DW_ROCKCHIP=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]43CONFIG_SF_DEFAULT_SPEED=20000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]44CONFIG_PINCTRL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]45CONFIG_DM_PMIC=y
46# CONFIG_SPL_PMIC_CHILDREN is not set
47CONFIG_PMIC_ACT8846=y
48CONFIG_REGULATOR_ACT8846=y
49CONFIG_DM_REGULATOR_FIXED=y
50CONFIG_RAM=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]51CONFIG_DEBUG_UART_SHIFT=2
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]52CONFIG_SYSRESET=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]53CONFIG_TIMER=y
54CONFIG_SPL_TIMER=y
55CONFIG_ROCKCHIP_TIMER=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]56CONFIG_USB=y
57CONFIG_ROCKCHIP_USB2_PHY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]58CONFIG_SPL_TINY_MEMSET=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]59CONFIG_CMD_DHRYSTONE=y
60CONFIG_ERRNO_STR=y