Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the SAMA5D3xEK board. |
| 3 | * |
| 4 | * Copyright (C) 2012 - 2013 Atmel |
| 5 | * |
| 6 | * based on at91sam9m10g45ek.h by: |
| 7 | * Stelian Pop <stelian@popies.net> |
| 8 | * Lead Tech Design <www.leadtechdesign.com> |
| 9 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
Wu, Josh | 4258754 | 2015-03-30 14:51:19 +0800 | [diff] [blame] | 16 | #include "at91-sama5_common.h" |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 17 | |
Wu, Josh | 3c0c660 | 2015-08-19 19:11:19 +0800 | [diff] [blame] | 18 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 19 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 20 | /* |
| 21 | * This needs to be defined for the OHCI code to work but it is defined as |
| 22 | * ATMEL_ID_UHPHS in the CPU specific header files. |
| 23 | */ |
| 24 | #define ATMEL_ID_UHP ATMEL_ID_UHPHS |
| 25 | |
| 26 | /* |
| 27 | * Specify the clock enable bit in the PMC_SCER register. |
| 28 | */ |
| 29 | #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP |
| 30 | |
| 31 | /* LCD */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 32 | #define LCD_BPP LCD_COLOR16 |
| 33 | #define LCD_OUTPUT_BPP 24 |
| 34 | #define CONFIG_LCD_LOGO |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 35 | #define CONFIG_LCD_INFO |
| 36 | #define CONFIG_LCD_INFO_BELOW_LOGO |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 37 | #define CONFIG_ATMEL_HLCD |
| 38 | #define CONFIG_ATMEL_LCD_RGB565 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 39 | |
| 40 | /* board specific (not enough SRAM) */ |
| 41 | #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 |
| 42 | |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 43 | /* NOR flash */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 44 | #ifdef CONFIG_MTD_NOR_FLASH |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 45 | #define CONFIG_FLASH_CFI_DRIVER |
| 46 | #define CONFIG_SYS_FLASH_CFI |
| 47 | #define CONFIG_SYS_FLASH_PROTECTION |
| 48 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
| 49 | #define CONFIG_SYS_MAX_FLASH_SECT 131 |
| 50 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 51 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 52 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 53 | /* SDRAM */ |
| 54 | #define CONFIG_NR_DRAM_BANKS 1 |
| 55 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS |
| 56 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 |
| 57 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 58 | #ifdef CONFIG_SPL_BUILD |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 59 | #define CONFIG_SYS_INIT_SP_ADDR 0x318000 |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 60 | #else |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 61 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 62 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 63 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 64 | |
| 65 | /* SerialFlash */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 66 | |
| 67 | #ifdef CONFIG_CMD_SF |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 68 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
| 69 | #endif |
| 70 | |
| 71 | /* NAND flash */ |
| 72 | #define CONFIG_CMD_NAND |
| 73 | |
| 74 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 75 | #define CONFIG_NAND_ATMEL |
| 76 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 77 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 78 | /* our ALE is AD21 */ |
| 79 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 80 | /* our CLE is AD22 */ |
| 81 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 82 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 83 | /* PMECC & PMERRLOC */ |
| 84 | #define CONFIG_ATMEL_NAND_HWECC |
| 85 | #define CONFIG_ATMEL_NAND_HW_PMECC |
| 86 | #define CONFIG_PMECC_CAP 4 |
| 87 | #define CONFIG_PMECC_SECTOR_SIZE 512 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 88 | #define CONFIG_CMD_NAND_TRIMFFS |
| 89 | #endif |
| 90 | |
Bo Shen | 6f6afad | 2013-06-26 10:11:06 +0800 | [diff] [blame] | 91 | #define CONFIG_PHY_MICREL_KSZ9021 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 92 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 93 | /* USB */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 94 | |
| 95 | #ifdef CONFIG_CMD_USB |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 96 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 97 | #define CONFIG_USB_OHCI_NEW |
| 98 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 99 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI |
| 100 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" |
| 101 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 102 | #endif |
| 103 | |
| 104 | #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) |
Wu, Josh | a3dd08e | 2015-01-20 10:33:32 +0800 | [diff] [blame] | 105 | #define CONFIG_FAT_WRITE |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 106 | #endif |
| 107 | |
| 108 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 109 | |
| 110 | #ifdef CONFIG_SYS_USE_SERIALFLASH |
Wu, Josh | 12e8441 | 2015-08-19 19:11:21 +0800 | [diff] [blame] | 111 | /* override the bootcmd, bootargs and other configuration for spi flash env*/ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 112 | #elif CONFIG_SYS_USE_NANDFLASH |
Wu, Josh | 244caf0 | 2015-08-19 19:11:20 +0800 | [diff] [blame] | 113 | /* override the bootcmd, bootargs and other configuration nandflash env */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 114 | #elif CONFIG_SYS_USE_MMC |
Wu, Josh | 8b9c751 | 2015-08-19 19:11:18 +0800 | [diff] [blame] | 115 | /* override the bootcmd, bootargs and other configuration for sd/mmc env */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 116 | #else |
Bo Shen | adaa136 | 2013-08-11 14:26:20 +0000 | [diff] [blame] | 117 | #define CONFIG_ENV_IS_NOWHERE |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 118 | #endif |
| 119 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 120 | /* SPL */ |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 121 | #define CONFIG_SPL_FRAMEWORK |
| 122 | #define CONFIG_SPL_TEXT_BASE 0x300000 |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 123 | #define CONFIG_SPL_MAX_SIZE 0x18000 |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 124 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 125 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 126 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 127 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 128 | |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 129 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 130 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 131 | #ifdef CONFIG_SYS_USE_MMC |
Bo Shen | 83a718d | 2015-03-04 13:32:57 +0800 | [diff] [blame] | 132 | #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds |
Paul Kocialkowski | 341e8cd | 2014-11-08 23:14:55 +0100 | [diff] [blame] | 133 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 134 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 135 | |
Bo Shen | 540c031 | 2014-03-03 14:47:17 +0800 | [diff] [blame] | 136 | #elif CONFIG_SYS_USE_NANDFLASH |
Bo Shen | 540c031 | 2014-03-03 14:47:17 +0800 | [diff] [blame] | 137 | #define CONFIG_SPL_NAND_DRIVERS |
| 138 | #define CONFIG_SPL_NAND_BASE |
| 139 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
| 140 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 141 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
| 142 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 143 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 144 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
| 145 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
Andreas Bießmann | f52c019 | 2014-05-19 14:23:41 +0200 | [diff] [blame] | 146 | #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER |
Bo Shen | 540c031 | 2014-03-03 14:47:17 +0800 | [diff] [blame] | 147 | |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 148 | #elif CONFIG_SYS_USE_SERIALFLASH |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 149 | #define CONFIG_SPL_SPI_LOAD |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 150 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 151 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 152 | #endif |
| 153 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 154 | #endif |