| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _X86_ARCH_TNC_H_ |
| 8 | #define _X86_ARCH_TNC_H_ |
| 9 | |
| Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 10 | /* IGD Control Register */ |
| 11 | #define IGD_GC 0x50 |
| 12 | #define VGA_DISABLE 0x00020000 |
| 13 | #define GMS_MASK 0x00700000 |
| 14 | |
| Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 15 | /* Memory BAR Enable */ |
| 16 | #define MEM_BAR_EN 0x00000001 |
| 17 | |
| 18 | /* LPC PCI Configuration Registers */ |
| 19 | #define LPC_RCBA 0xf0 |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 20 | |
| Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 21 | /* Root Complex Register Block */ |
| 22 | struct tnc_rcba { |
| 23 | u32 rctl; |
| 24 | u32 esd; |
| 25 | u32 rsvd1[2]; |
| 26 | u32 hdd; |
| 27 | u32 rsvd2; |
| 28 | u32 hdba; |
| 29 | u32 rsvd3[3129]; |
| 30 | u32 d31ip; |
| 31 | u32 rsvd4[3]; |
| 32 | u32 d27ip; |
| 33 | u32 rsvd5; |
| 34 | u32 d02ip; |
| 35 | u32 rsvd6; |
| 36 | u32 d26ip; |
| 37 | u32 d25ip; |
| 38 | u32 d24ip; |
| 39 | u32 d23ip; |
| 40 | u32 d03ip; |
| 41 | u32 rsvd7[3]; |
| 42 | u16 d31ir; |
| 43 | u16 rsvd8[3]; |
| 44 | u16 d27ir; |
| 45 | u16 d26ir; |
| 46 | u16 d25ir; |
| 47 | u16 d24ir; |
| 48 | u16 d23ir; |
| 49 | u16 rsvd9[7]; |
| 50 | u16 d02ir; |
| 51 | u16 d03ir; |
| 52 | }; |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 53 | |
| 54 | #endif /* _X86_ARCH_TNC_H_ */ |