blob: bb01d73bdecb4161ec312b6679aff6f87da97b2f [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc824x.h>
26#include <pci.h>
Ben Warrenf2c1acb2008-08-31 10:03:22 -070027#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000028
29int checkboard (void)
30{
31 /*TODO: Check processor type */
32
33 puts ( "Board: Sandpoint "
34#ifdef CONFIG_MPC8240
35 "8240"
36#endif
37#ifdef CONFIG_MPC8245
38 "8245"
39#endif
40 " Unity ##Test not implemented yet##\n");
41 return 0;
42}
43
Wolfgang Denka1be4762008-05-20 16:00:29 +020044#if 0 /* NOT USED */
wdenkc6097192002-11-03 00:24:07 +000045int checkflash (void)
46{
47 /* TODO: XXX XXX XXX */
48 printf ("## Test not implemented yet ##\n");
49
50 return (0);
51}
52#endif
53
Becky Brucebd99ae72008-06-09 16:03:40 -050054phys_size_t initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +000055{
wdenk87249ba2004-01-06 22:38:14 +000056 long size;
57 long new_bank0_end;
58 long mear1;
59 long emear1;
wdenkc6097192002-11-03 00:24:07 +000060
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061 size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
wdenkc6097192002-11-03 00:24:07 +000062
wdenk87249ba2004-01-06 22:38:14 +000063 new_bank0_end = size - 1;
64 mear1 = mpc824x_mpc107_getreg(MEAR1);
65 emear1 = mpc824x_mpc107_getreg(EMEAR1);
66 mear1 = (mear1 & 0xFFFFFF00) |
67 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
68 emear1 = (emear1 & 0xFFFFFF00) |
69 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
70 mpc824x_mpc107_setreg(MEAR1, mear1);
71 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenkc6097192002-11-03 00:24:07 +000072
wdenk87249ba2004-01-06 22:38:14 +000073 return (size);
wdenkc6097192002-11-03 00:24:07 +000074}
75
76/*
77 * Initialize PCI Devices, report devices found.
78 */
79#ifndef CONFIG_PCI_PNP
80static struct pci_config_table pci_sandpoint_config_table[] = {
81 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
82 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
83 PCI_ENET0_MEMADDR,
84 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
85 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
86 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
87 PCI_ENET1_MEMADDR,
88 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
89 { }
90};
91#endif
92
93struct pci_controller hose = {
94#ifndef CONFIG_PCI_PNP
95 config_table: pci_sandpoint_config_table,
96#endif
97};
98
stroesef5dd4102003-02-14 11:21:23 +000099void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000100{
101 pci_mpc824x_init(&hose);
102}
Ben Warrenf2c1acb2008-08-31 10:03:22 -0700103
104int board_eth_init(bd_t *bis)
105{
106 return pci_eth_init(bis);
107}