Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Sysam stmark2 board configuration |
| 4 | * |
| 5 | * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __STMARK2_CONFIG_H |
| 9 | #define __STMARK2_CONFIG_H |
| 10 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 11 | #define CFG_SYS_UART_PORT 0 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 12 | |
| 13 | #define LDS_BOARD_TEXT \ |
| 14 | board/sysam/stmark2/sbf_dram_init.o (.text*) |
| 15 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 16 | #define CFG_EXTRA_ENV_SETTINGS \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 17 | "kern_size=0x700000\0" \ |
| 18 | "loadaddr=0x40001000\0" \ |
| 19 | "-(rootfs)\0" \ |
| 20 | "update_uboot=loady ${loadaddr}; " \ |
| 21 | "sf probe 0:1 50000000; " \ |
| 22 | "sf erase 0 0x80000; " \ |
| 23 | "sf write ${loadaddr} 0 ${filesize}\0" \ |
| 24 | "update_kernel=loady ${loadaddr}; " \ |
| 25 | "setenv kern_size ${filesize}; saveenv; " \ |
| 26 | "sf probe 0:1 50000000; " \ |
| 27 | "sf erase 0x100000 0x700000; " \ |
| 28 | "sf write ${loadaddr} 0x100000 ${filesize}\0" \ |
| 29 | "update_rootfs=loady ${loadaddr}; " \ |
| 30 | "sf probe 0:1 50000000; " \ |
| 31 | "sf erase 0x00800000 0x100000; " \ |
| 32 | "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ |
| 33 | "" |
| 34 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 35 | #define CFG_SYS_SBFHDR_SIZE 0x7 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 36 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 37 | /* Input, PCI, Flexbus, and VCO */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 38 | |
Tom Rini | 0bb9b09 | 2022-12-04 10:13:37 -0500 | [diff] [blame] | 39 | #define CFG_PRAM 2048 /* 2048 KB */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 40 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 41 | #define CFG_SYS_MBAR 0xFC000000 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 42 | |
| 43 | /* |
| 44 | * Definitions for initial stack pointer and data area (in internal SRAM) |
| 45 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 46 | #define CFG_SYS_INIT_RAM_ADDR 0x80000000 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 47 | /* End of used area in internal SRAM */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 48 | #define CFG_SYS_INIT_RAM_SIZE 0x10000 |
| 49 | #define CFG_SYS_INIT_RAM_CTRL 0x221 |
| 50 | #define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 51 | GENERATED_GBL_DATA_SIZE) - 32) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 52 | #define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32) |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Start addresses for the final memory configuration |
| 56 | * (Set up by the startup code) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 57 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 58 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 59 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| 60 | #define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 61 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 62 | #define CFG_SYS_DRAM_TEST |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 63 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 64 | /* Reserve 256 kB for Monitor */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 65 | |
| 66 | /* |
| 67 | * For booting Linux, the board info and command line data |
| 68 | * have to be in the first 8 MB of memory, since this is |
| 69 | * the maximum mapped by the Linux kernel during initialization ?? |
| 70 | */ |
| 71 | /* Initial Memory map for Linux */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 72 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 73 | (CFG_SYS_SDRAM_SIZE << 20)) |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 74 | |
| 75 | /* Configuration for environment |
| 76 | * Environment is embedded in u-boot in the second sector of the flash |
| 77 | */ |
| 78 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 79 | /* Cache Configuration */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 80 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 81 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 82 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 83 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 84 | #define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
| 85 | #define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA) |
| 86 | #define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 87 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 88 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 89 | #define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 90 | CF_CACR_ICINVA | CF_CACR_EUSP) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 91 | #define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 92 | CF_CACR_DEC | CF_CACR_DDCM_P | \ |
| 93 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) |
| 94 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | #define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 96 | CFG_SYS_INIT_RAM_SIZE - 12) |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 97 | |
Angelo Dureghello | 49becce | 2023-02-25 23:25:26 +0100 | [diff] [blame] | 98 | |
Angelo Dureghello | 6d57570 | 2023-04-05 00:59:24 +0200 | [diff] [blame] | 99 | #define CFG_SYS_I2C_0 |
| 100 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 101 | #endif /* __STMARK2_CONFIG_H */ |