| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Marek Vasut | ac737ff | 2011-08-28 03:35:13 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| Marek Vasut | ac737ff | 2011-08-28 03:35:13 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __REGS_UART_H__ |
| 7 | #define __REGS_UART_H__ |
| 8 | |
| 9 | #define FFUART_BASE 0x40100000 |
| 10 | #define BTUART_BASE 0x40200000 |
| 11 | #define STUART_BASE 0x40700000 |
| 12 | #define HWUART_BASE 0x41600000 |
| 13 | |
| 14 | struct pxa_uart_regs { |
| 15 | union { |
| 16 | uint32_t thr; |
| 17 | uint32_t rbr; |
| 18 | uint32_t dll; |
| 19 | }; |
| 20 | union { |
| 21 | uint32_t ier; |
| 22 | uint32_t dlh; |
| 23 | }; |
| 24 | union { |
| 25 | uint32_t fcr; |
| 26 | uint32_t iir; |
| 27 | }; |
| 28 | uint32_t lcr; |
| 29 | uint32_t mcr; |
| 30 | uint32_t lsr; |
| 31 | uint32_t msr; |
| 32 | uint32_t spr; |
| 33 | uint32_t isr; |
| 34 | }; |
| 35 | |
| 36 | #define IER_DMAE (1 << 7) |
| 37 | #define IER_UUE (1 << 6) |
| 38 | #define IER_NRZE (1 << 5) |
| 39 | #define IER_RTIOE (1 << 4) |
| 40 | #define IER_MIE (1 << 3) |
| 41 | #define IER_RLSE (1 << 2) |
| 42 | #define IER_TIE (1 << 1) |
| 43 | #define IER_RAVIE (1 << 0) |
| 44 | |
| 45 | #define IIR_FIFOES1 (1 << 7) |
| 46 | #define IIR_FIFOES0 (1 << 6) |
| 47 | #define IIR_TOD (1 << 3) |
| 48 | #define IIR_IID2 (1 << 2) |
| 49 | #define IIR_IID1 (1 << 1) |
| 50 | #define IIR_IP (1 << 0) |
| 51 | |
| 52 | #define FCR_ITL2 (1 << 7) |
| 53 | #define FCR_ITL1 (1 << 6) |
| 54 | #define FCR_RESETTF (1 << 2) |
| 55 | #define FCR_RESETRF (1 << 1) |
| 56 | #define FCR_TRFIFOE (1 << 0) |
| 57 | #define FCR_ITL_1 0 |
| 58 | #define FCR_ITL_8 (FCR_ITL1) |
| 59 | #define FCR_ITL_16 (FCR_ITL2) |
| 60 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) |
| 61 | |
| 62 | #define LCR_DLAB (1 << 7) |
| 63 | #define LCR_SB (1 << 6) |
| 64 | #define LCR_STKYP (1 << 5) |
| 65 | #define LCR_EPS (1 << 4) |
| 66 | #define LCR_PEN (1 << 3) |
| 67 | #define LCR_STB (1 << 2) |
| 68 | #define LCR_WLS1 (1 << 1) |
| 69 | #define LCR_WLS0 (1 << 0) |
| 70 | |
| 71 | #define LSR_FIFOE (1 << 7) |
| 72 | #define LSR_TEMT (1 << 6) |
| 73 | #define LSR_TDRQ (1 << 5) |
| 74 | #define LSR_BI (1 << 4) |
| 75 | #define LSR_FE (1 << 3) |
| 76 | #define LSR_PE (1 << 2) |
| 77 | #define LSR_OE (1 << 1) |
| 78 | #define LSR_DR (1 << 0) |
| 79 | |
| 80 | #define MCR_LOOP (1 << 4) |
| 81 | #define MCR_OUT2 (1 << 3) |
| 82 | #define MCR_OUT1 (1 << 2) |
| 83 | #define MCR_RTS (1 << 1) |
| 84 | #define MCR_DTR (1 << 0) |
| 85 | |
| 86 | #define MSR_DCD (1 << 7) |
| 87 | #define MSR_RI (1 << 6) |
| 88 | #define MSR_DSR (1 << 5) |
| 89 | #define MSR_CTS (1 << 4) |
| 90 | #define MSR_DDCD (1 << 3) |
| 91 | #define MSR_TERI (1 << 2) |
| 92 | #define MSR_DDSR (1 << 1) |
| 93 | #define MSR_DCTS (1 << 0) |
| 94 | |
| 95 | #endif /* __REGS_UART_H__ */ |