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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hongbo Zhang539e4f12016-08-19 17:20:33 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
Hongbo Zhang539e4f12016-08-19 17:20:33 +08005 * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
6 */
7
8#include <config.h>
9#include <asm/io.h>
10#include <asm/psci.h>
11#include <asm/arch/immap_ls102xa.h>
12#include <fsl_immap.h>
13#include "fsl_epu.h"
14
15#define __secure __attribute__((section("._secure.text")))
16
17#define CCSR_GICD_CTLR 0x1000
18#define CCSR_GICC_CTLR 0x2000
19#define DCSR_RCPM_CG1CR0 0x31c
20#define DCSR_RCPM_CSTTACR0 0xb00
21#define DCFG_CRSTSR_WDRFR 0x8
22#define DDR_RESV_LEN 128
23
24#ifdef CONFIG_LS1_DEEP_SLEEP
25/*
26 * DDR controller initialization training breaks the first 128 bytes of DDR,
27 * save them so that the bootloader can restore them while resuming.
28 */
29static void __secure ls1_save_ddr_head(void)
30{
31 const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
32 char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
33 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
34 int i;
35
36 out_le32(&scfg->sparecr[2], dest);
37
38 for (i = 0; i < DDR_RESV_LEN; i++)
39 *dest++ = *src++;
40}
41
42static void __secure ls1_fsm_setup(void)
43{
44 void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
York Sun48d55ac2016-09-26 08:09:30 -070045 void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
Hongbo Zhang539e4f12016-08-19 17:20:33 +080046
47 out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
48 out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
49
50 fsl_epu_setup((void *)dcsr_epu_base);
51
52 /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
53 out_be32(dcsr_epu_base + EPECR0, 0x5);
54 out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
55}
56
57static void __secure ls1_deepsleep_irq_cfg(void)
58{
59 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
60 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
61 u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
62
63 /* Mask interrupts from GIC */
64 out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
65 out_be32(&rcpm->nirqoutr, 0x0ffffffff);
66 /* Mask deep sleep wake-up interrupts while entering deep sleep */
67 out_be32(&rcpm->dsimskr, 0x0ffffffff);
68
69 ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
70 /*
71 * Workaround: There is bug of register ippdexpcr1, when read it always
72 * returns zero, so its value is saved to a scrachpad register to be
73 * read, that is why we don't read it from register ippdexpcr1 itself.
74 */
75 ippdexpcr1 = in_le32(&scfg->sparecr[7]);
Ran Wangaed04582018-09-26 13:46:30 +080076 out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
Hongbo Zhang539e4f12016-08-19 17:20:33 +080077
78 if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
79 pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
80 SCFG_PMCINTECR_ETSECRXG1 |
81 SCFG_PMCINTECR_ETSECERRG0 |
82 SCFG_PMCINTECR_ETSECERRG1;
83
84 if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
85 pmcintecr |= SCFG_PMCINTECR_GPIO;
86
87 if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
88 pmcintecr |= SCFG_PMCINTECR_LPUART;
89
90 if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
91 pmcintecr |= SCFG_PMCINTECR_FTM;
92
93 /* Always set external IRQ pins as wakeup source */
94 pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
95
96 out_be32(&scfg->pmcintlecr, 0);
97 /* Clear PMC interrupt status */
98 out_be32(&scfg->pmcintsr, 0xffffffff);
99 /* Enable wakeup interrupt during deep sleep */
100 out_be32(&scfg->pmcintecr, pmcintecr);
101}
102
103static void __secure ls1_delay(unsigned int loop)
104{
105 while (loop--) {
106 int i = 1000;
107 while (i--)
108 ;
109 }
110}
111
112static void __secure ls1_start_fsm(void)
113{
114 void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
York Sun48d55ac2016-09-26 08:09:30 -0700115 void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
Hongbo Zhang539e4f12016-08-19 17:20:33 +0800116 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
117 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
118
119 /* Set HRSTCR */
120 setbits_be32(&scfg->hrstcr, 0x80000000);
121
122 /* Place DDR controller in self refresh mode */
123 setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
124
125 ls1_delay(2000);
126
127 /* Set EVT4_B to lock the signal MCKE down */
128 out_be32(dcsr_epu_base + EPECR0, 0x0);
129
130 ls1_delay(2000);
131
132 out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
133 out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
134
135 /* Enable all EPU Counters */
136 setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
137
138 /* Enable SCU15 */
139 setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
140
141 /* Enter WFI mode, and EPU FSM will start */
142 __asm__ __volatile__ ("wfi" : : : "memory");
143
144 /* NEVER ENTER HERE */
145 while (1)
146 ;
147}
148
149static void __secure ls1_deep_sleep(u32 entry_point)
150{
151 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
152 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
153 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
154#ifdef QIXIS_BASE
155 u32 tmp;
156 void *qixis_base = (void *)QIXIS_BASE;
157#endif
158
159 /* Enable cluster to enter the PCL10 state */
160 out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
161
162 /* Save the first 128 bytes of DDR data */
163 ls1_save_ddr_head();
164
165 /* Save the kernel resume entry */
166 out_le32(&scfg->sparecr[3], entry_point);
167
168 /* Request to put cluster 0 in PCL10 state */
169 setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
170
171 /* Setup the registers of the EPU FSM for deep sleep */
172 ls1_fsm_setup();
173
174#ifdef QIXIS_BASE
175 /* Connect the EVENT button to IRQ in FPGA */
176 tmp = in_8(qixis_base + QIXIS_CTL_SYS);
177 tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
178 tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
179 out_8(qixis_base + QIXIS_CTL_SYS, tmp);
180
181 /* Enable deep sleep signals in FPGA */
182 tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
183 tmp |= QIXIS_PWR_CTL2_PCTL;
184 out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
185
186 /* Pull down PCIe RST# */
187 tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
188 tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
189 out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
190#endif
191
192 /* Enable Warm Device Reset */
193 setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
194 setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
195
Ran Wangaed04582018-09-26 13:46:30 +0800196 /* Disable QE */
197 setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
198
Hongbo Zhang539e4f12016-08-19 17:20:33 +0800199 ls1_deepsleep_irq_cfg();
200
201 psci_v7_flush_dcache_all();
202
203 ls1_start_fsm();
204}
205
206#else
207static void __secure ls1_sleep(void)
208{
209 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
210 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
211
212#ifdef QIXIS_BASE
213 u32 tmp;
214 void *qixis_base = (void *)QIXIS_BASE;
215
216 /* Connect the EVENT button to IRQ in FPGA */
217 tmp = in_8(qixis_base + QIXIS_CTL_SYS);
218 tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
219 tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
220 out_8(qixis_base + QIXIS_CTL_SYS, tmp);
221#endif
222
223 /* Enable cluster to enter the PCL10 state */
224 out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
225
226 setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
227
228 __asm__ __volatile__ ("wfi" : : : "memory");
229}
230#endif
231
232void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
233{
234#ifdef CONFIG_LS1_DEEP_SLEEP
235 ls1_deep_sleep(entry_point);
236#else
237 ls1_sleep();
238#endif
239}