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git01.mediatek.com / filogic / uboot / 01c5bd224c860b0df4c1c5ae8751a7e278a89bdf / . / arch / arm / include / asm / arch-rockchip / grf_rk3368.h
blob: a438f5de73a5f9a902fd4796bb521f84440ab9c2 [file] [log] [blame]
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]1/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5#ifndef _ASM_ARCH_GRF_RK3368_H
6#define _ASM_ARCH_GRF_RK3368_H
7
8#include <common.h>
9
10struct rk3368_grf {
11 u32 gpio1a_iomux;
12 u32 gpio1b_iomux;
13 u32 gpio1c_iomux;
14 u32 gpio1d_iomux;
15 u32 gpio2a_iomux;
16 u32 gpio2b_iomux;
17 u32 gpio2c_iomux;
18 u32 gpio2d_iomux;
19 u32 gpio3a_iomux;
20 u32 gpio3b_iomux;
21 u32 gpio3c_iomux;
22 u32 gpio3d_iomux;
23 u32 reserved[0x34];
24 u32 gpio1a_pull;
25 u32 gpio1b_pull;
26 u32 gpio1c_pull;
27 u32 gpio1d_pull;
28 u32 gpio2a_pull;
29 u32 gpio2b_pull;
30 u32 gpio2c_pull;
31 u32 gpio2d_pull;
32 u32 gpio3a_pull;
33 u32 gpio3b_pull;
34 u32 gpio3c_pull;
35 u32 gpio3d_pull;
36 u32 reserved1[0x34];
37 u32 gpio1a_drv;
38 u32 gpio1b_drv;
39 u32 gpio1c_drv;
40 u32 gpio1d_drv;
41 u32 gpio2a_drv;
42 u32 gpio2b_drv;
43 u32 gpio2c_drv;
44 u32 gpio2d_drv;
45 u32 gpio3a_drv;
46 u32 gpio3b_drv;
47 u32 gpio3c_drv;
48 u32 gpio3d_drv;
49 u32 reserved2[0x34];
50 u32 gpio1l_sr;
51 u32 gpio1h_sr;
52 u32 gpio2l_sr;
53 u32 gpio2h_sr;
54 u32 gpio3l_sr;
55 u32 gpio3h_sr;
56 u32 reserved3[0x1a];
57 u32 gpio_smt;
58 u32 reserved4[0x1f];
59 u32 soc_con0;
60 u32 soc_con1;
61 u32 soc_con2;
62 u32 soc_con3;
63 u32 soc_con4;
64 u32 soc_con5;
65 u32 soc_con6;
66 u32 soc_con7;
67 u32 soc_con8;
68 u32 soc_con9;
69 u32 soc_con10;
70 u32 soc_con11;
71 u32 soc_con12;
72 u32 soc_con13;
73 u32 soc_con14;
74 u32 soc_con15;
75 u32 soc_con16;
76 u32 soc_con17;
77};
78check_member(rk3368_grf, soc_con17, 0x444);
79
80struct rk3368_pmu_grf {
81 u32 gpio0a_iomux;
82 u32 gpio0b_iomux;
83 u32 gpio0c_iomux;
84 u32 gpio0d_iomux;
85 u32 gpio0a_pull;
86 u32 gpio0b_pull;
87 u32 gpio0c_pull;
88 u32 gpio0d_pull;
89 u32 gpio0a_drv;
90 u32 gpio0b_drv;
91 u32 gpio0c_drv;
92 u32 gpio0d_drv;
93 u32 gpio0l_sr;
94 u32 gpio0h_sr;
Philipp Tomsich01c5bd22017-07-11 13:42:55 +0200[diff] [blame^]95 u32 reserved[0x72];
Kever Yang7a0ab302017-06-23 16:11:08 +0800[diff] [blame]96 u32 os_reg[4];
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]97};
Philipp Tomsich01c5bd22017-07-11 13:42:55 +0200[diff] [blame^]98check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
99check_member(rk3368_pmu_grf, os_reg[0], 0x200);
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]100
101/*GRF_GPIO0C_IOMUX*/
102enum {
103 GPIO0C7_SHIFT = 14,
104 GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
105 GPIO0C7_GPIO = 0,
106 GPIO0C7_LCDC_D19,
107 GPIO0C7_TRACE_D9,
108 GPIO0C7_UART1_RTSN,
109
110 GPIO0C6_SHIFT = 12,
111 GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
112 GPIO0C6_GPIO = 0,
113 GPIO0C6_LCDC_D18,
114 GPIO0C6_TRACE_D8,
115 GPIO0C6_UART1_CTSN,
116
117 GPIO0C5_SHIFT = 10,
118 GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
119 GPIO0C5_GPIO = 0,
120 GPIO0C5_LCDC_D17,
121 GPIO0C5_TRACE_D7,
122 GPIO0C5_UART1_SOUT,
123
124 GPIO0C4_SHIFT = 8,
125 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
126 GPIO0C4_GPIO = 0,
127 GPIO0C4_LCDC_D16,
128 GPIO0C4_TRACE_D6,
129 GPIO0C4_UART1_SIN,
130
131 GPIO0C3_SHIFT = 6,
132 GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
133 GPIO0C3_GPIO = 0,
134 GPIO0C3_LCDC_D15,
135 GPIO0C3_TRACE_D5,
136 GPIO0C3_MCU_JTAG_TDO,
137
138 GPIO0C2_SHIFT = 4,
139 GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
140 GPIO0C2_GPIO = 0,
141 GPIO0C2_LCDC_D14,
142 GPIO0C2_TRACE_D4,
143 GPIO0C2_MCU_JTAG_TDI,
144
145 GPIO0C1_SHIFT = 2,
146 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
147 GPIO0C1_GPIO = 0,
148 GPIO0C1_LCDC_D13,
149 GPIO0C1_TRACE_D3,
150 GPIO0C1_MCU_JTAG_TRTSN,
151
152 GPIO0C0_SHIFT = 0,
153 GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
154 GPIO0C0_GPIO = 0,
155 GPIO0C0_LCDC_D12,
156 GPIO0C0_TRACE_D2,
157 GPIO0C0_MCU_JTAG_TDO,
158};
159
160/*GRF_GPIO0D_IOMUX*/
161enum {
162 GPIO0D7_SHIFT = 14,
163 GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
164 GPIO0D7_GPIO = 0,
165 GPIO0D7_LCDC_DCLK,
166 GPIO0D7_TRACE_CTL,
167 GPIO0D7_PMU_DEBUG5,
168
169 GPIO0D6_SHIFT = 12,
170 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
171 GPIO0D6_GPIO = 0,
172 GPIO0D6_LCDC_DEN,
173 GPIO0D6_TRACE_CLK,
174 GPIO0D6_PMU_DEBUG4,
175
176 GPIO0D5_SHIFT = 10,
177 GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
178 GPIO0D5_GPIO = 0,
179 GPIO0D5_LCDC_VSYNC,
180 GPIO0D5_TRACE_D15,
181 GPIO0D5_PMU_DEBUG3,
182
183 GPIO0D4_SHIFT = 8,
184 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
185 GPIO0D4_GPIO = 0,
186 GPIO0D4_LCDC_HSYNC,
187 GPIO0D4_TRACE_D14,
188 GPIO0D4_PMU_DEBUG2,
189
190 GPIO0D3_SHIFT = 6,
191 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
192 GPIO0D3_GPIO = 0,
193 GPIO0D3_LCDC_D23,
194 GPIO0D3_TRACE_D13,
195 GPIO0D3_UART4_SIN,
196
197 GPIO0D2_SHIFT = 4,
198 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
199 GPIO0D2_GPIO = 0,
200 GPIO0D2_LCDC_D22,
201 GPIO0D2_TRACE_D12,
202 GPIO0D2_UART4_SOUT,
203
204 GPIO0D1_SHIFT = 2,
205 GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
206 GPIO0D1_GPIO = 0,
207 GPIO0D1_LCDC_D21,
208 GPIO0D1_TRACE_D11,
209 GPIO0D1_UART4_RTSN,
210
211 GPIO0D0_SHIFT = 0,
212 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
213 GPIO0D0_GPIO = 0,
214 GPIO0D0_LCDC_D20,
215 GPIO0D0_TRACE_D10,
216 GPIO0D0_UART4_CTSN,
217};
218
219/*GRF_GPIO2A_IOMUX*/
220enum {
221 GPIO2A7_SHIFT = 14,
222 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
223 GPIO2A7_GPIO = 0,
224 GPIO2A7_SDMMC0_D2,
225 GPIO2A7_JTAG_TCK,
226
227 GPIO2A6_SHIFT = 12,
228 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
229 GPIO2A6_GPIO = 0,
230 GPIO2A6_SDMMC0_D1,
231 GPIO2A6_UART2_SIN,
232
233 GPIO2A5_SHIFT = 10,
234 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
235 GPIO2A5_GPIO = 0,
236 GPIO2A5_SDMMC0_D0,
237 GPIO2A5_UART2_SOUT,
238
239 GPIO2A4_SHIFT = 8,
240 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
241 GPIO2A4_GPIO = 0,
242 GPIO2A4_FLASH_DQS,
243 GPIO2A4_EMMC_CLKO,
244
245 GPIO2A3_SHIFT = 6,
246 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
247 GPIO2A3_GPIO = 0,
248 GPIO2A3_FLASH_CSN3,
249 GPIO2A3_EMMC_RSTNO,
250
251 GPIO2A2_SHIFT = 4,
252 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
253 GPIO2A2_GPIO = 0,
254 GPIO2A2_FLASH_CSN2,
255
256 GPIO2A1_SHIFT = 2,
257 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
258 GPIO2A1_GPIO = 0,
259 GPIO2A1_FLASH_CSN1,
260
261 GPIO2A0_SHIFT = 0,
262 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
263 GPIO2A0_GPIO = 0,
264 GPIO2A0_FLASH_CSN0,
265};
266
267/*GRF_GPIO2D_IOMUX*/
268enum {
269 GPIO2D7_SHIFT = 14,
270 GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
271 GPIO2D7_GPIO = 0,
272 GPIO2D7_SDIO0_D3,
273
274 GPIO2D6_SHIFT = 12,
275 GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
276 GPIO2D6_GPIO = 0,
277 GPIO2D6_SDIO0_D2,
278
279 GPIO2D5_SHIFT = 10,
280 GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
281 GPIO2D5_GPIO = 0,
282 GPIO2D5_SDIO0_D1,
283
284 GPIO2D4_SHIFT = 8,
285 GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
286 GPIO2D4_GPIO = 0,
287 GPIO2D4_SDIO0_D0,
288
289 GPIO2D3_SHIFT = 6,
290 GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
291 GPIO2D3_GPIO = 0,
292 GPIO2D3_UART0_RTS0,
293
294 GPIO2D2_SHIFT = 4,
295 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
296 GPIO2D2_GPIO = 0,
297 GPIO2D2_UART0_CTS0,
298
299 GPIO2D1_SHIFT = 2,
300 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
301 GPIO2D1_GPIO = 0,
302 GPIO2D1_UART0_SOUT,
303
304 GPIO2D0_SHIFT = 0,
305 GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
306 GPIO2D0_GPIO = 0,
307 GPIO2D0_UART0_SIN,
308};
309
310/*GRF_GPIO3C_IOMUX*/
311enum {
312 GPIO3C7_SHIFT = 14,
313 GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
314 GPIO3C7_GPIO = 0,
315 GPIO3C7_EDPHDMI_CECINOUT,
316 GPIO3C7_ISP_FLASHTRIGIN,
317
318 GPIO3C6_SHIFT = 12,
319 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
320 GPIO3C6_GPIO = 0,
321 GPIO3C6_MAC_CLK,
322 GPIO3C6_ISP_SHUTTERTRIG,
323
324 GPIO3C5_SHIFT = 10,
325 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
326 GPIO3C5_GPIO = 0,
327 GPIO3C5_MAC_RXER,
328 GPIO3C5_ISP_PRELIGHTTRIG,
329
330 GPIO3C4_SHIFT = 8,
331 GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
332 GPIO3C4_GPIO = 0,
333 GPIO3C4_MAC_RXDV,
334 GPIO3C4_ISP_FLASHTRIGOUT,
335
336 GPIO3C3_SHIFT = 6,
337 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
338 GPIO3C3_GPIO = 0,
339 GPIO3C3_MAC_RXDV,
340 GPIO3C3_EMMC_RSTNO,
341
342 GPIO3C2_SHIFT = 4,
343 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
344 GPIO3C2_MAC_MDC = 0,
345 GPIO3C2_ISP_SHUTTEREN,
346
347 GPIO3C1_SHIFT = 2,
348 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
349 GPIO3C1_GPIO = 0,
350 GPIO3C1_MAC_RXD2,
351 GPIO3C1_UART3_RTSN,
352
353 GPIO3C0_SHIFT = 0,
354 GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
355 GPIO3C0_GPIO = 0,
356 GPIO3C0_MAC_RXD1,
357 GPIO3C0_UART3_CTSN,
358 GPIO3C0_GPS_RFCLK,
359};
360
361/*GRF_GPIO3D_IOMUX*/
362enum {
363 GPIO3D7_SHIFT = 14,
364 GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
365 GPIO3D7_GPIO = 0,
366 GPIO3D7_SC_VCC18V,
367 GPIO3D7_I2C2_SDA,
368 GPIO3D7_GPUJTAG_TCK,
369
370 GPIO3D6_SHIFT = 12,
371 GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
372 GPIO3D6_GPIO = 0,
373 GPIO3D6_IR_TX,
374 GPIO3D6_UART3_SOUT,
375 GPIO3D6_PWM3,
376
377 GPIO3D5_SHIFT = 10,
378 GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
379 GPIO3D5_GPIO = 0,
380 GPIO3D5_IR_RX,
381 GPIO3D5_UART3_SIN,
382
383 GPIO3D4_SHIFT = 8,
384 GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
385 GPIO3D4_GPIO = 0,
386 GPIO3D4_MAC_TXCLKOUT,
387 GPIO3D4_SPI1_CSN1,
388
389 GPIO3D3_SHIFT = 6,
390 GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
391 GPIO3D3_GPIO = 0,
392 GPIO3D3_HDMII2C_SCL,
393 GPIO3D3_I2C5_SCL,
394
395 GPIO3D2_SHIFT = 4,
396 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
397 GPIO3D2_GPIO = 0,
398 GPIO3D2_HDMII2C_SDA,
399 GPIO3D2_I2C5_SDA,
400
401 GPIO3D1_SHIFT = 2,
402 GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
403 GPIO3D1_GPIO = 0,
404 GPIO3D1_MAC_RXCLKIN,
405 GPIO3D1_I2C4_SCL,
406
407 GPIO3D0_SHIFT = 0,
408 GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
409 GPIO3D0_GPIO = 0,
410 GPIO3D0_MAC_MDIO,
411 GPIO3D0_I2C4_SDA,
412};
413
414/*GRF_SOC_CON11/12/13*/
415enum {
416 MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
417 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
418};
419
420/*GRF_SOC_CON12*/
421enum {
422 MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
423 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
424};
425
426/*GRF_SOC_CON13*/
427enum {
428 MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
429 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
430};
431
432/*GRF_SOC_CON14*/
433enum {
434 MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
435 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
436 MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
437 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
438 MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
439 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
440 MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
441 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
442};
443#endif