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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09002/*
3 * Configuation settings for the Renesas SH7763RDP board
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09007 */
8
9#ifndef __SH7763RDP_H
10#define __SH7763RDP_H
11
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090012#define CONFIG_CPU_SH7763 1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090013#define __LITTLE_ENDIAN 1
14
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090015#define CONFIG_ENV_OVERWRITE 1
16
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090018
19/* SCIF */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090020#define CONFIG_CONS_SCIF2 1
21
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090024 settings for this board */
25
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090026/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
28#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
29#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
30#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090031
32/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_FLASH_BASE (0xA0000000)
34#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
35#define CONFIG_SYS_MAX_FLASH_BANKS (1)
36#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090037
Bin Meng75574052016-02-05 19:30:11 -080038/* U-Boot setting */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
40#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
41#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090042/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090045
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#undef CONFIG_SYS_FLASH_QUIET_TEST
47#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090048/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090050/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090052/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090054/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090056/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020058#define CONFIG_ENV_SECT_SIZE (128 * 1024)
59#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
61/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
62#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020063#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090065
66/* Clock */
67#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090068#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090069
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090070/* Ether */
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090071#define CONFIG_SH_ETHER_USE_PORT (1)
72#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +090073#define CONFIG_BITBANGMII
74#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +090075#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090076
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090077#endif /* __SH7763RDP_H */