Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Renesas SH7763RDP board |
| 4 | * |
| 5 | * Copyright (C) 2008 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __SH7763RDP_H |
| 10 | #define __SH7763RDP_H |
| 11 | |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 12 | #define CONFIG_CPU_SH7763 1 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 13 | #define __LITTLE_ENDIAN 1 |
| 14 | |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 15 | #define CONFIG_ENV_OVERWRITE 1 |
| 16 | |
Vladimir Zapolskiy | 5e72b84 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 17 | #define CONFIG_DISPLAY_BOARDINFO |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 18 | |
| 19 | /* SCIF */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 20 | #define CONFIG_CONS_SCIF2 1 |
| 21 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 24 | settings for this board */ |
| 25 | |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 26 | /* SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
| 28 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
| 29 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
| 30 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 31 | |
| 32 | /* Flash(NOR) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
| 34 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) |
| 35 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) |
| 36 | #define CONFIG_SYS_MAX_FLASH_SECT (520) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 37 | |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 38 | /* U-Boot setting */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
| 40 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
| 41 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 42 | /* Size of DRAM reserved for malloc() use */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 45 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
| 47 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 48 | /* Timeout for Flash erase operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 50 | /* Timeout for Flash write operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 52 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 54 | /* Timeout for Flash clear lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 56 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 58 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 59 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
| 61 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ |
| 62 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 63 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 65 | |
| 66 | /* Clock */ |
| 67 | #define CONFIG_SYS_CLK_FREQ 66666666 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 68 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 69 | |
Nobuhiro Iwamatsu | 8a0d1c7 | 2008-08-08 16:30:23 +0900 | [diff] [blame] | 70 | /* Ether */ |
Nobuhiro Iwamatsu | 8a0d1c7 | 2008-08-08 16:30:23 +0900 | [diff] [blame] | 71 | #define CONFIG_SH_ETHER_USE_PORT (1) |
| 72 | #define CONFIG_SH_ETHER_PHY_ADDR (0x01) |
Yoshihiro Shimoda | c578baa | 2011-10-31 10:44:18 +0900 | [diff] [blame] | 73 | #define CONFIG_BITBANGMII |
| 74 | #define CONFIG_BITBANGMII_MULTI |
Nobuhiro Iwamatsu | 32f900e | 2012-05-16 10:23:21 +0900 | [diff] [blame] | 75 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
Nobuhiro Iwamatsu | 8a0d1c7 | 2008-08-08 16:30:23 +0900 | [diff] [blame] | 76 | |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 77 | #endif /* __SH7763RDP_H */ |