Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 2 | /* |
Kumar Gala | 6ad0eb5 | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 3 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * mpc8569mds board configuration file |
| 8 | */ |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
Kumar Gala | 6ad0eb5 | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 12 | #define CONFIG_SYS_SRIO |
| 13 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 14 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 15 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
| 16 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 17 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 18 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 19 | #define CONFIG_ENV_OVERWRITE |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 20 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 21 | #ifndef __ASSEMBLY__ |
| 22 | extern unsigned long get_clock_freq(void); |
| 23 | #endif |
| 24 | /* Replace a call to get_clock_freq (after it is implemented)*/ |
Dave Liu | 3058358 | 2009-05-18 17:49:23 +0800 | [diff] [blame] | 25 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 26 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 27 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 28 | #ifdef CONFIG_ATM |
Liu Yu | 06f0ebe | 2009-11-27 15:31:52 +0800 | [diff] [blame] | 29 | #define CONFIG_PQ_MDS_PIB |
| 30 | #define CONFIG_PQ_MDS_PIB_ATM |
| 31 | #endif |
| 32 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 33 | /* |
| 34 | * These can be toggled for performance analysis, otherwise use default. |
| 35 | */ |
| 36 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 37 | #define CONFIG_BTB /* toggle branch predition */ |
| 38 | |
Haiying Wang | 31b9012 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 39 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 40 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 41 | #endif |
| 42 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 43 | /* |
| 44 | * Only possible on E500 Version 2 or newer cores. |
| 45 | */ |
| 46 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 47 | |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 48 | #define CONFIG_HWCONFIG |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 49 | |
| 50 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 51 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 52 | |
| 53 | /* |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 54 | * Config the L2 Cache as L2 SRAM |
| 55 | */ |
| 56 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 57 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 58 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 59 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 60 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 61 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 62 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 63 | |
Kumar Gala | 842aa5b | 2011-11-09 09:10:49 -0600 | [diff] [blame] | 64 | #if defined(CONFIG_NAND_SPL) |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 65 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 66 | #endif |
| 67 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 68 | /* DDR Setup */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 69 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 70 | #define CONFIG_DDR_SPD |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 71 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 72 | |
| 73 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 74 | |
| 75 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 76 | /* DDR is system memory*/ |
| 77 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 78 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 79 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 80 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 81 | |
| 82 | /* I2C addresses of SPD EEPROMs */ |
Kumar Gala | c68e86c | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 83 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 84 | |
| 85 | /* These are used when DDR doesn't use SPD. */ |
| 86 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ |
| 87 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| 88 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 89 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 90 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 |
| 91 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 |
| 92 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 |
| 93 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 |
| 94 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 |
| 95 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 |
| 96 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 |
| 97 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 |
| 98 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 99 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 |
| 100 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 101 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 102 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
| 103 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 |
| 104 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 |
| 105 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 |
| 106 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 107 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 108 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ |
| 109 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 |
| 110 | |
| 111 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 112 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 113 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
| 114 | |
| 115 | #undef CONFIG_CLOCKS_IN_MHZ |
| 116 | |
| 117 | /* |
| 118 | * Local Bus Definitions |
| 119 | */ |
| 120 | |
| 121 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
| 122 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 123 | |
| 124 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 |
| 125 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE |
| 126 | |
| 127 | /*Chip select 0 - Flash*/ |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 128 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
| 129 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 130 | |
Haiying Wang | 7a1d7b8 | 2009-05-20 12:30:32 -0400 | [diff] [blame] | 131 | /*Chip select 1 - BCSR*/ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 132 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
| 133 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 |
| 134 | |
Haiying Wang | 7a1d7b8 | 2009-05-20 12:30:32 -0400 | [diff] [blame] | 135 | /*Chip select 4 - PIB*/ |
| 136 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 |
| 137 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 |
| 138 | |
| 139 | /*Chip select 5 - PIB*/ |
| 140 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 |
| 141 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 |
| 142 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 143 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 144 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ |
| 145 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 146 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 147 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 148 | |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 149 | #undef CONFIG_SYS_RAMBOOT |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 150 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 151 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 152 | |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 153 | /* Chip select 3 - NAND */ |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 154 | #ifndef CONFIG_NAND_SPL |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 155 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 156 | #else |
| 157 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 |
| 158 | #endif |
| 159 | |
| 160 | /* NAND boot: 4K NAND loader config */ |
| 161 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
| 162 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) |
| 163 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| 164 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| 165 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| 166 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 167 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| 168 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| 169 | |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 170 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 171 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } |
| 172 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 173 | #define CONFIG_NAND_FSL_ELBC 1 |
| 174 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 175 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 176 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 177 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 178 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 179 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 180 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Anton Vorontsov | f1a8051 | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 181 | | OR_FCM_CSCT \ |
| 182 | | OR_FCM_CST \ |
| 183 | | OR_FCM_CHT \ |
| 184 | | OR_FCM_SCY_1 \ |
| 185 | | OR_FCM_TRLX \ |
| 186 | | OR_FCM_EHTR) |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 187 | |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 188 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 189 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 190 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 191 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 192 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 193 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
| 194 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ |
| 195 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 196 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
| 197 | |
| 198 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 199 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 201 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 202 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 203 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 204 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 205 | |
| 206 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
Haiying Wang | b228ae6 | 2009-06-04 16:12:39 -0400 | [diff] [blame] | 207 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 208 | |
| 209 | /* Serial Port */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 210 | #define CONFIG_SYS_NS16550_SERIAL |
| 211 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 212 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Kumar Gala | f273623 | 2010-04-07 01:34:11 -0500 | [diff] [blame] | 213 | #ifdef CONFIG_NAND_SPL |
| 214 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 215 | #endif |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 216 | |
| 217 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 218 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 219 | |
| 220 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 221 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 222 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 223 | /* |
| 224 | * I2C |
| 225 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_I2C |
| 227 | #define CONFIG_SYS_I2C_FSL |
| 228 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 229 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 230 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 231 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 232 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 233 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 234 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 235 | |
| 236 | /* |
| 237 | * I2C2 EEPROM |
| 238 | */ |
| 239 | #define CONFIG_ID_EEPROM |
| 240 | #ifdef CONFIG_ID_EEPROM |
| 241 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 242 | #endif |
| 243 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 244 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 245 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| 246 | |
| 247 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F |
| 248 | #define PLPPAR1_I2C2_VAL 0x00000000 |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 249 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 250 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
| 251 | #define PLPDIR1_I2C2_VAL 0x0000000F |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 252 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
Anton Vorontsov | 0524117 | 2009-12-16 01:14:31 +0300 | [diff] [blame] | 253 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
| 254 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 |
| 255 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 |
| 256 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 257 | |
| 258 | /* |
| 259 | * General PCI |
| 260 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 |
| 261 | */ |
Kumar Gala | b999ae8 | 2010-12-17 10:18:07 -0600 | [diff] [blame] | 262 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 263 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
| 264 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
| 265 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
| 266 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 267 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
| 268 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 269 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
| 270 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ |
| 271 | |
Kumar Gala | 6ad0eb5 | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 272 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
| 273 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 |
| 274 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS |
| 275 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 276 | |
| 277 | #ifdef CONFIG_QE |
| 278 | /* |
| 279 | * QE UEC ethernet configuration |
| 280 | */ |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 281 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
| 282 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 283 | |
| 284 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) |
| 285 | #define CONFIG_UEC_ETH |
Kim Phillips | b42cf5f | 2010-07-26 18:34:57 -0500 | [diff] [blame] | 286 | #define CONFIG_ETHPRIME "UEC0" |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 287 | #define CONFIG_PHY_MODE_NEED_CHANGE |
| 288 | |
| 289 | #define CONFIG_UEC_ETH1 /* GETH1 */ |
| 290 | #define CONFIG_HAS_ETH0 |
| 291 | |
| 292 | #ifdef CONFIG_UEC_ETH1 |
| 293 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
| 294 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 295 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 296 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
| 297 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH |
| 298 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 299 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 300 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 301 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 302 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ |
| 303 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
| 304 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 305 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 306 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 307 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 308 | #endif /* CONFIG_UEC_ETH1 */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 309 | |
| 310 | #define CONFIG_UEC_ETH2 /* GETH2 */ |
| 311 | #define CONFIG_HAS_ETH1 |
| 312 | |
| 313 | #ifdef CONFIG_UEC_ETH2 |
| 314 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
| 315 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 316 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 317 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
| 318 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH |
| 319 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 320 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 321 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 322 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 323 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ |
| 324 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH |
| 325 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 326 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 327 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 328 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 329 | #endif /* CONFIG_UEC_ETH2 */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 330 | |
Haiying Wang | df1bbbd | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 331 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
| 332 | #define CONFIG_HAS_ETH2 |
| 333 | |
| 334 | #ifdef CONFIG_UEC_ETH3 |
| 335 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ |
| 336 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 337 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | df1bbbd | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 338 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
| 339 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH |
| 340 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 341 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 342 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 343 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 344 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ |
| 345 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH |
| 346 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 347 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 348 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 349 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 350 | #endif /* CONFIG_UEC_ETH3 */ |
Haiying Wang | df1bbbd | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 351 | |
| 352 | #define CONFIG_UEC_ETH4 /* GETH4 */ |
| 353 | #define CONFIG_HAS_ETH3 |
| 354 | |
| 355 | #ifdef CONFIG_UEC_ETH4 |
| 356 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ |
| 357 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 358 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | df1bbbd | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 359 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
| 360 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH |
| 361 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 362 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 363 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 364 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 365 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ |
| 366 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH |
| 367 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 368 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 369 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
Haiying Wang | bc759ee | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 370 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 371 | #endif /* CONFIG_UEC_ETH4 */ |
Haiying Wang | 10b981b | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 372 | |
| 373 | #undef CONFIG_UEC_ETH6 /* GETH6 */ |
| 374 | #define CONFIG_HAS_ETH5 |
| 375 | |
| 376 | #ifdef CONFIG_UEC_ETH6 |
| 377 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ |
| 378 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE |
| 379 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE |
| 380 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH |
| 381 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 382 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 383 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
Haiying Wang | 10b981b | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 384 | #endif /* CONFIG_UEC_ETH6 */ |
| 385 | |
| 386 | #undef CONFIG_UEC_ETH8 /* GETH8 */ |
| 387 | #define CONFIG_HAS_ETH7 |
| 388 | |
| 389 | #ifdef CONFIG_UEC_ETH8 |
| 390 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ |
| 391 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE |
| 392 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE |
| 393 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH |
| 394 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 |
Andy Fleming | 7832a46 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 395 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
Heiko Schocher | 40b44bc | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 396 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
Haiying Wang | 10b981b | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 397 | #endif /* CONFIG_UEC_ETH8 */ |
| 398 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 399 | #endif /* CONFIG_QE */ |
| 400 | |
| 401 | #if defined(CONFIG_PCI) |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 402 | #undef CONFIG_EEPRO100 |
| 403 | #undef CONFIG_TULIP |
| 404 | |
| 405 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 406 | |
| 407 | #endif /* CONFIG_PCI */ |
| 408 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 409 | /* |
| 410 | * Environment |
| 411 | */ |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 412 | #if defined(CONFIG_SYS_RAMBOOT) |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 413 | #else |
Haiying Wang | b228ae6 | 2009-06-04 16:12:39 -0400 | [diff] [blame] | 414 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
Haiying Wang | bd76d19 | 2010-09-29 13:44:14 -0400 | [diff] [blame] | 415 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 416 | #define CONFIG_ENV_SIZE 0x2000 |
Liu Yu | 2639e51 | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 417 | #endif |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 418 | |
| 419 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 420 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 421 | |
| 422 | /* QE microcode/firmware address */ |
Zhao Qiang | 83a9084 | 2014-03-21 16:21:44 +0800 | [diff] [blame] | 423 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * BOOTP options |
| 427 | */ |
| 428 | #define CONFIG_BOOTP_BOOTFILESIZE |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 429 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 430 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 431 | |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 432 | #ifdef CONFIG_MMC |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 433 | #define CONFIG_FSL_ESDHC_PIN_MUX |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 434 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
Anton Vorontsov | da22594 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 435 | #endif |
| 436 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 437 | /* |
| 438 | * Miscellaneous configurable options |
| 439 | */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 440 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 441 | #if defined(CONFIG_CMD_KGDB) |
| 442 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ |
| 443 | #else |
| 444 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 445 | #endif |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 446 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
| 447 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 448 | /* Boot Argument Buffer Size */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 449 | |
| 450 | /* |
| 451 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 452 | * have to be in the first 64 MB of memory, since this is |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 453 | * the maximum mapped by the Linux kernel during initialization. |
| 454 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 455 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 456 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 457 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 458 | #if defined(CONFIG_CMD_KGDB) |
| 459 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 460 | #endif |
| 461 | |
| 462 | /* |
| 463 | * Environment Configuration |
| 464 | */ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 465 | #define CONFIG_HOSTNAME "mpc8569mds" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 466 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 467 | #define CONFIG_BOOTFILE "your.uImage" |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 468 | |
| 469 | #define CONFIG_SERVERIP 192.168.1.1 |
| 470 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 471 | #define CONFIG_NETMASK 255.255.255.0 |
| 472 | |
| 473 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
| 474 | |
Haiying Wang | bd25537 | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 475 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 476 | "netdev=eth0\0" \ |
| 477 | "consoledev=ttyS0\0" \ |
| 478 | "ramdiskaddr=600000\0" \ |
| 479 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 480 | "fdtaddr=400000\0" \ |
| 481 | "fdtfile=your.fdt.dtb\0" \ |
| 482 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 483 | "nfsroot=$serverip:$rootpath " \ |
| 484 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 485 | "console=$consoledev,$baudrate $othbootargs\0" \ |
| 486 | "ramargs=setenv bootargs root=/dev/ram rw " \ |
| 487 | "console=$consoledev,$baudrate $othbootargs\0" \ |
| 488 | |
| 489 | #define CONFIG_NFSBOOTCOMMAND \ |
| 490 | "run nfsargs;" \ |
| 491 | "tftp $loadaddr $bootfile;" \ |
| 492 | "tftp $fdtaddr $fdtfile;" \ |
| 493 | "bootm $loadaddr - $fdtaddr" |
| 494 | |
| 495 | #define CONFIG_RAMBOOTCOMMAND \ |
| 496 | "run ramargs;" \ |
| 497 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 498 | "tftp $loadaddr $bootfile;" \ |
| 499 | "bootm $loadaddr $ramdiskaddr" |
| 500 | |
| 501 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 502 | |
| 503 | #endif /* __CONFIG_H */ |