blob: de187bf9a4f56e4ed857cde63648e2115a259234 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Haiying Wangbd255372009-03-27 17:02:45 -04002/*
Kumar Gala6ad0eb52011-01-04 18:04:01 -06003 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Haiying Wangbd255372009-03-27 17:02:45 -04004 */
5
6/*
7 * mpc8569mds board configuration file
8 */
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kumar Gala6ad0eb52011-01-04 18:04:01 -060012#define CONFIG_SYS_SRIO
13#define CONFIG_SRIO1 /* SRIO port 1 */
14
Haiying Wangbd255372009-03-27 17:02:45 -040015#define CONFIG_PCIE1 1 /* PCIE controller */
16#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000017#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Haiying Wangbd255372009-03-27 17:02:45 -040018#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Haiying Wangbd255372009-03-27 17:02:45 -040019#define CONFIG_ENV_OVERWRITE
Haiying Wangbd255372009-03-27 17:02:45 -040020
Haiying Wangbd255372009-03-27 17:02:45 -040021#ifndef __ASSEMBLY__
22extern unsigned long get_clock_freq(void);
23#endif
24/* Replace a call to get_clock_freq (after it is implemented)*/
Dave Liu30583582009-05-18 17:49:23 +080025#define CONFIG_SYS_CLK_FREQ 66666666
26#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
Haiying Wangbd255372009-03-27 17:02:45 -040027
Wolfgang Denkdc25d152010-10-04 19:58:00 +020028#ifdef CONFIG_ATM
Liu Yu06f0ebe2009-11-27 15:31:52 +080029#define CONFIG_PQ_MDS_PIB
30#define CONFIG_PQ_MDS_PIB_ATM
31#endif
32
Haiying Wangbd255372009-03-27 17:02:45 -040033/*
34 * These can be toggled for performance analysis, otherwise use default.
35 */
36#define CONFIG_L2_CACHE /* toggle L2 cache */
37#define CONFIG_BTB /* toggle branch predition */
38
Haiying Wang31b90122010-11-10 15:37:13 -050039#ifndef CONFIG_SYS_MONITOR_BASE
40#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
41#endif
42
Haiying Wangbd255372009-03-27 17:02:45 -040043/*
44 * Only possible on E500 Version 2 or newer cores.
45 */
46#define CONFIG_ENABLE_36BIT_PHYS 1
47
Anton Vorontsovda225942009-10-15 17:47:06 +040048#define CONFIG_HWCONFIG
Haiying Wangbd255372009-03-27 17:02:45 -040049
50#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
51#define CONFIG_SYS_MEMTEST_END 0x00400000
52
53/*
Liu Yu2639e512010-01-18 19:03:28 +080054 * Config the L2 Cache as L2 SRAM
55 */
56#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
57#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
58#define CONFIG_SYS_L2_SIZE (512 << 10)
59#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
60
Timur Tabid8f341c2011-08-04 18:03:41 -050061#define CONFIG_SYS_CCSRBAR 0xe0000000
62#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Haiying Wangbd255372009-03-27 17:02:45 -040063
Kumar Gala842aa5b2011-11-09 09:10:49 -060064#if defined(CONFIG_NAND_SPL)
Timur Tabid8f341c2011-08-04 18:03:41 -050065#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Liu Yu2639e512010-01-18 19:03:28 +080066#endif
67
Haiying Wangbd255372009-03-27 17:02:45 -040068/* DDR Setup */
Haiying Wangbd255372009-03-27 17:02:45 -040069#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
70#define CONFIG_DDR_SPD
Haiying Wangbd255372009-03-27 17:02:45 -040071#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
72
73#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
74
75#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
76 /* DDR is system memory*/
77#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
78
Haiying Wangbd255372009-03-27 17:02:45 -040079#define CONFIG_DIMM_SLOTS_PER_CTLR 1
80#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
81
82/* I2C addresses of SPD EEPROMs */
Kumar Galac68e86c2011-01-31 22:18:47 -060083#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Haiying Wangbd255372009-03-27 17:02:45 -040084
85/* These are used when DDR doesn't use SPD. */
86#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
87#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
88#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
89#define CONFIG_SYS_DDR_TIMING_3 0x00020000
90#define CONFIG_SYS_DDR_TIMING_0 0x00330004
91#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
92#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
93#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
94#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
95#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
96#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
97#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
98#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
99#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
100#define CONFIG_SYS_DDR_TIMING_4 0x00220001
101#define CONFIG_SYS_DDR_TIMING_5 0x03402400
102#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
103#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
104#define CONFIG_SYS_DDR_CDR_1 0x80040000
105#define CONFIG_SYS_DDR_CDR_2 0x00000000
106#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
107#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
108#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
109#define CONFIG_SYS_DDR_CONTROL2 0x24400000
110
111#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
112#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
113#define CONFIG_SYS_DDR_SBE 0x00010000
114
115#undef CONFIG_CLOCKS_IN_MHZ
116
117/*
118 * Local Bus Definitions
119 */
120
121#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
122#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
123
124#define CONFIG_SYS_BCSR_BASE 0xf8000000
125#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
126
127/*Chip select 0 - Flash*/
Liu Yu2639e512010-01-18 19:03:28 +0800128#define CONFIG_FLASH_BR_PRELIM 0xfe000801
129#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
Haiying Wangbd255372009-03-27 17:02:45 -0400130
Haiying Wang7a1d7b82009-05-20 12:30:32 -0400131/*Chip select 1 - BCSR*/
Haiying Wangbd255372009-03-27 17:02:45 -0400132#define CONFIG_SYS_BR1_PRELIM 0xf8000801
133#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
134
Haiying Wang7a1d7b82009-05-20 12:30:32 -0400135/*Chip select 4 - PIB*/
136#define CONFIG_SYS_BR4_PRELIM 0xf8008801
137#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
138
139/*Chip select 5 - PIB*/
140#define CONFIG_SYS_BR5_PRELIM 0xf8010801
141#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
142
Haiying Wangbd255372009-03-27 17:02:45 -0400143#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
144#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
145#undef CONFIG_SYS_FLASH_CHECKSUM
146#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
148
Liu Yu2639e512010-01-18 19:03:28 +0800149#undef CONFIG_SYS_RAMBOOT
Liu Yu2639e512010-01-18 19:03:28 +0800150
Haiying Wangbd255372009-03-27 17:02:45 -0400151#define CONFIG_SYS_FLASH_EMPTY_INFO
152
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400153/* Chip select 3 - NAND */
Liu Yu2639e512010-01-18 19:03:28 +0800154#ifndef CONFIG_NAND_SPL
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400155#define CONFIG_SYS_NAND_BASE 0xFC000000
Liu Yu2639e512010-01-18 19:03:28 +0800156#else
157#define CONFIG_SYS_NAND_BASE 0xFFF00000
158#endif
159
160/* NAND boot: 4K NAND loader config */
161#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
162#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
163#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
164#define CONFIG_SYS_NAND_U_BOOT_START \
165 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
166#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
167#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
168#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
169
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400170#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
171#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
172#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400173#define CONFIG_NAND_FSL_ELBC 1
174#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Matthew McClintock48aab142011-04-05 14:39:33 -0500175#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400176 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
177 | BR_PS_8 /* Port Size = 8 bit */ \
178 | BR_MS_FCM /* MSEL = FCM */ \
179 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500180#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Anton Vorontsovf1a80512009-10-15 17:47:08 +0400181 | OR_FCM_CSCT \
182 | OR_FCM_CST \
183 | OR_FCM_CHT \
184 | OR_FCM_SCY_1 \
185 | OR_FCM_TRLX \
186 | OR_FCM_EHTR)
Liu Yu2639e512010-01-18 19:03:28 +0800187
Liu Yu2639e512010-01-18 19:03:28 +0800188#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
189#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintock48aab142011-04-05 14:39:33 -0500190#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
191#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangbd255372009-03-27 17:02:45 -0400192
Haiying Wangbd255372009-03-27 17:02:45 -0400193#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
194#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
195#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
196#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
197
198#define CONFIG_SYS_INIT_RAM_LOCK 1
199#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200200#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Haiying Wangbd255372009-03-27 17:02:45 -0400201
Haiying Wangbd255372009-03-27 17:02:45 -0400202#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Haiying Wangbd255372009-03-27 17:02:45 -0400204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205
206#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Haiying Wangb228ae62009-06-04 16:12:39 -0400207#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Haiying Wangbd255372009-03-27 17:02:45 -0400208
209/* Serial Port */
Haiying Wangbd255372009-03-27 17:02:45 -0400210#define CONFIG_SYS_NS16550_SERIAL
211#define CONFIG_SYS_NS16550_REG_SIZE 1
212#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galaf2736232010-04-07 01:34:11 -0500213#ifdef CONFIG_NAND_SPL
214#define CONFIG_NS16550_MIN_FUNCTIONS
215#endif
Haiying Wangbd255372009-03-27 17:02:45 -0400216
217#define CONFIG_SYS_BAUDRATE_TABLE \
218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
219
220#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
221#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
222
Haiying Wangbd255372009-03-27 17:02:45 -0400223/*
224 * I2C
225 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200226#define CONFIG_SYS_I2C
227#define CONFIG_SYS_I2C_FSL
228#define CONFIG_SYS_FSL_I2C_SPEED 400000
229#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230#define CONFIG_SYS_FSL_I2C2_SPEED 400000
231#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
232#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
233#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
234#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Haiying Wangbd255372009-03-27 17:02:45 -0400235
236/*
237 * I2C2 EEPROM
238 */
239#define CONFIG_ID_EEPROM
240#ifdef CONFIG_ID_EEPROM
241#define CONFIG_SYS_I2C_EEPROM_NXID
242#endif
243#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
244#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
245#define CONFIG_SYS_EEPROM_BUS_NUM 1
246
247#define PLPPAR1_I2C_BIT_MASK 0x0000000F
248#define PLPPAR1_I2C2_VAL 0x00000000
Anton Vorontsovda225942009-10-15 17:47:06 +0400249#define PLPPAR1_ESDHC_VAL 0x0000000A
Haiying Wangbd255372009-03-27 17:02:45 -0400250#define PLPDIR1_I2C_BIT_MASK 0x0000000F
251#define PLPDIR1_I2C2_VAL 0x0000000F
Anton Vorontsovda225942009-10-15 17:47:06 +0400252#define PLPDIR1_ESDHC_VAL 0x00000006
Anton Vorontsov05241172009-12-16 01:14:31 +0300253#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
254#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
255#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
256#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
Haiying Wangbd255372009-03-27 17:02:45 -0400257
258/*
259 * General PCI
260 * Memory Addresses are mapped 1-1. I/O is mapped from 0
261 */
Kumar Galab999ae82010-12-17 10:18:07 -0600262#define CONFIG_SYS_PCIE1_NAME "Slot"
Haiying Wangbd255372009-03-27 17:02:45 -0400263#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
264#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
265#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
266#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
267#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
268#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
269#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
270#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
271
Kumar Gala6ad0eb52011-01-04 18:04:01 -0600272#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
273#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
274#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
275#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Haiying Wangbd255372009-03-27 17:02:45 -0400276
277#ifdef CONFIG_QE
278/*
279 * QE UEC ethernet configuration
280 */
Haiying Wangbc759ee2009-05-20 12:30:37 -0400281#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
282#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
Haiying Wangbd255372009-03-27 17:02:45 -0400283
284#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
285#define CONFIG_UEC_ETH
Kim Phillipsb42cf5f2010-07-26 18:34:57 -0500286#define CONFIG_ETHPRIME "UEC0"
Haiying Wangbd255372009-03-27 17:02:45 -0400287#define CONFIG_PHY_MODE_NEED_CHANGE
288
289#define CONFIG_UEC_ETH1 /* GETH1 */
290#define CONFIG_HAS_ETH0
291
292#ifdef CONFIG_UEC_ETH1
293#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
294#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
Haiying Wangbc759ee2009-05-20 12:30:37 -0400295#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wangbd255372009-03-27 17:02:45 -0400296#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
297#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
298#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming7832a462011-04-13 00:37:12 -0500299#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100300#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Haiying Wangbc759ee2009-05-20 12:30:37 -0400301#elif defined(CONFIG_SYS_UCC_RMII_MODE)
302#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
303#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
304#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
Andy Fleming7832a462011-04-13 00:37:12 -0500305#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100306#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Haiying Wangbc759ee2009-05-20 12:30:37 -0400307#endif /* CONFIG_SYS_UCC_RGMII_MODE */
308#endif /* CONFIG_UEC_ETH1 */
Haiying Wangbd255372009-03-27 17:02:45 -0400309
310#define CONFIG_UEC_ETH2 /* GETH2 */
311#define CONFIG_HAS_ETH1
312
313#ifdef CONFIG_UEC_ETH2
314#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
315#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
Haiying Wangbc759ee2009-05-20 12:30:37 -0400316#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wangbd255372009-03-27 17:02:45 -0400317#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
318#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
319#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming7832a462011-04-13 00:37:12 -0500320#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100321#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Haiying Wangbc759ee2009-05-20 12:30:37 -0400322#elif defined(CONFIG_SYS_UCC_RMII_MODE)
323#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
324#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
325#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
Andy Fleming7832a462011-04-13 00:37:12 -0500326#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100327#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Haiying Wangbc759ee2009-05-20 12:30:37 -0400328#endif /* CONFIG_SYS_UCC_RGMII_MODE */
329#endif /* CONFIG_UEC_ETH2 */
Haiying Wangbd255372009-03-27 17:02:45 -0400330
Haiying Wangdf1bbbd2009-05-20 12:30:36 -0400331#define CONFIG_UEC_ETH3 /* GETH3 */
332#define CONFIG_HAS_ETH2
333
334#ifdef CONFIG_UEC_ETH3
335#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
336#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
Haiying Wangbc759ee2009-05-20 12:30:37 -0400337#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wangdf1bbbd2009-05-20 12:30:36 -0400338#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
339#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
340#define CONFIG_SYS_UEC3_PHY_ADDR 2
Andy Fleming7832a462011-04-13 00:37:12 -0500341#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100342#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
Haiying Wangbc759ee2009-05-20 12:30:37 -0400343#elif defined(CONFIG_SYS_UCC_RMII_MODE)
344#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
345#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
346#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
Andy Fleming7832a462011-04-13 00:37:12 -0500347#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100348#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
Haiying Wangbc759ee2009-05-20 12:30:37 -0400349#endif /* CONFIG_SYS_UCC_RGMII_MODE */
350#endif /* CONFIG_UEC_ETH3 */
Haiying Wangdf1bbbd2009-05-20 12:30:36 -0400351
352#define CONFIG_UEC_ETH4 /* GETH4 */
353#define CONFIG_HAS_ETH3
354
355#ifdef CONFIG_UEC_ETH4
356#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
357#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
Haiying Wangbc759ee2009-05-20 12:30:37 -0400358#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wangdf1bbbd2009-05-20 12:30:36 -0400359#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
360#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
361#define CONFIG_SYS_UEC4_PHY_ADDR 3
Andy Fleming7832a462011-04-13 00:37:12 -0500362#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100363#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
Haiying Wangbc759ee2009-05-20 12:30:37 -0400364#elif defined(CONFIG_SYS_UCC_RMII_MODE)
365#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
366#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
367#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
Andy Fleming7832a462011-04-13 00:37:12 -0500368#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100369#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
Haiying Wangbc759ee2009-05-20 12:30:37 -0400370#endif /* CONFIG_SYS_UCC_RGMII_MODE */
371#endif /* CONFIG_UEC_ETH4 */
Haiying Wang10b981b2009-05-20 12:30:41 -0400372
373#undef CONFIG_UEC_ETH6 /* GETH6 */
374#define CONFIG_HAS_ETH5
375
376#ifdef CONFIG_UEC_ETH6
377#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
378#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
379#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
380#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
381#define CONFIG_SYS_UEC6_PHY_ADDR 4
Andy Fleming7832a462011-04-13 00:37:12 -0500382#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100383#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
Haiying Wang10b981b2009-05-20 12:30:41 -0400384#endif /* CONFIG_UEC_ETH6 */
385
386#undef CONFIG_UEC_ETH8 /* GETH8 */
387#define CONFIG_HAS_ETH7
388
389#ifdef CONFIG_UEC_ETH8
390#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
391#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
392#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
393#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
394#define CONFIG_SYS_UEC8_PHY_ADDR 6
Andy Fleming7832a462011-04-13 00:37:12 -0500395#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100396#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
Haiying Wang10b981b2009-05-20 12:30:41 -0400397#endif /* CONFIG_UEC_ETH8 */
398
Haiying Wangbd255372009-03-27 17:02:45 -0400399#endif /* CONFIG_QE */
400
401#if defined(CONFIG_PCI)
Haiying Wangbd255372009-03-27 17:02:45 -0400402#undef CONFIG_EEPRO100
403#undef CONFIG_TULIP
404
405#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
406
407#endif /* CONFIG_PCI */
408
Haiying Wangbd255372009-03-27 17:02:45 -0400409/*
410 * Environment
411 */
Liu Yu2639e512010-01-18 19:03:28 +0800412#if defined(CONFIG_SYS_RAMBOOT)
Liu Yu2639e512010-01-18 19:03:28 +0800413#else
Haiying Wangb228ae62009-06-04 16:12:39 -0400414#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Haiying Wangbd76d192010-09-29 13:44:14 -0400415#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
416#define CONFIG_ENV_SIZE 0x2000
Liu Yu2639e512010-01-18 19:03:28 +0800417#endif
Haiying Wangbd255372009-03-27 17:02:45 -0400418
419#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
420#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
421
422/* QE microcode/firmware address */
Zhao Qiang83a90842014-03-21 16:21:44 +0800423#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
Haiying Wangbd255372009-03-27 17:02:45 -0400424
425/*
426 * BOOTP options
427 */
428#define CONFIG_BOOTP_BOOTFILESIZE
Haiying Wangbd255372009-03-27 17:02:45 -0400429
Haiying Wangbd255372009-03-27 17:02:45 -0400430#undef CONFIG_WATCHDOG /* watchdog disabled */
431
Anton Vorontsovda225942009-10-15 17:47:06 +0400432#ifdef CONFIG_MMC
Chenhui Zhao025eab02011-01-04 17:23:05 +0800433#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovda225942009-10-15 17:47:06 +0400434#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Anton Vorontsovda225942009-10-15 17:47:06 +0400435#endif
436
Haiying Wangbd255372009-03-27 17:02:45 -0400437/*
438 * Miscellaneous configurable options
439 */
Haiying Wangbd255372009-03-27 17:02:45 -0400440#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Haiying Wangbd255372009-03-27 17:02:45 -0400441#if defined(CONFIG_CMD_KGDB)
442#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
443#else
444#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
445#endif
Haiying Wangbd255372009-03-27 17:02:45 -0400446#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
447#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
448 /* Boot Argument Buffer Size */
Haiying Wangbd255372009-03-27 17:02:45 -0400449
450/*
451 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500452 * have to be in the first 64 MB of memory, since this is
Haiying Wangbd255372009-03-27 17:02:45 -0400453 * the maximum mapped by the Linux kernel during initialization.
454 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500455#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
456#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Haiying Wangbd255372009-03-27 17:02:45 -0400457
Haiying Wangbd255372009-03-27 17:02:45 -0400458#if defined(CONFIG_CMD_KGDB)
459#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Haiying Wangbd255372009-03-27 17:02:45 -0400460#endif
461
462/*
463 * Environment Configuration
464 */
Mario Six790d8442018-03-28 14:38:20 +0200465#define CONFIG_HOSTNAME "mpc8569mds"
Joe Hershberger257ff782011-10-13 13:03:47 +0000466#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000467#define CONFIG_BOOTFILE "your.uImage"
Haiying Wangbd255372009-03-27 17:02:45 -0400468
469#define CONFIG_SERVERIP 192.168.1.1
470#define CONFIG_GATEWAYIP 192.168.1.1
471#define CONFIG_NETMASK 255.255.255.0
472
473#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
474
Haiying Wangbd255372009-03-27 17:02:45 -0400475#define CONFIG_EXTRA_ENV_SETTINGS \
476 "netdev=eth0\0" \
477 "consoledev=ttyS0\0" \
478 "ramdiskaddr=600000\0" \
479 "ramdiskfile=your.ramdisk.u-boot\0" \
480 "fdtaddr=400000\0" \
481 "fdtfile=your.fdt.dtb\0" \
482 "nfsargs=setenv bootargs root=/dev/nfs rw " \
483 "nfsroot=$serverip:$rootpath " \
484 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
485 "console=$consoledev,$baudrate $othbootargs\0" \
486 "ramargs=setenv bootargs root=/dev/ram rw " \
487 "console=$consoledev,$baudrate $othbootargs\0" \
488
489#define CONFIG_NFSBOOTCOMMAND \
490 "run nfsargs;" \
491 "tftp $loadaddr $bootfile;" \
492 "tftp $fdtaddr $fdtfile;" \
493 "bootm $loadaddr - $fdtaddr"
494
495#define CONFIG_RAMBOOTCOMMAND \
496 "run ramargs;" \
497 "tftp $ramdiskaddr $ramdiskfile;" \
498 "tftp $loadaddr $bootfile;" \
499 "bootm $loadaddr $ramdiskaddr"
500
501#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
502
503#endif /* __CONFIG_H */