| Neil Armstrong | add986c | 2018-07-24 17:45:28 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Amlogic Meson Video Processing Unit driver |
| 4 | * |
| 5 | * Copyright (c) 2018 BayLibre, SAS. |
| 6 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __MESON_VPU_H__ |
| 10 | #define __MESON_VPU_H__ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <dm.h> |
| 14 | #include <video.h> |
| 15 | #include <display.h> |
| 16 | #include <linux/io.h> |
| 17 | #include "meson_registers.h" |
| 18 | |
| 19 | enum { |
| 20 | /* Maximum size we support */ |
| 21 | VPU_MAX_WIDTH = 3840, |
| 22 | VPU_MAX_HEIGHT = 2160, |
| 23 | VPU_MAX_LOG2_BPP = VIDEO_BPP32, |
| 24 | }; |
| 25 | |
| 26 | enum vpu_compatible { |
| 27 | VPU_COMPATIBLE_GXBB = 0, |
| 28 | VPU_COMPATIBLE_GXL = 1, |
| 29 | VPU_COMPATIBLE_GXM = 2, |
| 30 | }; |
| 31 | |
| 32 | struct meson_vpu_priv { |
| 33 | struct udevice *dev; |
| 34 | void __iomem *io_base; |
| 35 | void __iomem *hhi_base; |
| 36 | void __iomem *dmc_base; |
| 37 | }; |
| 38 | |
| 39 | static inline bool meson_vpu_is_compatible(struct meson_vpu_priv *priv, |
| 40 | enum vpu_compatible family) |
| 41 | { |
| 42 | enum vpu_compatible compat = dev_get_driver_data(priv->dev); |
| 43 | |
| 44 | return compat == family; |
| 45 | } |
| 46 | |
| 47 | #define hhi_update_bits(offset, mask, value) \ |
| 48 | writel_bits(mask, value, priv->hhi_base + offset) |
| 49 | |
| 50 | #define hhi_write(offset, value) \ |
| 51 | writel(value, priv->hhi_base + offset) |
| 52 | |
| 53 | #define hhi_read(offset) \ |
| 54 | readl(priv->hhi_base + offset) |
| 55 | |
| 56 | #define dmc_update_bits(offset, mask, value) \ |
| 57 | writel_bits(mask, value, priv->dmc_base + offset) |
| 58 | |
| 59 | #define dmc_write(offset, value) \ |
| 60 | writel(value, priv->dmc_base + offset) |
| 61 | |
| 62 | #define dmc_read(offset) \ |
| 63 | readl(priv->dmc_base + offset) |
| 64 | |
| 65 | #define MESON_CANVAS_ID_OSD1 0x4e |
| 66 | |
| 67 | /* Canvas configuration. */ |
| 68 | #define MESON_CANVAS_WRAP_NONE 0x00 |
| 69 | #define MESON_CANVAS_WRAP_X 0x01 |
| 70 | #define MESON_CANVAS_WRAP_Y 0x02 |
| 71 | |
| 72 | #define MESON_CANVAS_BLKMODE_LINEAR 0x00 |
| 73 | #define MESON_CANVAS_BLKMODE_32x32 0x01 |
| 74 | #define MESON_CANVAS_BLKMODE_64x64 0x02 |
| 75 | |
| 76 | void meson_canvas_setup(struct meson_vpu_priv *priv, |
| 77 | u32 canvas_index, u32 addr, |
| 78 | u32 stride, u32 height, |
| 79 | unsigned int wrap, |
| 80 | unsigned int blkmode); |
| 81 | |
| 82 | /* Mux VIU/VPP to ENCI */ |
| 83 | #define MESON_VIU_VPP_MUX_ENCI 0x5 |
| 84 | /* Mux VIU/VPP to ENCP */ |
| 85 | #define MESON_VIU_VPP_MUX_ENCP 0xA |
| 86 | |
| 87 | void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux); |
| 88 | void meson_vpu_init(struct udevice *dev); |
| 89 | void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced); |
| 90 | bool meson_venc_hdmi_supported_mode(const struct display_timing *mode); |
| 91 | void meson_vpu_setup_venc(struct udevice *dev, |
| 92 | const struct display_timing *mode, bool is_cvbs); |
| 93 | bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv, |
| 94 | unsigned int freq); |
| 95 | void meson_vpu_setup_vclk(struct udevice *dev, |
| 96 | const struct display_timing *mode, bool is_cvbs); |
| 97 | #endif |