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git01.mediatek.com / filogic / uboot / 019a50405b9fd9b86dcb8eb279754f0f3df47689 / . / arch / mips / mach-octeon / include / mach / cvmx-bgxx-defs.h
blob: 7bcf805827b5f49967fa44d302b93d37721c76ed [file] [log] [blame]
Aaron Williams7fa6c4c2020-12-11 17:05:27 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon bgxx.
7 */
8
9#ifndef __CVMX_BGXX_DEFS_H__
10#define __CVMX_BGXX_DEFS_H__
11
12#define CVMX_BGXX_CMRX_CONFIG(offset, block_id) \
13 (0x00011800E0000000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
14#define CVMX_BGXX_CMRX_INT(offset, block_id) \
15 (0x00011800E0000020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
16#define CVMX_BGXX_CMRX_PRT_CBFC_CTL(offset, block_id) \
17 (0x00011800E0000408ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
18#define CVMX_BGXX_CMRX_RX_ADR_CTL(offset, block_id) \
19 (0x00011800E00000A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
20#define CVMX_BGXX_CMRX_RX_BP_DROP(offset, block_id) \
21 (0x00011800E0000080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
22#define CVMX_BGXX_CMRX_RX_BP_OFF(offset, block_id) \
23 (0x00011800E0000090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
24#define CVMX_BGXX_CMRX_RX_BP_ON(offset, block_id) \
25 (0x00011800E0000088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
26#define CVMX_BGXX_CMRX_RX_BP_STATUS(offset, block_id) \
27 (0x00011800E00000A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
28#define CVMX_BGXX_CMRX_RX_FIFO_LEN(offset, block_id) \
29 (0x00011800E00000C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
30#define CVMX_BGXX_CMRX_RX_ID_MAP(offset, block_id) \
31 (0x00011800E0000028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
32#define CVMX_BGXX_CMRX_RX_LOGL_XOFF(offset, block_id) \
33 (0x00011800E00000B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
34#define CVMX_BGXX_CMRX_RX_LOGL_XON(offset, block_id) \
35 (0x00011800E00000B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
36#define CVMX_BGXX_CMRX_RX_PAUSE_DROP_TIME(offset, block_id) \
37 (0x00011800E0000030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
38#define CVMX_BGXX_CMRX_RX_STAT0(offset, block_id) \
39 (0x00011800E0000038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
40#define CVMX_BGXX_CMRX_RX_STAT1(offset, block_id) \
41 (0x00011800E0000040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
42#define CVMX_BGXX_CMRX_RX_STAT2(offset, block_id) \
43 (0x00011800E0000048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
44#define CVMX_BGXX_CMRX_RX_STAT3(offset, block_id) \
45 (0x00011800E0000050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
46#define CVMX_BGXX_CMRX_RX_STAT4(offset, block_id) \
47 (0x00011800E0000058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
48#define CVMX_BGXX_CMRX_RX_STAT5(offset, block_id) \
49 (0x00011800E0000060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
50#define CVMX_BGXX_CMRX_RX_STAT6(offset, block_id) \
51 (0x00011800E0000068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
52#define CVMX_BGXX_CMRX_RX_STAT7(offset, block_id) \
53 (0x00011800E0000070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
54#define CVMX_BGXX_CMRX_RX_STAT8(offset, block_id) \
55 (0x00011800E0000078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
56#define CVMX_BGXX_CMRX_RX_WEIGHT(offset, block_id) \
57 (0x00011800E0000098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
58#define CVMX_BGXX_CMRX_TX_CHANNEL(offset, block_id) \
59 (0x00011800E0000400ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
60#define CVMX_BGXX_CMRX_TX_FIFO_LEN(offset, block_id) \
61 (0x00011800E0000418ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
62#define CVMX_BGXX_CMRX_TX_HG2_STATUS(offset, block_id) \
63 (0x00011800E0000410ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
64#define CVMX_BGXX_CMRX_TX_OVR_BP(offset, block_id) \
65 (0x00011800E0000420ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
66#define CVMX_BGXX_CMRX_TX_STAT0(offset, block_id) \
67 (0x00011800E0000508ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
68#define CVMX_BGXX_CMRX_TX_STAT1(offset, block_id) \
69 (0x00011800E0000510ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
70#define CVMX_BGXX_CMRX_TX_STAT10(offset, block_id) \
71 (0x00011800E0000558ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
72#define CVMX_BGXX_CMRX_TX_STAT11(offset, block_id) \
73 (0x00011800E0000560ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
74#define CVMX_BGXX_CMRX_TX_STAT12(offset, block_id) \
75 (0x00011800E0000568ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
76#define CVMX_BGXX_CMRX_TX_STAT13(offset, block_id) \
77 (0x00011800E0000570ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
78#define CVMX_BGXX_CMRX_TX_STAT14(offset, block_id) \
79 (0x00011800E0000578ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
80#define CVMX_BGXX_CMRX_TX_STAT15(offset, block_id) \
81 (0x00011800E0000580ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
82#define CVMX_BGXX_CMRX_TX_STAT16(offset, block_id) \
83 (0x00011800E0000588ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
84#define CVMX_BGXX_CMRX_TX_STAT17(offset, block_id) \
85 (0x00011800E0000590ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
86#define CVMX_BGXX_CMRX_TX_STAT2(offset, block_id) \
87 (0x00011800E0000518ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
88#define CVMX_BGXX_CMRX_TX_STAT3(offset, block_id) \
89 (0x00011800E0000520ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
90#define CVMX_BGXX_CMRX_TX_STAT4(offset, block_id) \
91 (0x00011800E0000528ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
92#define CVMX_BGXX_CMRX_TX_STAT5(offset, block_id) \
93 (0x00011800E0000530ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
94#define CVMX_BGXX_CMRX_TX_STAT6(offset, block_id) \
95 (0x00011800E0000538ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
96#define CVMX_BGXX_CMRX_TX_STAT7(offset, block_id) \
97 (0x00011800E0000540ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
98#define CVMX_BGXX_CMRX_TX_STAT8(offset, block_id) \
99 (0x00011800E0000548ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
100#define CVMX_BGXX_CMRX_TX_STAT9(offset, block_id) \
101 (0x00011800E0000550ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
102#define CVMX_BGXX_CMR_BAD(offset) (0x00011800E0001020ull + ((offset) & 7) * 0x1000000ull)
103#define CVMX_BGXX_CMR_BIST_STATUS(offset) (0x00011800E0000300ull + ((offset) & 7) * 0x1000000ull)
104#define CVMX_BGXX_CMR_CHAN_MSK_AND(offset) (0x00011800E0000200ull + ((offset) & 7) * 0x1000000ull)
105#define CVMX_BGXX_CMR_CHAN_MSK_OR(offset) (0x00011800E0000208ull + ((offset) & 7) * 0x1000000ull)
106#define CVMX_BGXX_CMR_ECO(offset) (0x00011800E0001028ull + ((offset) & 7) * 0x1000000ull)
107#define CVMX_BGXX_CMR_GLOBAL_CONFIG(offset) (0x00011800E0000008ull + ((offset) & 7) * 0x1000000ull)
108#define CVMX_BGXX_CMR_MEM_CTRL(offset) (0x00011800E0000018ull + ((offset) & 7) * 0x1000000ull)
109#define CVMX_BGXX_CMR_MEM_INT(offset) (0x00011800E0000010ull + ((offset) & 7) * 0x1000000ull)
110#define CVMX_BGXX_CMR_NXC_ADR(offset) (0x00011800E0001018ull + ((offset) & 7) * 0x1000000ull)
111#define CVMX_BGXX_CMR_RX_ADRX_CAM(offset, block_id) \
112 (0x00011800E0000100ull + (((offset) & 31) + ((block_id) & 7) * 0x200000ull) * 8)
113#define CVMX_BGXX_CMR_RX_LMACS(offset) (0x00011800E0000308ull + ((offset) & 7) * 0x1000000ull)
114#define CVMX_BGXX_CMR_RX_OVR_BP(offset) (0x00011800E0000318ull + ((offset) & 7) * 0x1000000ull)
115#define CVMX_BGXX_CMR_TX_LMACS(offset) (0x00011800E0001000ull + ((offset) & 7) * 0x1000000ull)
116#define CVMX_BGXX_GMP_GMI_PRTX_CFG(offset, block_id) \
117 (0x00011800E0038010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
118#define CVMX_BGXX_GMP_GMI_RXX_DECISION(offset, block_id) \
119 (0x00011800E0038040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
120#define CVMX_BGXX_GMP_GMI_RXX_FRM_CHK(offset, block_id) \
121 (0x00011800E0038020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
122#define CVMX_BGXX_GMP_GMI_RXX_FRM_CTL(offset, block_id) \
123 (0x00011800E0038018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
124#define CVMX_BGXX_GMP_GMI_RXX_IFG(offset, block_id) \
125 (0x00011800E0038058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
126#define CVMX_BGXX_GMP_GMI_RXX_INT(offset, block_id) \
127 (0x00011800E0038000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
128#define CVMX_BGXX_GMP_GMI_RXX_JABBER(offset, block_id) \
129 (0x00011800E0038038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
130#define CVMX_BGXX_GMP_GMI_RXX_UDD_SKP(offset, block_id) \
131 (0x00011800E0038048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
132#define CVMX_BGXX_GMP_GMI_SMACX(offset, block_id) \
133 (0x00011800E0038230ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
134#define CVMX_BGXX_GMP_GMI_TXX_APPEND(offset, block_id) \
135 (0x00011800E0038218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
136#define CVMX_BGXX_GMP_GMI_TXX_BURST(offset, block_id) \
137 (0x00011800E0038228ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
138#define CVMX_BGXX_GMP_GMI_TXX_CTL(offset, block_id) \
139 (0x00011800E0038270ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
140#define CVMX_BGXX_GMP_GMI_TXX_INT(offset, block_id) \
141 (0x00011800E0038500ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
142#define CVMX_BGXX_GMP_GMI_TXX_MIN_PKT(offset, block_id) \
143 (0x00011800E0038240ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
144#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
145 (0x00011800E0038248ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
146#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(offset, block_id) \
147 (0x00011800E0038238ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
148#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_TOGO(offset, block_id) \
149 (0x00011800E0038258ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
150#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_ZERO(offset, block_id) \
151 (0x00011800E0038260ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
152#define CVMX_BGXX_GMP_GMI_TXX_SGMII_CTL(offset, block_id) \
153 (0x00011800E0038300ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
154#define CVMX_BGXX_GMP_GMI_TXX_SLOT(offset, block_id) \
155 (0x00011800E0038220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
156#define CVMX_BGXX_GMP_GMI_TXX_SOFT_PAUSE(offset, block_id) \
157 (0x00011800E0038250ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
158#define CVMX_BGXX_GMP_GMI_TXX_THRESH(offset, block_id) \
159 (0x00011800E0038210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
160#define CVMX_BGXX_GMP_GMI_TX_COL_ATTEMPT(offset) \
161 (0x00011800E0039010ull + ((offset) & 7) * 0x1000000ull)
162#define CVMX_BGXX_GMP_GMI_TX_IFG(offset) (0x00011800E0039000ull + ((offset) & 7) * 0x1000000ull)
163#define CVMX_BGXX_GMP_GMI_TX_JAM(offset) (0x00011800E0039008ull + ((offset) & 7) * 0x1000000ull)
164#define CVMX_BGXX_GMP_GMI_TX_LFSR(offset) (0x00011800E0039028ull + ((offset) & 7) * 0x1000000ull)
165#define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(offset) \
166 (0x00011800E0039018ull + ((offset) & 7) * 0x1000000ull)
167#define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(offset) \
168 (0x00011800E0039020ull + ((offset) & 7) * 0x1000000ull)
169#define CVMX_BGXX_GMP_PCS_ANX_ADV(offset, block_id) \
170 (0x00011800E0030010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
171#define CVMX_BGXX_GMP_PCS_ANX_EXT_ST(offset, block_id) \
172 (0x00011800E0030028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
173#define CVMX_BGXX_GMP_PCS_ANX_LP_ABIL(offset, block_id) \
174 (0x00011800E0030018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
175#define CVMX_BGXX_GMP_PCS_ANX_RESULTS(offset, block_id) \
176 (0x00011800E0030020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
177#define CVMX_BGXX_GMP_PCS_INTX(offset, block_id) \
178 (0x00011800E0030080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
179#define CVMX_BGXX_GMP_PCS_LINKX_TIMER(offset, block_id) \
180 (0x00011800E0030040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
181#define CVMX_BGXX_GMP_PCS_MISCX_CTL(offset, block_id) \
182 (0x00011800E0030078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
183#define CVMX_BGXX_GMP_PCS_MRX_CONTROL(offset, block_id) \
184 (0x00011800E0030000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
185#define CVMX_BGXX_GMP_PCS_MRX_STATUS(offset, block_id) \
186 (0x00011800E0030008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
187#define CVMX_BGXX_GMP_PCS_RXX_STATES(offset, block_id) \
188 (0x00011800E0030058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
189#define CVMX_BGXX_GMP_PCS_RXX_SYNC(offset, block_id) \
190 (0x00011800E0030050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
191#define CVMX_BGXX_GMP_PCS_SGMX_AN_ADV(offset, block_id) \
192 (0x00011800E0030068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
193#define CVMX_BGXX_GMP_PCS_SGMX_LP_ADV(offset, block_id) \
194 (0x00011800E0030070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
195#define CVMX_BGXX_GMP_PCS_TXX_STATES(offset, block_id) \
196 (0x00011800E0030060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
197#define CVMX_BGXX_GMP_PCS_TX_RXX_POLARITY(offset, block_id) \
198 (0x00011800E0030048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
199#define CVMX_BGXX_SMUX_CBFC_CTL(offset, block_id) \
200 (0x00011800E0020218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
201#define CVMX_BGXX_SMUX_CTRL(offset, block_id) \
202 (0x00011800E0020200ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
203#define CVMX_BGXX_SMUX_EXT_LOOPBACK(offset, block_id) \
204 (0x00011800E0020208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
205#define CVMX_BGXX_SMUX_HG2_CONTROL(offset, block_id) \
206 (0x00011800E0020210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
207#define CVMX_BGXX_SMUX_RX_BAD_COL_HI(offset, block_id) \
208 (0x00011800E0020040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
209#define CVMX_BGXX_SMUX_RX_BAD_COL_LO(offset, block_id) \
210 (0x00011800E0020038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
211#define CVMX_BGXX_SMUX_RX_CTL(offset, block_id) \
212 (0x00011800E0020030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
213#define CVMX_BGXX_SMUX_RX_DECISION(offset, block_id) \
214 (0x00011800E0020020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
215#define CVMX_BGXX_SMUX_RX_FRM_CHK(offset, block_id) \
216 (0x00011800E0020010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
217#define CVMX_BGXX_SMUX_RX_FRM_CTL(offset, block_id) \
218 (0x00011800E0020008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
219#define CVMX_BGXX_SMUX_RX_INT(offset, block_id) \
220 (0x00011800E0020000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
221#define CVMX_BGXX_SMUX_RX_JABBER(offset, block_id) \
222 (0x00011800E0020018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
223#define CVMX_BGXX_SMUX_RX_UDD_SKP(offset, block_id) \
224 (0x00011800E0020028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
225#define CVMX_BGXX_SMUX_SMAC(offset, block_id) \
226 (0x00011800E0020108ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
227#define CVMX_BGXX_SMUX_TX_APPEND(offset, block_id) \
228 (0x00011800E0020100ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
229#define CVMX_BGXX_SMUX_TX_CTL(offset, block_id) \
230 (0x00011800E0020160ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
231#define CVMX_BGXX_SMUX_TX_IFG(offset, block_id) \
232 (0x00011800E0020148ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
233#define CVMX_BGXX_SMUX_TX_INT(offset, block_id) \
234 (0x00011800E0020140ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
235#define CVMX_BGXX_SMUX_TX_MIN_PKT(offset, block_id) \
236 (0x00011800E0020118ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
237#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_DMAC(offset, block_id) \
238 (0x00011800E0020150ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
239#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(offset, block_id) \
240 (0x00011800E0020120ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
241#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TIME(offset, block_id) \
242 (0x00011800E0020110ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
243#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TYPE(offset, block_id) \
244 (0x00011800E0020158ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
245#define CVMX_BGXX_SMUX_TX_PAUSE_TOGO(offset, block_id) \
246 (0x00011800E0020130ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
247#define CVMX_BGXX_SMUX_TX_PAUSE_ZERO(offset, block_id) \
248 (0x00011800E0020138ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
249#define CVMX_BGXX_SMUX_TX_SOFT_PAUSE(offset, block_id) \
250 (0x00011800E0020128ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
251#define CVMX_BGXX_SMUX_TX_THRESH(offset, block_id) \
252 (0x00011800E0020168ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
253#define CVMX_BGXX_SPUX_AN_ADV(offset, block_id) \
254 (0x00011800E00100D8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
255#define CVMX_BGXX_SPUX_AN_BP_STATUS(offset, block_id) \
256 (0x00011800E00100F8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
257#define CVMX_BGXX_SPUX_AN_CONTROL(offset, block_id) \
258 (0x00011800E00100C8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
259#define CVMX_BGXX_SPUX_AN_LP_BASE(offset, block_id) \
260 (0x00011800E00100E0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
261#define CVMX_BGXX_SPUX_AN_LP_XNP(offset, block_id) \
262 (0x00011800E00100F0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
263#define CVMX_BGXX_SPUX_AN_STATUS(offset, block_id) \
264 (0x00011800E00100D0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
265#define CVMX_BGXX_SPUX_AN_XNP_TX(offset, block_id) \
266 (0x00011800E00100E8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
267#define CVMX_BGXX_SPUX_BR_ALGN_STATUS(offset, block_id) \
268 (0x00011800E0010050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
269#define CVMX_BGXX_SPUX_BR_BIP_ERR_CNT(offset, block_id) \
270 (0x00011800E0010058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
271#define CVMX_BGXX_SPUX_BR_LANE_MAP(offset, block_id) \
272 (0x00011800E0010060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
273#define CVMX_BGXX_SPUX_BR_PMD_CONTROL(offset, block_id) \
274 (0x00011800E0010068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
275#define CVMX_BGXX_SPUX_BR_PMD_LD_CUP(offset, block_id) \
276 (0x00011800E0010088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
277#define CVMX_BGXX_SPUX_BR_PMD_LD_REP(offset, block_id) \
278 (0x00011800E0010090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
279#define CVMX_BGXX_SPUX_BR_PMD_LP_CUP(offset, block_id) \
280 (0x00011800E0010078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
281#define CVMX_BGXX_SPUX_BR_PMD_LP_REP(offset, block_id) \
282 (0x00011800E0010080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
283#define CVMX_BGXX_SPUX_BR_PMD_STATUS(offset, block_id) \
284 (0x00011800E0010070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
285#define CVMX_BGXX_SPUX_BR_STATUS1(offset, block_id) \
286 (0x00011800E0010030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
287#define CVMX_BGXX_SPUX_BR_STATUS2(offset, block_id) \
288 (0x00011800E0010038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
289#define CVMX_BGXX_SPUX_BR_TP_CONTROL(offset, block_id) \
290 (0x00011800E0010040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
291#define CVMX_BGXX_SPUX_BR_TP_ERR_CNT(offset, block_id) \
292 (0x00011800E0010048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
293#define CVMX_BGXX_SPUX_BX_STATUS(offset, block_id) \
294 (0x00011800E0010028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
295#define CVMX_BGXX_SPUX_CONTROL1(offset, block_id) \
296 (0x00011800E0010000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
297#define CVMX_BGXX_SPUX_CONTROL2(offset, block_id) \
298 (0x00011800E0010018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
299#define CVMX_BGXX_SPUX_FEC_ABIL(offset, block_id) \
300 (0x00011800E0010098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
301#define CVMX_BGXX_SPUX_FEC_CONTROL(offset, block_id) \
302 (0x00011800E00100A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
303#define CVMX_BGXX_SPUX_FEC_CORR_BLKS01(offset, block_id) \
304 (0x00011800E00100A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
305#define CVMX_BGXX_SPUX_FEC_CORR_BLKS23(offset, block_id) \
306 (0x00011800E00100B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
307#define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS01(offset, block_id) \
308 (0x00011800E00100B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
309#define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS23(offset, block_id) \
310 (0x00011800E00100C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
311#define CVMX_BGXX_SPUX_INT(offset, block_id) \
312 (0x00011800E0010220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
313#define CVMX_BGXX_SPUX_LPCS_STATES(offset, block_id) \
314 (0x00011800E0010208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
315#define CVMX_BGXX_SPUX_MISC_CONTROL(offset, block_id) \
316 (0x00011800E0010218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
317#define CVMX_BGXX_SPUX_SPD_ABIL(offset, block_id) \
318 (0x00011800E0010010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
319#define CVMX_BGXX_SPUX_STATUS1(offset, block_id) \
320 (0x00011800E0010008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
321#define CVMX_BGXX_SPUX_STATUS2(offset, block_id) \
322 (0x00011800E0010020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
323#define CVMX_BGXX_SPU_BIST_STATUS(offset) (0x00011800E0010318ull + ((offset) & 7) * 0x1000000ull)
324#define CVMX_BGXX_SPU_DBG_CONTROL(offset) (0x00011800E0010300ull + ((offset) & 7) * 0x1000000ull)
325#define CVMX_BGXX_SPU_MEM_INT(offset) (0x00011800E0010310ull + ((offset) & 7) * 0x1000000ull)
326#define CVMX_BGXX_SPU_MEM_STATUS(offset) (0x00011800E0010308ull + ((offset) & 7) * 0x1000000ull)
327#define CVMX_BGXX_SPU_SDSX_SKEW_STATUS(offset, block_id) \
328 (0x00011800E0010320ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)
329#define CVMX_BGXX_SPU_SDSX_STATES(offset, block_id) \
330 (0x00011800E0010340ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)
331
332/**
333 * cvmx_bgx#_cmr#_config
334 *
335 * Logical MAC/PCS configuration registers; one per LMAC. The maximum number of LMACs (and
336 * maximum LMAC ID) that can be enabled by these registers is limited by
337 * BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. When multiple LMACs are
338 * enabled, they must be configured with the same [LMAC_TYPE] value.
339 */
340union cvmx_bgxx_cmrx_config {
341 u64 u64;
342 struct cvmx_bgxx_cmrx_config_s {
343 u64 reserved_16_63 : 48;
344 u64 enable : 1;
345 u64 data_pkt_rx_en : 1;
346 u64 data_pkt_tx_en : 1;
347 u64 int_beat_gen : 1;
348 u64 mix_en : 1;
349 u64 lmac_type : 3;
350 u64 lane_to_sds : 8;
351 } s;
352 struct cvmx_bgxx_cmrx_config_s cn73xx;
353 struct cvmx_bgxx_cmrx_config_s cn78xx;
354 struct cvmx_bgxx_cmrx_config_s cn78xxp1;
355 struct cvmx_bgxx_cmrx_config_s cnf75xx;
356};
357
358typedef union cvmx_bgxx_cmrx_config cvmx_bgxx_cmrx_config_t;
359
360/**
361 * cvmx_bgx#_cmr#_int
362 */
363union cvmx_bgxx_cmrx_int {
364 u64 u64;
365 struct cvmx_bgxx_cmrx_int_s {
366 u64 reserved_3_63 : 61;
367 u64 pko_nxc : 1;
368 u64 overflw : 1;
369 u64 pause_drp : 1;
370 } s;
371 struct cvmx_bgxx_cmrx_int_s cn73xx;
372 struct cvmx_bgxx_cmrx_int_s cn78xx;
373 struct cvmx_bgxx_cmrx_int_s cn78xxp1;
374 struct cvmx_bgxx_cmrx_int_s cnf75xx;
375};
376
377typedef union cvmx_bgxx_cmrx_int cvmx_bgxx_cmrx_int_t;
378
379/**
380 * cvmx_bgx#_cmr#_prt_cbfc_ctl
381 *
382 * See XOFF definition listed under BGX()_SMU()_CBFC_CTL.
383 *
384 */
385union cvmx_bgxx_cmrx_prt_cbfc_ctl {
386 u64 u64;
387 struct cvmx_bgxx_cmrx_prt_cbfc_ctl_s {
388 u64 reserved_32_63 : 32;
389 u64 phys_bp : 16;
390 u64 reserved_0_15 : 16;
391 } s;
392 struct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn73xx;
393 struct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn78xx;
394 struct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn78xxp1;
395 struct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cnf75xx;
396};
397
398typedef union cvmx_bgxx_cmrx_prt_cbfc_ctl cvmx_bgxx_cmrx_prt_cbfc_ctl_t;
399
400/**
401 * cvmx_bgx#_cmr#_rx_adr_ctl
402 */
403union cvmx_bgxx_cmrx_rx_adr_ctl {
404 u64 u64;
405 struct cvmx_bgxx_cmrx_rx_adr_ctl_s {
406 u64 reserved_4_63 : 60;
407 u64 cam_accept : 1;
408 u64 mcst_mode : 2;
409 u64 bcst_accept : 1;
410 } s;
411 struct cvmx_bgxx_cmrx_rx_adr_ctl_s cn73xx;
412 struct cvmx_bgxx_cmrx_rx_adr_ctl_s cn78xx;
413 struct cvmx_bgxx_cmrx_rx_adr_ctl_s cn78xxp1;
414 struct cvmx_bgxx_cmrx_rx_adr_ctl_s cnf75xx;
415};
416
417typedef union cvmx_bgxx_cmrx_rx_adr_ctl cvmx_bgxx_cmrx_rx_adr_ctl_t;
418
419/**
420 * cvmx_bgx#_cmr#_rx_bp_drop
421 */
422union cvmx_bgxx_cmrx_rx_bp_drop {
423 u64 u64;
424 struct cvmx_bgxx_cmrx_rx_bp_drop_s {
425 u64 reserved_7_63 : 57;
426 u64 mark : 7;
427 } s;
428 struct cvmx_bgxx_cmrx_rx_bp_drop_s cn73xx;
429 struct cvmx_bgxx_cmrx_rx_bp_drop_s cn78xx;
430 struct cvmx_bgxx_cmrx_rx_bp_drop_s cn78xxp1;
431 struct cvmx_bgxx_cmrx_rx_bp_drop_s cnf75xx;
432};
433
434typedef union cvmx_bgxx_cmrx_rx_bp_drop cvmx_bgxx_cmrx_rx_bp_drop_t;
435
436/**
437 * cvmx_bgx#_cmr#_rx_bp_off
438 */
439union cvmx_bgxx_cmrx_rx_bp_off {
440 u64 u64;
441 struct cvmx_bgxx_cmrx_rx_bp_off_s {
442 u64 reserved_7_63 : 57;
443 u64 mark : 7;
444 } s;
445 struct cvmx_bgxx_cmrx_rx_bp_off_s cn73xx;
446 struct cvmx_bgxx_cmrx_rx_bp_off_s cn78xx;
447 struct cvmx_bgxx_cmrx_rx_bp_off_s cn78xxp1;
448 struct cvmx_bgxx_cmrx_rx_bp_off_s cnf75xx;
449};
450
451typedef union cvmx_bgxx_cmrx_rx_bp_off cvmx_bgxx_cmrx_rx_bp_off_t;
452
453/**
454 * cvmx_bgx#_cmr#_rx_bp_on
455 */
456union cvmx_bgxx_cmrx_rx_bp_on {
457 u64 u64;
458 struct cvmx_bgxx_cmrx_rx_bp_on_s {
459 u64 reserved_12_63 : 52;
460 u64 mark : 12;
461 } s;
462 struct cvmx_bgxx_cmrx_rx_bp_on_s cn73xx;
463 struct cvmx_bgxx_cmrx_rx_bp_on_s cn78xx;
464 struct cvmx_bgxx_cmrx_rx_bp_on_s cn78xxp1;
465 struct cvmx_bgxx_cmrx_rx_bp_on_s cnf75xx;
466};
467
468typedef union cvmx_bgxx_cmrx_rx_bp_on cvmx_bgxx_cmrx_rx_bp_on_t;
469
470/**
471 * cvmx_bgx#_cmr#_rx_bp_status
472 */
473union cvmx_bgxx_cmrx_rx_bp_status {
474 u64 u64;
475 struct cvmx_bgxx_cmrx_rx_bp_status_s {
476 u64 reserved_1_63 : 63;
477 u64 bp : 1;
478 } s;
479 struct cvmx_bgxx_cmrx_rx_bp_status_s cn73xx;
480 struct cvmx_bgxx_cmrx_rx_bp_status_s cn78xx;
481 struct cvmx_bgxx_cmrx_rx_bp_status_s cn78xxp1;
482 struct cvmx_bgxx_cmrx_rx_bp_status_s cnf75xx;
483};
484
485typedef union cvmx_bgxx_cmrx_rx_bp_status cvmx_bgxx_cmrx_rx_bp_status_t;
486
487/**
488 * cvmx_bgx#_cmr#_rx_fifo_len
489 */
490union cvmx_bgxx_cmrx_rx_fifo_len {
491 u64 u64;
492 struct cvmx_bgxx_cmrx_rx_fifo_len_s {
493 u64 reserved_13_63 : 51;
494 u64 fifo_len : 13;
495 } s;
496 struct cvmx_bgxx_cmrx_rx_fifo_len_s cn73xx;
497 struct cvmx_bgxx_cmrx_rx_fifo_len_s cn78xx;
498 struct cvmx_bgxx_cmrx_rx_fifo_len_s cn78xxp1;
499 struct cvmx_bgxx_cmrx_rx_fifo_len_s cnf75xx;
500};
501
502typedef union cvmx_bgxx_cmrx_rx_fifo_len cvmx_bgxx_cmrx_rx_fifo_len_t;
503
504/**
505 * cvmx_bgx#_cmr#_rx_id_map
506 *
507 * These registers set the RX LMAC ID mapping for X2P/PKI.
508 *
509 */
510union cvmx_bgxx_cmrx_rx_id_map {
511 u64 u64;
512 struct cvmx_bgxx_cmrx_rx_id_map_s {
513 u64 reserved_15_63 : 49;
514 u64 rid : 7;
515 u64 pknd : 8;
516 } s;
517 struct cvmx_bgxx_cmrx_rx_id_map_cn73xx {
518 u64 reserved_15_63 : 49;
519 u64 rid : 7;
520 u64 reserved_6_7 : 2;
521 u64 pknd : 6;
522 } cn73xx;
523 struct cvmx_bgxx_cmrx_rx_id_map_cn73xx cn78xx;
524 struct cvmx_bgxx_cmrx_rx_id_map_s cn78xxp1;
525 struct cvmx_bgxx_cmrx_rx_id_map_cn73xx cnf75xx;
526};
527
528typedef union cvmx_bgxx_cmrx_rx_id_map cvmx_bgxx_cmrx_rx_id_map_t;
529
530/**
531 * cvmx_bgx#_cmr#_rx_logl_xoff
532 */
533union cvmx_bgxx_cmrx_rx_logl_xoff {
534 u64 u64;
535 struct cvmx_bgxx_cmrx_rx_logl_xoff_s {
536 u64 reserved_16_63 : 48;
537 u64 xoff : 16;
538 } s;
539 struct cvmx_bgxx_cmrx_rx_logl_xoff_s cn73xx;
540 struct cvmx_bgxx_cmrx_rx_logl_xoff_s cn78xx;
541 struct cvmx_bgxx_cmrx_rx_logl_xoff_s cn78xxp1;
542 struct cvmx_bgxx_cmrx_rx_logl_xoff_s cnf75xx;
543};
544
545typedef union cvmx_bgxx_cmrx_rx_logl_xoff cvmx_bgxx_cmrx_rx_logl_xoff_t;
546
547/**
548 * cvmx_bgx#_cmr#_rx_logl_xon
549 */
550union cvmx_bgxx_cmrx_rx_logl_xon {
551 u64 u64;
552 struct cvmx_bgxx_cmrx_rx_logl_xon_s {
553 u64 reserved_16_63 : 48;
554 u64 xon : 16;
555 } s;
556 struct cvmx_bgxx_cmrx_rx_logl_xon_s cn73xx;
557 struct cvmx_bgxx_cmrx_rx_logl_xon_s cn78xx;
558 struct cvmx_bgxx_cmrx_rx_logl_xon_s cn78xxp1;
559 struct cvmx_bgxx_cmrx_rx_logl_xon_s cnf75xx;
560};
561
562typedef union cvmx_bgxx_cmrx_rx_logl_xon cvmx_bgxx_cmrx_rx_logl_xon_t;
563
564/**
565 * cvmx_bgx#_cmr#_rx_pause_drop_time
566 */
567union cvmx_bgxx_cmrx_rx_pause_drop_time {
568 u64 u64;
569 struct cvmx_bgxx_cmrx_rx_pause_drop_time_s {
570 u64 reserved_16_63 : 48;
571 u64 pause_time : 16;
572 } s;
573 struct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn73xx;
574 struct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn78xx;
575 struct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn78xxp1;
576 struct cvmx_bgxx_cmrx_rx_pause_drop_time_s cnf75xx;
577};
578
579typedef union cvmx_bgxx_cmrx_rx_pause_drop_time cvmx_bgxx_cmrx_rx_pause_drop_time_t;
580
581/**
582 * cvmx_bgx#_cmr#_rx_stat0
583 *
584 * These registers provide a count of received packets that meet the following conditions:
585 * * are not recognized as PAUSE packets.
586 * * are not dropped due DMAC filtering.
587 * * are not dropped due FIFO full status.
588 * * do not have any other OPCODE (FCS, Length, etc).
589 */
590union cvmx_bgxx_cmrx_rx_stat0 {
591 u64 u64;
592 struct cvmx_bgxx_cmrx_rx_stat0_s {
593 u64 reserved_48_63 : 16;
594 u64 cnt : 48;
595 } s;
596 struct cvmx_bgxx_cmrx_rx_stat0_s cn73xx;
597 struct cvmx_bgxx_cmrx_rx_stat0_s cn78xx;
598 struct cvmx_bgxx_cmrx_rx_stat0_s cn78xxp1;
599 struct cvmx_bgxx_cmrx_rx_stat0_s cnf75xx;
600};
601
602typedef union cvmx_bgxx_cmrx_rx_stat0 cvmx_bgxx_cmrx_rx_stat0_t;
603
604/**
605 * cvmx_bgx#_cmr#_rx_stat1
606 *
607 * These registers provide a count of octets of received packets.
608 *
609 */
610union cvmx_bgxx_cmrx_rx_stat1 {
611 u64 u64;
612 struct cvmx_bgxx_cmrx_rx_stat1_s {
613 u64 reserved_48_63 : 16;
614 u64 cnt : 48;
615 } s;
616 struct cvmx_bgxx_cmrx_rx_stat1_s cn73xx;
617 struct cvmx_bgxx_cmrx_rx_stat1_s cn78xx;
618 struct cvmx_bgxx_cmrx_rx_stat1_s cn78xxp1;
619 struct cvmx_bgxx_cmrx_rx_stat1_s cnf75xx;
620};
621
622typedef union cvmx_bgxx_cmrx_rx_stat1 cvmx_bgxx_cmrx_rx_stat1_t;
623
624/**
625 * cvmx_bgx#_cmr#_rx_stat2
626 *
627 * These registers provide a count of all packets received that were recognized as flow-control
628 * or PAUSE packets. PAUSE packets with any kind of error are counted in
629 * BGX()_CMR()_RX_STAT8 (error stats register). Pause packets can be optionally dropped
630 * or forwarded based on BGX()_SMU()_RX_FRM_CTL[CTL_DRP]. This count increments
631 * regardless of whether the packet is dropped. PAUSE packets are never counted in
632 * BGX()_CMR()_RX_STAT0.
633 */
634union cvmx_bgxx_cmrx_rx_stat2 {
635 u64 u64;
636 struct cvmx_bgxx_cmrx_rx_stat2_s {
637 u64 reserved_48_63 : 16;
638 u64 cnt : 48;
639 } s;
640 struct cvmx_bgxx_cmrx_rx_stat2_s cn73xx;
641 struct cvmx_bgxx_cmrx_rx_stat2_s cn78xx;
642 struct cvmx_bgxx_cmrx_rx_stat2_s cn78xxp1;
643 struct cvmx_bgxx_cmrx_rx_stat2_s cnf75xx;
644};
645
646typedef union cvmx_bgxx_cmrx_rx_stat2 cvmx_bgxx_cmrx_rx_stat2_t;
647
648/**
649 * cvmx_bgx#_cmr#_rx_stat3
650 *
651 * These registers provide a count of octets of received PAUSE and control packets.
652 *
653 */
654union cvmx_bgxx_cmrx_rx_stat3 {
655 u64 u64;
656 struct cvmx_bgxx_cmrx_rx_stat3_s {
657 u64 reserved_48_63 : 16;
658 u64 cnt : 48;
659 } s;
660 struct cvmx_bgxx_cmrx_rx_stat3_s cn73xx;
661 struct cvmx_bgxx_cmrx_rx_stat3_s cn78xx;
662 struct cvmx_bgxx_cmrx_rx_stat3_s cn78xxp1;
663 struct cvmx_bgxx_cmrx_rx_stat3_s cnf75xx;
664};
665
666typedef union cvmx_bgxx_cmrx_rx_stat3 cvmx_bgxx_cmrx_rx_stat3_t;
667
668/**
669 * cvmx_bgx#_cmr#_rx_stat4
670 *
671 * These registers provide a count of all packets received that were dropped by the DMAC filter.
672 * Packets that match the DMAC are dropped and counted here regardless of whether they were ERR
673 * packets, but does not include those reported in BGX()_CMR()_RX_STAT6. These packets
674 * are never counted in BGX()_CMR()_RX_STAT0. Eight-byte packets as the result of
675 * truncation or other means are not dropped by CNXXXX and will never appear in this count.
676 */
677union cvmx_bgxx_cmrx_rx_stat4 {
678 u64 u64;
679 struct cvmx_bgxx_cmrx_rx_stat4_s {
680 u64 reserved_48_63 : 16;
681 u64 cnt : 48;
682 } s;
683 struct cvmx_bgxx_cmrx_rx_stat4_s cn73xx;
684 struct cvmx_bgxx_cmrx_rx_stat4_s cn78xx;
685 struct cvmx_bgxx_cmrx_rx_stat4_s cn78xxp1;
686 struct cvmx_bgxx_cmrx_rx_stat4_s cnf75xx;
687};
688
689typedef union cvmx_bgxx_cmrx_rx_stat4 cvmx_bgxx_cmrx_rx_stat4_t;
690
691/**
692 * cvmx_bgx#_cmr#_rx_stat5
693 *
694 * These registers provide a count of octets of filtered DMAC packets.
695 *
696 */
697union cvmx_bgxx_cmrx_rx_stat5 {
698 u64 u64;
699 struct cvmx_bgxx_cmrx_rx_stat5_s {
700 u64 reserved_48_63 : 16;
701 u64 cnt : 48;
702 } s;
703 struct cvmx_bgxx_cmrx_rx_stat5_s cn73xx;
704 struct cvmx_bgxx_cmrx_rx_stat5_s cn78xx;
705 struct cvmx_bgxx_cmrx_rx_stat5_s cn78xxp1;
706 struct cvmx_bgxx_cmrx_rx_stat5_s cnf75xx;
707};
708
709typedef union cvmx_bgxx_cmrx_rx_stat5 cvmx_bgxx_cmrx_rx_stat5_t;
710
711/**
712 * cvmx_bgx#_cmr#_rx_stat6
713 *
714 * These registers provide a count of all packets received that were dropped due to a full
715 * receive FIFO. They do not count any packet that is truncated at the point of overflow and sent
716 * on to the PKI. These registers count all entire packets dropped by the FIFO for a given LMAC
717 * regardless of DMAC or PAUSE type.
718 */
719union cvmx_bgxx_cmrx_rx_stat6 {
720 u64 u64;
721 struct cvmx_bgxx_cmrx_rx_stat6_s {
722 u64 reserved_48_63 : 16;
723 u64 cnt : 48;
724 } s;
725 struct cvmx_bgxx_cmrx_rx_stat6_s cn73xx;
726 struct cvmx_bgxx_cmrx_rx_stat6_s cn78xx;
727 struct cvmx_bgxx_cmrx_rx_stat6_s cn78xxp1;
728 struct cvmx_bgxx_cmrx_rx_stat6_s cnf75xx;
729};
730
731typedef union cvmx_bgxx_cmrx_rx_stat6 cvmx_bgxx_cmrx_rx_stat6_t;
732
733/**
734 * cvmx_bgx#_cmr#_rx_stat7
735 *
736 * These registers provide a count of octets of received packets that were dropped due to a full
737 * receive FIFO.
738 */
739union cvmx_bgxx_cmrx_rx_stat7 {
740 u64 u64;
741 struct cvmx_bgxx_cmrx_rx_stat7_s {
742 u64 reserved_48_63 : 16;
743 u64 cnt : 48;
744 } s;
745 struct cvmx_bgxx_cmrx_rx_stat7_s cn73xx;
746 struct cvmx_bgxx_cmrx_rx_stat7_s cn78xx;
747 struct cvmx_bgxx_cmrx_rx_stat7_s cn78xxp1;
748 struct cvmx_bgxx_cmrx_rx_stat7_s cnf75xx;
749};
750
751typedef union cvmx_bgxx_cmrx_rx_stat7 cvmx_bgxx_cmrx_rx_stat7_t;
752
753/**
754 * cvmx_bgx#_cmr#_rx_stat8
755 *
756 * These registers provide a count of all packets received with some error that were not dropped
757 * either due to the DMAC filter or lack of room in the receive FIFO.
758 * This does not include packets which were counted in
759 * BGX()_CMR()_RX_STAT2, BGX()_CMR()_RX_STAT4 nor
760 * BGX()_CMR()_RX_STAT6.
761 *
762 * Which statistics are updated on control packet errors and drops are shown below:
763 *
764 * <pre>
765 * if dropped [
766 * if !errored STAT8
767 * if overflow STAT6
768 * else if dmac drop STAT4
769 * else if filter drop STAT2
770 * ] else [
771 * if errored STAT2
772 * else STAT8
773 * ]
774 * </pre>
775 */
776union cvmx_bgxx_cmrx_rx_stat8 {
777 u64 u64;
778 struct cvmx_bgxx_cmrx_rx_stat8_s {
779 u64 reserved_48_63 : 16;
780 u64 cnt : 48;
781 } s;
782 struct cvmx_bgxx_cmrx_rx_stat8_s cn73xx;
783 struct cvmx_bgxx_cmrx_rx_stat8_s cn78xx;
784 struct cvmx_bgxx_cmrx_rx_stat8_s cn78xxp1;
785 struct cvmx_bgxx_cmrx_rx_stat8_s cnf75xx;
786};
787
788typedef union cvmx_bgxx_cmrx_rx_stat8 cvmx_bgxx_cmrx_rx_stat8_t;
789
790/**
791 * cvmx_bgx#_cmr#_rx_weight
792 */
793union cvmx_bgxx_cmrx_rx_weight {
794 u64 u64;
795 struct cvmx_bgxx_cmrx_rx_weight_s {
796 u64 reserved_4_63 : 60;
797 u64 weight : 4;
798 } s;
799 struct cvmx_bgxx_cmrx_rx_weight_s cn73xx;
800 struct cvmx_bgxx_cmrx_rx_weight_s cn78xx;
801 struct cvmx_bgxx_cmrx_rx_weight_s cn78xxp1;
802 struct cvmx_bgxx_cmrx_rx_weight_s cnf75xx;
803};
804
805typedef union cvmx_bgxx_cmrx_rx_weight cvmx_bgxx_cmrx_rx_weight_t;
806
807/**
808 * cvmx_bgx#_cmr#_tx_channel
809 */
810union cvmx_bgxx_cmrx_tx_channel {
811 u64 u64;
812 struct cvmx_bgxx_cmrx_tx_channel_s {
813 u64 reserved_32_63 : 32;
814 u64 msk : 16;
815 u64 dis : 16;
816 } s;
817 struct cvmx_bgxx_cmrx_tx_channel_s cn73xx;
818 struct cvmx_bgxx_cmrx_tx_channel_s cn78xx;
819 struct cvmx_bgxx_cmrx_tx_channel_s cn78xxp1;
820 struct cvmx_bgxx_cmrx_tx_channel_s cnf75xx;
821};
822
823typedef union cvmx_bgxx_cmrx_tx_channel cvmx_bgxx_cmrx_tx_channel_t;
824
825/**
826 * cvmx_bgx#_cmr#_tx_fifo_len
827 */
828union cvmx_bgxx_cmrx_tx_fifo_len {
829 u64 u64;
830 struct cvmx_bgxx_cmrx_tx_fifo_len_s {
831 u64 reserved_14_63 : 50;
832 u64 lmac_idle : 1;
833 u64 fifo_len : 13;
834 } s;
835 struct cvmx_bgxx_cmrx_tx_fifo_len_s cn73xx;
836 struct cvmx_bgxx_cmrx_tx_fifo_len_s cn78xx;
837 struct cvmx_bgxx_cmrx_tx_fifo_len_s cn78xxp1;
838 struct cvmx_bgxx_cmrx_tx_fifo_len_s cnf75xx;
839};
840
841typedef union cvmx_bgxx_cmrx_tx_fifo_len cvmx_bgxx_cmrx_tx_fifo_len_t;
842
843/**
844 * cvmx_bgx#_cmr#_tx_hg2_status
845 */
846union cvmx_bgxx_cmrx_tx_hg2_status {
847 u64 u64;
848 struct cvmx_bgxx_cmrx_tx_hg2_status_s {
849 u64 reserved_32_63 : 32;
850 u64 xof : 16;
851 u64 lgtim2go : 16;
852 } s;
853 struct cvmx_bgxx_cmrx_tx_hg2_status_s cn73xx;
854 struct cvmx_bgxx_cmrx_tx_hg2_status_s cn78xx;
855 struct cvmx_bgxx_cmrx_tx_hg2_status_s cn78xxp1;
856 struct cvmx_bgxx_cmrx_tx_hg2_status_s cnf75xx;
857};
858
859typedef union cvmx_bgxx_cmrx_tx_hg2_status cvmx_bgxx_cmrx_tx_hg2_status_t;
860
861/**
862 * cvmx_bgx#_cmr#_tx_ovr_bp
863 */
864union cvmx_bgxx_cmrx_tx_ovr_bp {
865 u64 u64;
866 struct cvmx_bgxx_cmrx_tx_ovr_bp_s {
867 u64 reserved_16_63 : 48;
868 u64 tx_chan_bp : 16;
869 } s;
870 struct cvmx_bgxx_cmrx_tx_ovr_bp_s cn73xx;
871 struct cvmx_bgxx_cmrx_tx_ovr_bp_s cn78xx;
872 struct cvmx_bgxx_cmrx_tx_ovr_bp_s cn78xxp1;
873 struct cvmx_bgxx_cmrx_tx_ovr_bp_s cnf75xx;
874};
875
876typedef union cvmx_bgxx_cmrx_tx_ovr_bp cvmx_bgxx_cmrx_tx_ovr_bp_t;
877
878/**
879 * cvmx_bgx#_cmr#_tx_stat0
880 */
881union cvmx_bgxx_cmrx_tx_stat0 {
882 u64 u64;
883 struct cvmx_bgxx_cmrx_tx_stat0_s {
884 u64 reserved_48_63 : 16;
885 u64 xscol : 48;
886 } s;
887 struct cvmx_bgxx_cmrx_tx_stat0_s cn73xx;
888 struct cvmx_bgxx_cmrx_tx_stat0_s cn78xx;
889 struct cvmx_bgxx_cmrx_tx_stat0_s cn78xxp1;
890 struct cvmx_bgxx_cmrx_tx_stat0_s cnf75xx;
891};
892
893typedef union cvmx_bgxx_cmrx_tx_stat0 cvmx_bgxx_cmrx_tx_stat0_t;
894
895/**
896 * cvmx_bgx#_cmr#_tx_stat1
897 */
898union cvmx_bgxx_cmrx_tx_stat1 {
899 u64 u64;
900 struct cvmx_bgxx_cmrx_tx_stat1_s {
901 u64 reserved_48_63 : 16;
902 u64 xsdef : 48;
903 } s;
904 struct cvmx_bgxx_cmrx_tx_stat1_s cn73xx;
905 struct cvmx_bgxx_cmrx_tx_stat1_s cn78xx;
906 struct cvmx_bgxx_cmrx_tx_stat1_s cn78xxp1;
907 struct cvmx_bgxx_cmrx_tx_stat1_s cnf75xx;
908};
909
910typedef union cvmx_bgxx_cmrx_tx_stat1 cvmx_bgxx_cmrx_tx_stat1_t;
911
912/**
913 * cvmx_bgx#_cmr#_tx_stat10
914 */
915union cvmx_bgxx_cmrx_tx_stat10 {
916 u64 u64;
917 struct cvmx_bgxx_cmrx_tx_stat10_s {
918 u64 reserved_48_63 : 16;
919 u64 hist4 : 48;
920 } s;
921 struct cvmx_bgxx_cmrx_tx_stat10_s cn73xx;
922 struct cvmx_bgxx_cmrx_tx_stat10_s cn78xx;
923 struct cvmx_bgxx_cmrx_tx_stat10_s cn78xxp1;
924 struct cvmx_bgxx_cmrx_tx_stat10_s cnf75xx;
925};
926
927typedef union cvmx_bgxx_cmrx_tx_stat10 cvmx_bgxx_cmrx_tx_stat10_t;
928
929/**
930 * cvmx_bgx#_cmr#_tx_stat11
931 */
932union cvmx_bgxx_cmrx_tx_stat11 {
933 u64 u64;
934 struct cvmx_bgxx_cmrx_tx_stat11_s {
935 u64 reserved_48_63 : 16;
936 u64 hist5 : 48;
937 } s;
938 struct cvmx_bgxx_cmrx_tx_stat11_s cn73xx;
939 struct cvmx_bgxx_cmrx_tx_stat11_s cn78xx;
940 struct cvmx_bgxx_cmrx_tx_stat11_s cn78xxp1;
941 struct cvmx_bgxx_cmrx_tx_stat11_s cnf75xx;
942};
943
944typedef union cvmx_bgxx_cmrx_tx_stat11 cvmx_bgxx_cmrx_tx_stat11_t;
945
946/**
947 * cvmx_bgx#_cmr#_tx_stat12
948 */
949union cvmx_bgxx_cmrx_tx_stat12 {
950 u64 u64;
951 struct cvmx_bgxx_cmrx_tx_stat12_s {
952 u64 reserved_48_63 : 16;
953 u64 hist6 : 48;
954 } s;
955 struct cvmx_bgxx_cmrx_tx_stat12_s cn73xx;
956 struct cvmx_bgxx_cmrx_tx_stat12_s cn78xx;
957 struct cvmx_bgxx_cmrx_tx_stat12_s cn78xxp1;
958 struct cvmx_bgxx_cmrx_tx_stat12_s cnf75xx;
959};
960
961typedef union cvmx_bgxx_cmrx_tx_stat12 cvmx_bgxx_cmrx_tx_stat12_t;
962
963/**
964 * cvmx_bgx#_cmr#_tx_stat13
965 */
966union cvmx_bgxx_cmrx_tx_stat13 {
967 u64 u64;
968 struct cvmx_bgxx_cmrx_tx_stat13_s {
969 u64 reserved_48_63 : 16;
970 u64 hist7 : 48;
971 } s;
972 struct cvmx_bgxx_cmrx_tx_stat13_s cn73xx;
973 struct cvmx_bgxx_cmrx_tx_stat13_s cn78xx;
974 struct cvmx_bgxx_cmrx_tx_stat13_s cn78xxp1;
975 struct cvmx_bgxx_cmrx_tx_stat13_s cnf75xx;
976};
977
978typedef union cvmx_bgxx_cmrx_tx_stat13 cvmx_bgxx_cmrx_tx_stat13_t;
979
980/**
981 * cvmx_bgx#_cmr#_tx_stat14
982 */
983union cvmx_bgxx_cmrx_tx_stat14 {
984 u64 u64;
985 struct cvmx_bgxx_cmrx_tx_stat14_s {
986 u64 reserved_48_63 : 16;
987 u64 bcst : 48;
988 } s;
989 struct cvmx_bgxx_cmrx_tx_stat14_s cn73xx;
990 struct cvmx_bgxx_cmrx_tx_stat14_s cn78xx;
991 struct cvmx_bgxx_cmrx_tx_stat14_s cn78xxp1;
992 struct cvmx_bgxx_cmrx_tx_stat14_s cnf75xx;
993};
994
995typedef union cvmx_bgxx_cmrx_tx_stat14 cvmx_bgxx_cmrx_tx_stat14_t;
996
997/**
998 * cvmx_bgx#_cmr#_tx_stat15
999 */
1000union cvmx_bgxx_cmrx_tx_stat15 {
1001 u64 u64;
1002 struct cvmx_bgxx_cmrx_tx_stat15_s {
1003 u64 reserved_48_63 : 16;
1004 u64 mcst : 48;
1005 } s;
1006 struct cvmx_bgxx_cmrx_tx_stat15_s cn73xx;
1007 struct cvmx_bgxx_cmrx_tx_stat15_s cn78xx;
1008 struct cvmx_bgxx_cmrx_tx_stat15_s cn78xxp1;
1009 struct cvmx_bgxx_cmrx_tx_stat15_s cnf75xx;
1010};
1011
1012typedef union cvmx_bgxx_cmrx_tx_stat15 cvmx_bgxx_cmrx_tx_stat15_t;
1013
1014/**
1015 * cvmx_bgx#_cmr#_tx_stat16
1016 */
1017union cvmx_bgxx_cmrx_tx_stat16 {
1018 u64 u64;
1019 struct cvmx_bgxx_cmrx_tx_stat16_s {
1020 u64 reserved_48_63 : 16;
1021 u64 undflw : 48;
1022 } s;
1023 struct cvmx_bgxx_cmrx_tx_stat16_s cn73xx;
1024 struct cvmx_bgxx_cmrx_tx_stat16_s cn78xx;
1025 struct cvmx_bgxx_cmrx_tx_stat16_s cn78xxp1;
1026 struct cvmx_bgxx_cmrx_tx_stat16_s cnf75xx;
1027};
1028
1029typedef union cvmx_bgxx_cmrx_tx_stat16 cvmx_bgxx_cmrx_tx_stat16_t;
1030
1031/**
1032 * cvmx_bgx#_cmr#_tx_stat17
1033 */
1034union cvmx_bgxx_cmrx_tx_stat17 {
1035 u64 u64;
1036 struct cvmx_bgxx_cmrx_tx_stat17_s {
1037 u64 reserved_48_63 : 16;
1038 u64 ctl : 48;
1039 } s;
1040 struct cvmx_bgxx_cmrx_tx_stat17_s cn73xx;
1041 struct cvmx_bgxx_cmrx_tx_stat17_s cn78xx;
1042 struct cvmx_bgxx_cmrx_tx_stat17_s cn78xxp1;
1043 struct cvmx_bgxx_cmrx_tx_stat17_s cnf75xx;
1044};
1045
1046typedef union cvmx_bgxx_cmrx_tx_stat17 cvmx_bgxx_cmrx_tx_stat17_t;
1047
1048/**
1049 * cvmx_bgx#_cmr#_tx_stat2
1050 */
1051union cvmx_bgxx_cmrx_tx_stat2 {
1052 u64 u64;
1053 struct cvmx_bgxx_cmrx_tx_stat2_s {
1054 u64 reserved_48_63 : 16;
1055 u64 mcol : 48;
1056 } s;
1057 struct cvmx_bgxx_cmrx_tx_stat2_s cn73xx;
1058 struct cvmx_bgxx_cmrx_tx_stat2_s cn78xx;
1059 struct cvmx_bgxx_cmrx_tx_stat2_s cn78xxp1;
1060 struct cvmx_bgxx_cmrx_tx_stat2_s cnf75xx;
1061};
1062
1063typedef union cvmx_bgxx_cmrx_tx_stat2 cvmx_bgxx_cmrx_tx_stat2_t;
1064
1065/**
1066 * cvmx_bgx#_cmr#_tx_stat3
1067 */
1068union cvmx_bgxx_cmrx_tx_stat3 {
1069 u64 u64;
1070 struct cvmx_bgxx_cmrx_tx_stat3_s {
1071 u64 reserved_48_63 : 16;
1072 u64 scol : 48;
1073 } s;
1074 struct cvmx_bgxx_cmrx_tx_stat3_s cn73xx;
1075 struct cvmx_bgxx_cmrx_tx_stat3_s cn78xx;
1076 struct cvmx_bgxx_cmrx_tx_stat3_s cn78xxp1;
1077 struct cvmx_bgxx_cmrx_tx_stat3_s cnf75xx;
1078};
1079
1080typedef union cvmx_bgxx_cmrx_tx_stat3 cvmx_bgxx_cmrx_tx_stat3_t;
1081
1082/**
1083 * cvmx_bgx#_cmr#_tx_stat4
1084 */
1085union cvmx_bgxx_cmrx_tx_stat4 {
1086 u64 u64;
1087 struct cvmx_bgxx_cmrx_tx_stat4_s {
1088 u64 reserved_48_63 : 16;
1089 u64 octs : 48;
1090 } s;
1091 struct cvmx_bgxx_cmrx_tx_stat4_s cn73xx;
1092 struct cvmx_bgxx_cmrx_tx_stat4_s cn78xx;
1093 struct cvmx_bgxx_cmrx_tx_stat4_s cn78xxp1;
1094 struct cvmx_bgxx_cmrx_tx_stat4_s cnf75xx;
1095};
1096
1097typedef union cvmx_bgxx_cmrx_tx_stat4 cvmx_bgxx_cmrx_tx_stat4_t;
1098
1099/**
1100 * cvmx_bgx#_cmr#_tx_stat5
1101 */
1102union cvmx_bgxx_cmrx_tx_stat5 {
1103 u64 u64;
1104 struct cvmx_bgxx_cmrx_tx_stat5_s {
1105 u64 reserved_48_63 : 16;
1106 u64 pkts : 48;
1107 } s;
1108 struct cvmx_bgxx_cmrx_tx_stat5_s cn73xx;
1109 struct cvmx_bgxx_cmrx_tx_stat5_s cn78xx;
1110 struct cvmx_bgxx_cmrx_tx_stat5_s cn78xxp1;
1111 struct cvmx_bgxx_cmrx_tx_stat5_s cnf75xx;
1112};
1113
1114typedef union cvmx_bgxx_cmrx_tx_stat5 cvmx_bgxx_cmrx_tx_stat5_t;
1115
1116/**
1117 * cvmx_bgx#_cmr#_tx_stat6
1118 */
1119union cvmx_bgxx_cmrx_tx_stat6 {
1120 u64 u64;
1121 struct cvmx_bgxx_cmrx_tx_stat6_s {
1122 u64 reserved_48_63 : 16;
1123 u64 hist0 : 48;
1124 } s;
1125 struct cvmx_bgxx_cmrx_tx_stat6_s cn73xx;
1126 struct cvmx_bgxx_cmrx_tx_stat6_s cn78xx;
1127 struct cvmx_bgxx_cmrx_tx_stat6_s cn78xxp1;
1128 struct cvmx_bgxx_cmrx_tx_stat6_s cnf75xx;
1129};
1130
1131typedef union cvmx_bgxx_cmrx_tx_stat6 cvmx_bgxx_cmrx_tx_stat6_t;
1132
1133/**
1134 * cvmx_bgx#_cmr#_tx_stat7
1135 */
1136union cvmx_bgxx_cmrx_tx_stat7 {
1137 u64 u64;
1138 struct cvmx_bgxx_cmrx_tx_stat7_s {
1139 u64 reserved_48_63 : 16;
1140 u64 hist1 : 48;
1141 } s;
1142 struct cvmx_bgxx_cmrx_tx_stat7_s cn73xx;
1143 struct cvmx_bgxx_cmrx_tx_stat7_s cn78xx;
1144 struct cvmx_bgxx_cmrx_tx_stat7_s cn78xxp1;
1145 struct cvmx_bgxx_cmrx_tx_stat7_s cnf75xx;
1146};
1147
1148typedef union cvmx_bgxx_cmrx_tx_stat7 cvmx_bgxx_cmrx_tx_stat7_t;
1149
1150/**
1151 * cvmx_bgx#_cmr#_tx_stat8
1152 */
1153union cvmx_bgxx_cmrx_tx_stat8 {
1154 u64 u64;
1155 struct cvmx_bgxx_cmrx_tx_stat8_s {
1156 u64 reserved_48_63 : 16;
1157 u64 hist2 : 48;
1158 } s;
1159 struct cvmx_bgxx_cmrx_tx_stat8_s cn73xx;
1160 struct cvmx_bgxx_cmrx_tx_stat8_s cn78xx;
1161 struct cvmx_bgxx_cmrx_tx_stat8_s cn78xxp1;
1162 struct cvmx_bgxx_cmrx_tx_stat8_s cnf75xx;
1163};
1164
1165typedef union cvmx_bgxx_cmrx_tx_stat8 cvmx_bgxx_cmrx_tx_stat8_t;
1166
1167/**
1168 * cvmx_bgx#_cmr#_tx_stat9
1169 */
1170union cvmx_bgxx_cmrx_tx_stat9 {
1171 u64 u64;
1172 struct cvmx_bgxx_cmrx_tx_stat9_s {
1173 u64 reserved_48_63 : 16;
1174 u64 hist3 : 48;
1175 } s;
1176 struct cvmx_bgxx_cmrx_tx_stat9_s cn73xx;
1177 struct cvmx_bgxx_cmrx_tx_stat9_s cn78xx;
1178 struct cvmx_bgxx_cmrx_tx_stat9_s cn78xxp1;
1179 struct cvmx_bgxx_cmrx_tx_stat9_s cnf75xx;
1180};
1181
1182typedef union cvmx_bgxx_cmrx_tx_stat9 cvmx_bgxx_cmrx_tx_stat9_t;
1183
1184/**
1185 * cvmx_bgx#_cmr_bad
1186 */
1187union cvmx_bgxx_cmr_bad {
1188 u64 u64;
1189 struct cvmx_bgxx_cmr_bad_s {
1190 u64 reserved_1_63 : 63;
1191 u64 rxb_nxl : 1;
1192 } s;
1193 struct cvmx_bgxx_cmr_bad_s cn73xx;
1194 struct cvmx_bgxx_cmr_bad_s cn78xx;
1195 struct cvmx_bgxx_cmr_bad_s cn78xxp1;
1196 struct cvmx_bgxx_cmr_bad_s cnf75xx;
1197};
1198
1199typedef union cvmx_bgxx_cmr_bad cvmx_bgxx_cmr_bad_t;
1200
1201/**
1202 * cvmx_bgx#_cmr_bist_status
1203 */
1204union cvmx_bgxx_cmr_bist_status {
1205 u64 u64;
1206 struct cvmx_bgxx_cmr_bist_status_s {
1207 u64 reserved_25_63 : 39;
1208 u64 status : 25;
1209 } s;
1210 struct cvmx_bgxx_cmr_bist_status_s cn73xx;
1211 struct cvmx_bgxx_cmr_bist_status_s cn78xx;
1212 struct cvmx_bgxx_cmr_bist_status_s cn78xxp1;
1213 struct cvmx_bgxx_cmr_bist_status_s cnf75xx;
1214};
1215
1216typedef union cvmx_bgxx_cmr_bist_status cvmx_bgxx_cmr_bist_status_t;
1217
1218/**
1219 * cvmx_bgx#_cmr_chan_msk_and
1220 */
1221union cvmx_bgxx_cmr_chan_msk_and {
1222 u64 u64;
1223 struct cvmx_bgxx_cmr_chan_msk_and_s {
1224 u64 msk_and : 64;
1225 } s;
1226 struct cvmx_bgxx_cmr_chan_msk_and_s cn73xx;
1227 struct cvmx_bgxx_cmr_chan_msk_and_s cn78xx;
1228 struct cvmx_bgxx_cmr_chan_msk_and_s cn78xxp1;
1229 struct cvmx_bgxx_cmr_chan_msk_and_s cnf75xx;
1230};
1231
1232typedef union cvmx_bgxx_cmr_chan_msk_and cvmx_bgxx_cmr_chan_msk_and_t;
1233
1234/**
1235 * cvmx_bgx#_cmr_chan_msk_or
1236 */
1237union cvmx_bgxx_cmr_chan_msk_or {
1238 u64 u64;
1239 struct cvmx_bgxx_cmr_chan_msk_or_s {
1240 u64 msk_or : 64;
1241 } s;
1242 struct cvmx_bgxx_cmr_chan_msk_or_s cn73xx;
1243 struct cvmx_bgxx_cmr_chan_msk_or_s cn78xx;
1244 struct cvmx_bgxx_cmr_chan_msk_or_s cn78xxp1;
1245 struct cvmx_bgxx_cmr_chan_msk_or_s cnf75xx;
1246};
1247
1248typedef union cvmx_bgxx_cmr_chan_msk_or cvmx_bgxx_cmr_chan_msk_or_t;
1249
1250/**
1251 * cvmx_bgx#_cmr_eco
1252 */
1253union cvmx_bgxx_cmr_eco {
1254 u64 u64;
1255 struct cvmx_bgxx_cmr_eco_s {
1256 u64 eco_ro : 32;
1257 u64 eco_rw : 32;
1258 } s;
1259 struct cvmx_bgxx_cmr_eco_s cn73xx;
1260 struct cvmx_bgxx_cmr_eco_s cn78xx;
1261 struct cvmx_bgxx_cmr_eco_s cnf75xx;
1262};
1263
1264typedef union cvmx_bgxx_cmr_eco cvmx_bgxx_cmr_eco_t;
1265
1266/**
1267 * cvmx_bgx#_cmr_global_config
1268 *
1269 * These registers configure the global CMR, PCS, and MAC.
1270 *
1271 */
1272union cvmx_bgxx_cmr_global_config {
1273 u64 u64;
1274 struct cvmx_bgxx_cmr_global_config_s {
1275 u64 reserved_5_63 : 59;
1276 u64 cmr_mix1_reset : 1;
1277 u64 cmr_mix0_reset : 1;
1278 u64 cmr_x2p_reset : 1;
1279 u64 bgx_clk_enable : 1;
1280 u64 pmux_sds_sel : 1;
1281 } s;
1282 struct cvmx_bgxx_cmr_global_config_s cn73xx;
1283 struct cvmx_bgxx_cmr_global_config_s cn78xx;
1284 struct cvmx_bgxx_cmr_global_config_s cn78xxp1;
1285 struct cvmx_bgxx_cmr_global_config_s cnf75xx;
1286};
1287
1288typedef union cvmx_bgxx_cmr_global_config cvmx_bgxx_cmr_global_config_t;
1289
1290/**
1291 * cvmx_bgx#_cmr_mem_ctrl
1292 */
1293union cvmx_bgxx_cmr_mem_ctrl {
1294 u64 u64;
1295 struct cvmx_bgxx_cmr_mem_ctrl_s {
1296 u64 reserved_24_63 : 40;
1297 u64 txb_skid_synd : 2;
1298 u64 txb_skid_cor_dis : 1;
1299 u64 txb_fif_bk1_syn : 2;
1300 u64 txb_fif_bk1_cdis : 1;
1301 u64 txb_fif_bk0_syn : 2;
1302 u64 txb_fif_bk0_cdis : 1;
1303 u64 rxb_skid_synd : 2;
1304 u64 rxb_skid_cor_dis : 1;
1305 u64 rxb_fif_bk1_syn1 : 2;
1306 u64 rxb_fif_bk1_cdis1 : 1;
1307 u64 rxb_fif_bk1_syn0 : 2;
1308 u64 rxb_fif_bk1_cdis0 : 1;
1309 u64 rxb_fif_bk0_syn1 : 2;
1310 u64 rxb_fif_bk0_cdis1 : 1;
1311 u64 rxb_fif_bk0_syn0 : 2;
1312 u64 rxb_fif_bk0_cdis0 : 1;
1313 } s;
1314 struct cvmx_bgxx_cmr_mem_ctrl_s cn73xx;
1315 struct cvmx_bgxx_cmr_mem_ctrl_s cn78xx;
1316 struct cvmx_bgxx_cmr_mem_ctrl_s cn78xxp1;
1317 struct cvmx_bgxx_cmr_mem_ctrl_s cnf75xx;
1318};
1319
1320typedef union cvmx_bgxx_cmr_mem_ctrl cvmx_bgxx_cmr_mem_ctrl_t;
1321
1322/**
1323 * cvmx_bgx#_cmr_mem_int
1324 */
1325union cvmx_bgxx_cmr_mem_int {
1326 u64 u64;
1327 struct cvmx_bgxx_cmr_mem_int_s {
1328 u64 reserved_18_63 : 46;
1329 u64 smu_in_overfl : 1;
1330 u64 gmp_in_overfl : 1;
1331 u64 txb_skid_sbe : 1;
1332 u64 txb_skid_dbe : 1;
1333 u64 txb_fif_bk1_sbe : 1;
1334 u64 txb_fif_bk1_dbe : 1;
1335 u64 txb_fif_bk0_sbe : 1;
1336 u64 txb_fif_bk0_dbe : 1;
1337 u64 rxb_skid_sbe : 1;
1338 u64 rxb_skid_dbe : 1;
1339 u64 rxb_fif_bk1_sbe1 : 1;
1340 u64 rxb_fif_bk1_dbe1 : 1;
1341 u64 rxb_fif_bk1_sbe0 : 1;
1342 u64 rxb_fif_bk1_dbe0 : 1;
1343 u64 rxb_fif_bk0_sbe1 : 1;
1344 u64 rxb_fif_bk0_dbe1 : 1;
1345 u64 rxb_fif_bk0_sbe0 : 1;
1346 u64 rxb_fif_bk0_dbe0 : 1;
1347 } s;
1348 struct cvmx_bgxx_cmr_mem_int_s cn73xx;
1349 struct cvmx_bgxx_cmr_mem_int_s cn78xx;
1350 struct cvmx_bgxx_cmr_mem_int_s cn78xxp1;
1351 struct cvmx_bgxx_cmr_mem_int_s cnf75xx;
1352};
1353
1354typedef union cvmx_bgxx_cmr_mem_int cvmx_bgxx_cmr_mem_int_t;
1355
1356/**
1357 * cvmx_bgx#_cmr_nxc_adr
1358 */
1359union cvmx_bgxx_cmr_nxc_adr {
1360 u64 u64;
1361 struct cvmx_bgxx_cmr_nxc_adr_s {
1362 u64 reserved_16_63 : 48;
1363 u64 lmac_id : 4;
1364 u64 channel : 12;
1365 } s;
1366 struct cvmx_bgxx_cmr_nxc_adr_s cn73xx;
1367 struct cvmx_bgxx_cmr_nxc_adr_s cn78xx;
1368 struct cvmx_bgxx_cmr_nxc_adr_s cn78xxp1;
1369 struct cvmx_bgxx_cmr_nxc_adr_s cnf75xx;
1370};
1371
1372typedef union cvmx_bgxx_cmr_nxc_adr cvmx_bgxx_cmr_nxc_adr_t;
1373
1374/**
1375 * cvmx_bgx#_cmr_rx_adr#_cam
1376 *
1377 * These registers provide access to the 32 DMAC CAM entries in BGX.
1378 *
1379 */
1380union cvmx_bgxx_cmr_rx_adrx_cam {
1381 u64 u64;
1382 struct cvmx_bgxx_cmr_rx_adrx_cam_s {
1383 u64 reserved_54_63 : 10;
1384 u64 id : 2;
1385 u64 reserved_49_51 : 3;
1386 u64 en : 1;
1387 u64 adr : 48;
1388 } s;
1389 struct cvmx_bgxx_cmr_rx_adrx_cam_s cn73xx;
1390 struct cvmx_bgxx_cmr_rx_adrx_cam_s cn78xx;
1391 struct cvmx_bgxx_cmr_rx_adrx_cam_s cn78xxp1;
1392 struct cvmx_bgxx_cmr_rx_adrx_cam_s cnf75xx;
1393};
1394
1395typedef union cvmx_bgxx_cmr_rx_adrx_cam cvmx_bgxx_cmr_rx_adrx_cam_t;
1396
1397/**
1398 * cvmx_bgx#_cmr_rx_lmacs
1399 */
1400union cvmx_bgxx_cmr_rx_lmacs {
1401 u64 u64;
1402 struct cvmx_bgxx_cmr_rx_lmacs_s {
1403 u64 reserved_3_63 : 61;
1404 u64 lmacs : 3;
1405 } s;
1406 struct cvmx_bgxx_cmr_rx_lmacs_s cn73xx;
1407 struct cvmx_bgxx_cmr_rx_lmacs_s cn78xx;
1408 struct cvmx_bgxx_cmr_rx_lmacs_s cn78xxp1;
1409 struct cvmx_bgxx_cmr_rx_lmacs_s cnf75xx;
1410};
1411
1412typedef union cvmx_bgxx_cmr_rx_lmacs cvmx_bgxx_cmr_rx_lmacs_t;
1413
1414/**
1415 * cvmx_bgx#_cmr_rx_ovr_bp
1416 *
1417 * BGX()_CMR_RX_OVR_BP[EN<0>] must be set to one and BGX()_CMR_RX_OVR_BP[BP<0>] must be
1418 * cleared to zero (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with
1419 * the HiGig2 Protocol when BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is
1420 * indicated by BGX()_SMU()_TX_CTL[HG_EN]=1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16).
1421 * Hardware can only auto-generate backpressure through HiGig2 messages (optionally, when
1422 * BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2 protocol.
1423 */
1424union cvmx_bgxx_cmr_rx_ovr_bp {
1425 u64 u64;
1426 struct cvmx_bgxx_cmr_rx_ovr_bp_s {
1427 u64 reserved_12_63 : 52;
1428 u64 en : 4;
1429 u64 bp : 4;
1430 u64 ign_fifo_bp : 4;
1431 } s;
1432 struct cvmx_bgxx_cmr_rx_ovr_bp_s cn73xx;
1433 struct cvmx_bgxx_cmr_rx_ovr_bp_s cn78xx;
1434 struct cvmx_bgxx_cmr_rx_ovr_bp_s cn78xxp1;
1435 struct cvmx_bgxx_cmr_rx_ovr_bp_s cnf75xx;
1436};
1437
1438typedef union cvmx_bgxx_cmr_rx_ovr_bp cvmx_bgxx_cmr_rx_ovr_bp_t;
1439
1440/**
1441 * cvmx_bgx#_cmr_tx_lmacs
1442 *
1443 * This register sets the number of LMACs allowed on the TX interface. The value is important for
1444 * defining the partitioning of the transmit FIFO.
1445 */
1446union cvmx_bgxx_cmr_tx_lmacs {
1447 u64 u64;
1448 struct cvmx_bgxx_cmr_tx_lmacs_s {
1449 u64 reserved_3_63 : 61;
1450 u64 lmacs : 3;
1451 } s;
1452 struct cvmx_bgxx_cmr_tx_lmacs_s cn73xx;
1453 struct cvmx_bgxx_cmr_tx_lmacs_s cn78xx;
1454 struct cvmx_bgxx_cmr_tx_lmacs_s cn78xxp1;
1455 struct cvmx_bgxx_cmr_tx_lmacs_s cnf75xx;
1456};
1457
1458typedef union cvmx_bgxx_cmr_tx_lmacs cvmx_bgxx_cmr_tx_lmacs_t;
1459
1460/**
1461 * cvmx_bgx#_gmp_gmi_prt#_cfg
1462 *
1463 * This register controls the configuration of the LMAC.
1464 *
1465 */
1466union cvmx_bgxx_gmp_gmi_prtx_cfg {
1467 u64 u64;
1468 struct cvmx_bgxx_gmp_gmi_prtx_cfg_s {
1469 u64 reserved_14_63 : 50;
1470 u64 tx_idle : 1;
1471 u64 rx_idle : 1;
1472 u64 reserved_9_11 : 3;
1473 u64 speed_msb : 1;
1474 u64 reserved_4_7 : 4;
1475 u64 slottime : 1;
1476 u64 duplex : 1;
1477 u64 speed : 1;
1478 u64 reserved_0_0 : 1;
1479 } s;
1480 struct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn73xx;
1481 struct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn78xx;
1482 struct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn78xxp1;
1483 struct cvmx_bgxx_gmp_gmi_prtx_cfg_s cnf75xx;
1484};
1485
1486typedef union cvmx_bgxx_gmp_gmi_prtx_cfg cvmx_bgxx_gmp_gmi_prtx_cfg_t;
1487
1488/**
1489 * cvmx_bgx#_gmp_gmi_rx#_decision
1490 *
1491 * This register specifies the byte count used to determine when to accept or to filter a packet.
1492 * As each byte in a packet is received by GMI, the L2 byte count is compared against
1493 * [CNT]. In normal operation, the L2 header begins after the
1494 * PREAMBLE + SFD (BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] = 1) and any optional UDD skip
1495 * data (BGX()_GMP_GMI_RX()_UDD_SKP[LEN]).
1496 */
1497union cvmx_bgxx_gmp_gmi_rxx_decision {
1498 u64 u64;
1499 struct cvmx_bgxx_gmp_gmi_rxx_decision_s {
1500 u64 reserved_5_63 : 59;
1501 u64 cnt : 5;
1502 } s;
1503 struct cvmx_bgxx_gmp_gmi_rxx_decision_s cn73xx;
1504 struct cvmx_bgxx_gmp_gmi_rxx_decision_s cn78xx;
1505 struct cvmx_bgxx_gmp_gmi_rxx_decision_s cn78xxp1;
1506 struct cvmx_bgxx_gmp_gmi_rxx_decision_s cnf75xx;
1507};
1508
1509typedef union cvmx_bgxx_gmp_gmi_rxx_decision cvmx_bgxx_gmp_gmi_rxx_decision_t;
1510
1511/**
1512 * cvmx_bgx#_gmp_gmi_rx#_frm_chk
1513 */
1514union cvmx_bgxx_gmp_gmi_rxx_frm_chk {
1515 u64 u64;
1516 struct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s {
1517 u64 reserved_9_63 : 55;
1518 u64 skperr : 1;
1519 u64 rcverr : 1;
1520 u64 reserved_5_6 : 2;
1521 u64 fcserr : 1;
1522 u64 jabber : 1;
1523 u64 reserved_2_2 : 1;
1524 u64 carext : 1;
1525 u64 minerr : 1;
1526 } s;
1527 struct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn73xx;
1528 struct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn78xx;
1529 struct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn78xxp1;
1530 struct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cnf75xx;
1531};
1532
1533typedef union cvmx_bgxx_gmp_gmi_rxx_frm_chk cvmx_bgxx_gmp_gmi_rxx_frm_chk_t;
1534
1535/**
1536 * cvmx_bgx#_gmp_gmi_rx#_frm_ctl
1537 *
1538 * This register controls the handling of the frames.
1539 * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The
1540 * most
1541 * common modes of operation:
1542 * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything.
1543 * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames.
1544 * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored.
1545 *
1546 * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since
1547 * PAUSE
1548 * packets only apply to full duplex operation, any PAUSE packet would constitute an exception
1549 * which should be handled by the processing cores. PAUSE packets should not be forwarded.
1550 */
1551union cvmx_bgxx_gmp_gmi_rxx_frm_ctl {
1552 u64 u64;
1553 struct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s {
1554 u64 reserved_13_63 : 51;
1555 u64 ptp_mode : 1;
1556 u64 reserved_11_11 : 1;
1557 u64 null_dis : 1;
1558 u64 pre_align : 1;
1559 u64 reserved_7_8 : 2;
1560 u64 pre_free : 1;
1561 u64 ctl_smac : 1;
1562 u64 ctl_mcst : 1;
1563 u64 ctl_bck : 1;
1564 u64 ctl_drp : 1;
1565 u64 pre_strp : 1;
1566 u64 pre_chk : 1;
1567 } s;
1568 struct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn73xx;
1569 struct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn78xx;
1570 struct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn78xxp1;
1571 struct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cnf75xx;
1572};
1573
1574typedef union cvmx_bgxx_gmp_gmi_rxx_frm_ctl cvmx_bgxx_gmp_gmi_rxx_frm_ctl_t;
1575
1576/**
1577 * cvmx_bgx#_gmp_gmi_rx#_ifg
1578 *
1579 * This register specifies the minimum number of interframe-gap (IFG) cycles between packets.
1580 *
1581 */
1582union cvmx_bgxx_gmp_gmi_rxx_ifg {
1583 u64 u64;
1584 struct cvmx_bgxx_gmp_gmi_rxx_ifg_s {
1585 u64 reserved_4_63 : 60;
1586 u64 ifg : 4;
1587 } s;
1588 struct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn73xx;
1589 struct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn78xx;
1590 struct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn78xxp1;
1591 struct cvmx_bgxx_gmp_gmi_rxx_ifg_s cnf75xx;
1592};
1593
1594typedef union cvmx_bgxx_gmp_gmi_rxx_ifg cvmx_bgxx_gmp_gmi_rxx_ifg_t;
1595
1596/**
1597 * cvmx_bgx#_gmp_gmi_rx#_int
1598 *
1599 * '"These registers allow interrupts to be sent to the control processor.
1600 * * Exception conditions <10:0> can also set the rcv/opcode in the received packet's work-queue
1601 * entry. BGX()_GMP_GMI_RX()_FRM_CHK provides a bit mask for configuring which conditions
1602 * set the error.
1603 * In half duplex operation, the expectation is that collisions will appear as either MINERR or
1604 * CAREXT errors.'
1605 */
1606union cvmx_bgxx_gmp_gmi_rxx_int {
1607 u64 u64;
1608 struct cvmx_bgxx_gmp_gmi_rxx_int_s {
1609 u64 reserved_12_63 : 52;
1610 u64 ifgerr : 1;
1611 u64 coldet : 1;
1612 u64 falerr : 1;
1613 u64 rsverr : 1;
1614 u64 pcterr : 1;
1615 u64 ovrerr : 1;
1616 u64 skperr : 1;
1617 u64 rcverr : 1;
1618 u64 fcserr : 1;
1619 u64 jabber : 1;
1620 u64 carext : 1;
1621 u64 minerr : 1;
1622 } s;
1623 struct cvmx_bgxx_gmp_gmi_rxx_int_s cn73xx;
1624 struct cvmx_bgxx_gmp_gmi_rxx_int_s cn78xx;
1625 struct cvmx_bgxx_gmp_gmi_rxx_int_s cn78xxp1;
1626 struct cvmx_bgxx_gmp_gmi_rxx_int_s cnf75xx;
1627};
1628
1629typedef union cvmx_bgxx_gmp_gmi_rxx_int cvmx_bgxx_gmp_gmi_rxx_int_t;
1630
1631/**
1632 * cvmx_bgx#_gmp_gmi_rx#_jabber
1633 *
1634 * This register specifies the maximum size for packets, beyond which the GMI truncates.
1635 *
1636 */
1637union cvmx_bgxx_gmp_gmi_rxx_jabber {
1638 u64 u64;
1639 struct cvmx_bgxx_gmp_gmi_rxx_jabber_s {
1640 u64 reserved_16_63 : 48;
1641 u64 cnt : 16;
1642 } s;
1643 struct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn73xx;
1644 struct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn78xx;
1645 struct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn78xxp1;
1646 struct cvmx_bgxx_gmp_gmi_rxx_jabber_s cnf75xx;
1647};
1648
1649typedef union cvmx_bgxx_gmp_gmi_rxx_jabber cvmx_bgxx_gmp_gmi_rxx_jabber_t;
1650
1651/**
1652 * cvmx_bgx#_gmp_gmi_rx#_udd_skp
1653 *
1654 * This register specifies the amount of user-defined data (UDD) added before the start of the
1655 * L2C data.
1656 */
1657union cvmx_bgxx_gmp_gmi_rxx_udd_skp {
1658 u64 u64;
1659 struct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s {
1660 u64 reserved_9_63 : 55;
1661 u64 fcssel : 1;
1662 u64 reserved_7_7 : 1;
1663 u64 len : 7;
1664 } s;
1665 struct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn73xx;
1666 struct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn78xx;
1667 struct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn78xxp1;
1668 struct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cnf75xx;
1669};
1670
1671typedef union cvmx_bgxx_gmp_gmi_rxx_udd_skp cvmx_bgxx_gmp_gmi_rxx_udd_skp_t;
1672
1673/**
1674 * cvmx_bgx#_gmp_gmi_smac#
1675 */
1676union cvmx_bgxx_gmp_gmi_smacx {
1677 u64 u64;
1678 struct cvmx_bgxx_gmp_gmi_smacx_s {
1679 u64 reserved_48_63 : 16;
1680 u64 smac : 48;
1681 } s;
1682 struct cvmx_bgxx_gmp_gmi_smacx_s cn73xx;
1683 struct cvmx_bgxx_gmp_gmi_smacx_s cn78xx;
1684 struct cvmx_bgxx_gmp_gmi_smacx_s cn78xxp1;
1685 struct cvmx_bgxx_gmp_gmi_smacx_s cnf75xx;
1686};
1687
1688typedef union cvmx_bgxx_gmp_gmi_smacx cvmx_bgxx_gmp_gmi_smacx_t;
1689
1690/**
1691 * cvmx_bgx#_gmp_gmi_tx#_append
1692 */
1693union cvmx_bgxx_gmp_gmi_txx_append {
1694 u64 u64;
1695 struct cvmx_bgxx_gmp_gmi_txx_append_s {
1696 u64 reserved_4_63 : 60;
1697 u64 force_fcs : 1;
1698 u64 fcs : 1;
1699 u64 pad : 1;
1700 u64 preamble : 1;
1701 } s;
1702 struct cvmx_bgxx_gmp_gmi_txx_append_s cn73xx;
1703 struct cvmx_bgxx_gmp_gmi_txx_append_s cn78xx;
1704 struct cvmx_bgxx_gmp_gmi_txx_append_s cn78xxp1;
1705 struct cvmx_bgxx_gmp_gmi_txx_append_s cnf75xx;
1706};
1707
1708typedef union cvmx_bgxx_gmp_gmi_txx_append cvmx_bgxx_gmp_gmi_txx_append_t;
1709
1710/**
1711 * cvmx_bgx#_gmp_gmi_tx#_burst
1712 */
1713union cvmx_bgxx_gmp_gmi_txx_burst {
1714 u64 u64;
1715 struct cvmx_bgxx_gmp_gmi_txx_burst_s {
1716 u64 reserved_16_63 : 48;
1717 u64 burst : 16;
1718 } s;
1719 struct cvmx_bgxx_gmp_gmi_txx_burst_s cn73xx;
1720 struct cvmx_bgxx_gmp_gmi_txx_burst_s cn78xx;
1721 struct cvmx_bgxx_gmp_gmi_txx_burst_s cn78xxp1;
1722 struct cvmx_bgxx_gmp_gmi_txx_burst_s cnf75xx;
1723};
1724
1725typedef union cvmx_bgxx_gmp_gmi_txx_burst cvmx_bgxx_gmp_gmi_txx_burst_t;
1726
1727/**
1728 * cvmx_bgx#_gmp_gmi_tx#_ctl
1729 */
1730union cvmx_bgxx_gmp_gmi_txx_ctl {
1731 u64 u64;
1732 struct cvmx_bgxx_gmp_gmi_txx_ctl_s {
1733 u64 reserved_2_63 : 62;
1734 u64 xsdef_en : 1;
1735 u64 xscol_en : 1;
1736 } s;
1737 struct cvmx_bgxx_gmp_gmi_txx_ctl_s cn73xx;
1738 struct cvmx_bgxx_gmp_gmi_txx_ctl_s cn78xx;
1739 struct cvmx_bgxx_gmp_gmi_txx_ctl_s cn78xxp1;
1740 struct cvmx_bgxx_gmp_gmi_txx_ctl_s cnf75xx;
1741};
1742
1743typedef union cvmx_bgxx_gmp_gmi_txx_ctl cvmx_bgxx_gmp_gmi_txx_ctl_t;
1744
1745/**
1746 * cvmx_bgx#_gmp_gmi_tx#_int
1747 */
1748union cvmx_bgxx_gmp_gmi_txx_int {
1749 u64 u64;
1750 struct cvmx_bgxx_gmp_gmi_txx_int_s {
1751 u64 reserved_5_63 : 59;
1752 u64 ptp_lost : 1;
1753 u64 late_col : 1;
1754 u64 xsdef : 1;
1755 u64 xscol : 1;
1756 u64 undflw : 1;
1757 } s;
1758 struct cvmx_bgxx_gmp_gmi_txx_int_s cn73xx;
1759 struct cvmx_bgxx_gmp_gmi_txx_int_s cn78xx;
1760 struct cvmx_bgxx_gmp_gmi_txx_int_s cn78xxp1;
1761 struct cvmx_bgxx_gmp_gmi_txx_int_s cnf75xx;
1762};
1763
1764typedef union cvmx_bgxx_gmp_gmi_txx_int cvmx_bgxx_gmp_gmi_txx_int_t;
1765
1766/**
1767 * cvmx_bgx#_gmp_gmi_tx#_min_pkt
1768 */
1769union cvmx_bgxx_gmp_gmi_txx_min_pkt {
1770 u64 u64;
1771 struct cvmx_bgxx_gmp_gmi_txx_min_pkt_s {
1772 u64 reserved_8_63 : 56;
1773 u64 min_size : 8;
1774 } s;
1775 struct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn73xx;
1776 struct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn78xx;
1777 struct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn78xxp1;
1778 struct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cnf75xx;
1779};
1780
1781typedef union cvmx_bgxx_gmp_gmi_txx_min_pkt cvmx_bgxx_gmp_gmi_txx_min_pkt_t;
1782
1783/**
1784 * cvmx_bgx#_gmp_gmi_tx#_pause_pkt_interval
1785 *
1786 * This register specifies how often PAUSE packets are sent.
1787 *
1788 */
1789union cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval {
1790 u64 u64;
1791 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s {
1792 u64 reserved_16_63 : 48;
1793 u64 interval : 16;
1794 } s;
1795 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn73xx;
1796 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn78xx;
1797 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn78xxp1;
1798 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cnf75xx;
1799};
1800
1801typedef union cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_t;
1802
1803/**
1804 * cvmx_bgx#_gmp_gmi_tx#_pause_pkt_time
1805 */
1806union cvmx_bgxx_gmp_gmi_txx_pause_pkt_time {
1807 u64 u64;
1808 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s {
1809 u64 reserved_16_63 : 48;
1810 u64 ptime : 16;
1811 } s;
1812 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn73xx;
1813 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn78xx;
1814 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn78xxp1;
1815 struct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cnf75xx;
1816};
1817
1818typedef union cvmx_bgxx_gmp_gmi_txx_pause_pkt_time cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_t;
1819
1820/**
1821 * cvmx_bgx#_gmp_gmi_tx#_pause_togo
1822 */
1823union cvmx_bgxx_gmp_gmi_txx_pause_togo {
1824 u64 u64;
1825 struct cvmx_bgxx_gmp_gmi_txx_pause_togo_s {
1826 u64 reserved_16_63 : 48;
1827 u64 ptime : 16;
1828 } s;
1829 struct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn73xx;
1830 struct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn78xx;
1831 struct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn78xxp1;
1832 struct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cnf75xx;
1833};
1834
1835typedef union cvmx_bgxx_gmp_gmi_txx_pause_togo cvmx_bgxx_gmp_gmi_txx_pause_togo_t;
1836
1837/**
1838 * cvmx_bgx#_gmp_gmi_tx#_pause_zero
1839 */
1840union cvmx_bgxx_gmp_gmi_txx_pause_zero {
1841 u64 u64;
1842 struct cvmx_bgxx_gmp_gmi_txx_pause_zero_s {
1843 u64 reserved_1_63 : 63;
1844 u64 send : 1;
1845 } s;
1846 struct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn73xx;
1847 struct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn78xx;
1848 struct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn78xxp1;
1849 struct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cnf75xx;
1850};
1851
1852typedef union cvmx_bgxx_gmp_gmi_txx_pause_zero cvmx_bgxx_gmp_gmi_txx_pause_zero_t;
1853
1854/**
1855 * cvmx_bgx#_gmp_gmi_tx#_sgmii_ctl
1856 */
1857union cvmx_bgxx_gmp_gmi_txx_sgmii_ctl {
1858 u64 u64;
1859 struct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s {
1860 u64 reserved_1_63 : 63;
1861 u64 align : 1;
1862 } s;
1863 struct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn73xx;
1864 struct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn78xx;
1865 struct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn78xxp1;
1866 struct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cnf75xx;
1867};
1868
1869typedef union cvmx_bgxx_gmp_gmi_txx_sgmii_ctl cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_t;
1870
1871/**
1872 * cvmx_bgx#_gmp_gmi_tx#_slot
1873 */
1874union cvmx_bgxx_gmp_gmi_txx_slot {
1875 u64 u64;
1876 struct cvmx_bgxx_gmp_gmi_txx_slot_s {
1877 u64 reserved_10_63 : 54;
1878 u64 slot : 10;
1879 } s;
1880 struct cvmx_bgxx_gmp_gmi_txx_slot_s cn73xx;
1881 struct cvmx_bgxx_gmp_gmi_txx_slot_s cn78xx;
1882 struct cvmx_bgxx_gmp_gmi_txx_slot_s cn78xxp1;
1883 struct cvmx_bgxx_gmp_gmi_txx_slot_s cnf75xx;
1884};
1885
1886typedef union cvmx_bgxx_gmp_gmi_txx_slot cvmx_bgxx_gmp_gmi_txx_slot_t;
1887
1888/**
1889 * cvmx_bgx#_gmp_gmi_tx#_soft_pause
1890 */
1891union cvmx_bgxx_gmp_gmi_txx_soft_pause {
1892 u64 u64;
1893 struct cvmx_bgxx_gmp_gmi_txx_soft_pause_s {
1894 u64 reserved_16_63 : 48;
1895 u64 ptime : 16;
1896 } s;
1897 struct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn73xx;
1898 struct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn78xx;
1899 struct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn78xxp1;
1900 struct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cnf75xx;
1901};
1902
1903typedef union cvmx_bgxx_gmp_gmi_txx_soft_pause cvmx_bgxx_gmp_gmi_txx_soft_pause_t;
1904
1905/**
1906 * cvmx_bgx#_gmp_gmi_tx#_thresh
1907 */
1908union cvmx_bgxx_gmp_gmi_txx_thresh {
1909 u64 u64;
1910 struct cvmx_bgxx_gmp_gmi_txx_thresh_s {
1911 u64 reserved_11_63 : 53;
1912 u64 cnt : 11;
1913 } s;
1914 struct cvmx_bgxx_gmp_gmi_txx_thresh_s cn73xx;
1915 struct cvmx_bgxx_gmp_gmi_txx_thresh_s cn78xx;
1916 struct cvmx_bgxx_gmp_gmi_txx_thresh_s cn78xxp1;
1917 struct cvmx_bgxx_gmp_gmi_txx_thresh_s cnf75xx;
1918};
1919
1920typedef union cvmx_bgxx_gmp_gmi_txx_thresh cvmx_bgxx_gmp_gmi_txx_thresh_t;
1921
1922/**
1923 * cvmx_bgx#_gmp_gmi_tx_col_attempt
1924 */
1925union cvmx_bgxx_gmp_gmi_tx_col_attempt {
1926 u64 u64;
1927 struct cvmx_bgxx_gmp_gmi_tx_col_attempt_s {
1928 u64 reserved_5_63 : 59;
1929 u64 limit : 5;
1930 } s;
1931 struct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn73xx;
1932 struct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn78xx;
1933 struct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn78xxp1;
1934 struct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cnf75xx;
1935};
1936
1937typedef union cvmx_bgxx_gmp_gmi_tx_col_attempt cvmx_bgxx_gmp_gmi_tx_col_attempt_t;
1938
1939/**
1940 * cvmx_bgx#_gmp_gmi_tx_ifg
1941 *
1942 * Consider the following when programming IFG1 and IFG2:
1943 * * For 10/100/1000 Mb/s half-duplex systems that require IEEE 802.3 compatibility, IFG1 must be
1944 * in the range of 1-8, IFG2 must be in the range of 4-12, and the IFG1 + IFG2 sum must be 12.
1945 * * For 10/100/1000 Mb/s full-duplex systems that require IEEE 802.3 compatibility, IFG1 must be
1946 * in the range of 1-11, IFG2 must be in the range of 1-11, and the IFG1 + IFG2 sum must be 12.
1947 * For all other systems, IFG1 and IFG2 can be any value in the range of 1-15, allowing for a
1948 * total possible IFG sum of 2-30.
1949 */
1950union cvmx_bgxx_gmp_gmi_tx_ifg {
1951 u64 u64;
1952 struct cvmx_bgxx_gmp_gmi_tx_ifg_s {
1953 u64 reserved_8_63 : 56;
1954 u64 ifg2 : 4;
1955 u64 ifg1 : 4;
1956 } s;
1957 struct cvmx_bgxx_gmp_gmi_tx_ifg_s cn73xx;
1958 struct cvmx_bgxx_gmp_gmi_tx_ifg_s cn78xx;
1959 struct cvmx_bgxx_gmp_gmi_tx_ifg_s cn78xxp1;
1960 struct cvmx_bgxx_gmp_gmi_tx_ifg_s cnf75xx;
1961};
1962
1963typedef union cvmx_bgxx_gmp_gmi_tx_ifg cvmx_bgxx_gmp_gmi_tx_ifg_t;
1964
1965/**
1966 * cvmx_bgx#_gmp_gmi_tx_jam
1967 *
1968 * This register provides the pattern used in JAM bytes.
1969 *
1970 */
1971union cvmx_bgxx_gmp_gmi_tx_jam {
1972 u64 u64;
1973 struct cvmx_bgxx_gmp_gmi_tx_jam_s {
1974 u64 reserved_8_63 : 56;
1975 u64 jam : 8;
1976 } s;
1977 struct cvmx_bgxx_gmp_gmi_tx_jam_s cn73xx;
1978 struct cvmx_bgxx_gmp_gmi_tx_jam_s cn78xx;
1979 struct cvmx_bgxx_gmp_gmi_tx_jam_s cn78xxp1;
1980 struct cvmx_bgxx_gmp_gmi_tx_jam_s cnf75xx;
1981};
1982
1983typedef union cvmx_bgxx_gmp_gmi_tx_jam cvmx_bgxx_gmp_gmi_tx_jam_t;
1984
1985/**
1986 * cvmx_bgx#_gmp_gmi_tx_lfsr
1987 *
1988 * This register shows the contents of the linear feedback shift register (LFSR), which is used
1989 * to implement truncated binary exponential backoff.
1990 */
1991union cvmx_bgxx_gmp_gmi_tx_lfsr {
1992 u64 u64;
1993 struct cvmx_bgxx_gmp_gmi_tx_lfsr_s {
1994 u64 reserved_16_63 : 48;
1995 u64 lfsr : 16;
1996 } s;
1997 struct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn73xx;
1998 struct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn78xx;
1999 struct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn78xxp1;
2000 struct cvmx_bgxx_gmp_gmi_tx_lfsr_s cnf75xx;
2001};
2002
2003typedef union cvmx_bgxx_gmp_gmi_tx_lfsr cvmx_bgxx_gmp_gmi_tx_lfsr_t;
2004
2005/**
2006 * cvmx_bgx#_gmp_gmi_tx_pause_pkt_dmac
2007 */
2008union cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac {
2009 u64 u64;
2010 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s {
2011 u64 reserved_48_63 : 16;
2012 u64 dmac : 48;
2013 } s;
2014 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn73xx;
2015 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn78xx;
2016 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn78xxp1;
2017 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cnf75xx;
2018};
2019
2020typedef union cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_t;
2021
2022/**
2023 * cvmx_bgx#_gmp_gmi_tx_pause_pkt_type
2024 *
2025 * This register provides the PTYPE field that is placed in outbound PAUSE packets.
2026 *
2027 */
2028union cvmx_bgxx_gmp_gmi_tx_pause_pkt_type {
2029 u64 u64;
2030 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s {
2031 u64 reserved_16_63 : 48;
2032 u64 ptype : 16;
2033 } s;
2034 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn73xx;
2035 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn78xx;
2036 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn78xxp1;
2037 struct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cnf75xx;
2038};
2039
2040typedef union cvmx_bgxx_gmp_gmi_tx_pause_pkt_type cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_t;
2041
2042/**
2043 * cvmx_bgx#_gmp_pcs_an#_adv
2044 */
2045union cvmx_bgxx_gmp_pcs_anx_adv {
2046 u64 u64;
2047 struct cvmx_bgxx_gmp_pcs_anx_adv_s {
2048 u64 reserved_16_63 : 48;
2049 u64 np : 1;
2050 u64 reserved_14_14 : 1;
2051 u64 rem_flt : 2;
2052 u64 reserved_9_11 : 3;
2053 u64 pause : 2;
2054 u64 hfd : 1;
2055 u64 fd : 1;
2056 u64 reserved_0_4 : 5;
2057 } s;
2058 struct cvmx_bgxx_gmp_pcs_anx_adv_s cn73xx;
2059 struct cvmx_bgxx_gmp_pcs_anx_adv_s cn78xx;
2060 struct cvmx_bgxx_gmp_pcs_anx_adv_s cn78xxp1;
2061 struct cvmx_bgxx_gmp_pcs_anx_adv_s cnf75xx;
2062};
2063
2064typedef union cvmx_bgxx_gmp_pcs_anx_adv cvmx_bgxx_gmp_pcs_anx_adv_t;
2065
2066/**
2067 * cvmx_bgx#_gmp_pcs_an#_ext_st
2068 */
2069union cvmx_bgxx_gmp_pcs_anx_ext_st {
2070 u64 u64;
2071 struct cvmx_bgxx_gmp_pcs_anx_ext_st_s {
2072 u64 reserved_16_63 : 48;
2073 u64 thou_xfd : 1;
2074 u64 thou_xhd : 1;
2075 u64 thou_tfd : 1;
2076 u64 thou_thd : 1;
2077 u64 reserved_0_11 : 12;
2078 } s;
2079 struct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn73xx;
2080 struct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn78xx;
2081 struct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn78xxp1;
2082 struct cvmx_bgxx_gmp_pcs_anx_ext_st_s cnf75xx;
2083};
2084
2085typedef union cvmx_bgxx_gmp_pcs_anx_ext_st cvmx_bgxx_gmp_pcs_anx_ext_st_t;
2086
2087/**
2088 * cvmx_bgx#_gmp_pcs_an#_lp_abil
2089 *
2090 * This is the autonegotiation link partner ability register 5 as per IEEE 802.3, Clause 37.
2091 *
2092 */
2093union cvmx_bgxx_gmp_pcs_anx_lp_abil {
2094 u64 u64;
2095 struct cvmx_bgxx_gmp_pcs_anx_lp_abil_s {
2096 u64 reserved_16_63 : 48;
2097 u64 np : 1;
2098 u64 ack : 1;
2099 u64 rem_flt : 2;
2100 u64 reserved_9_11 : 3;
2101 u64 pause : 2;
2102 u64 hfd : 1;
2103 u64 fd : 1;
2104 u64 reserved_0_4 : 5;
2105 } s;
2106 struct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn73xx;
2107 struct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn78xx;
2108 struct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn78xxp1;
2109 struct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cnf75xx;
2110};
2111
2112typedef union cvmx_bgxx_gmp_pcs_anx_lp_abil cvmx_bgxx_gmp_pcs_anx_lp_abil_t;
2113
2114/**
2115 * cvmx_bgx#_gmp_pcs_an#_results
2116 *
2117 * This register is not valid when BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 1. If
2118 * BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 0 and
2119 * BGX()_GMP_PCS_AN()_RESULTS[AN_CPT] is set to 1, this register is valid.
2120 */
2121union cvmx_bgxx_gmp_pcs_anx_results {
2122 u64 u64;
2123 struct cvmx_bgxx_gmp_pcs_anx_results_s {
2124 u64 reserved_7_63 : 57;
2125 u64 pause : 2;
2126 u64 spd : 2;
2127 u64 an_cpt : 1;
2128 u64 dup : 1;
2129 u64 link_ok : 1;
2130 } s;
2131 struct cvmx_bgxx_gmp_pcs_anx_results_s cn73xx;
2132 struct cvmx_bgxx_gmp_pcs_anx_results_s cn78xx;
2133 struct cvmx_bgxx_gmp_pcs_anx_results_s cn78xxp1;
2134 struct cvmx_bgxx_gmp_pcs_anx_results_s cnf75xx;
2135};
2136
2137typedef union cvmx_bgxx_gmp_pcs_anx_results cvmx_bgxx_gmp_pcs_anx_results_t;
2138
2139/**
2140 * cvmx_bgx#_gmp_pcs_int#
2141 */
2142union cvmx_bgxx_gmp_pcs_intx {
2143 u64 u64;
2144 struct cvmx_bgxx_gmp_pcs_intx_s {
2145 u64 reserved_13_63 : 51;
2146 u64 dbg_sync : 1;
2147 u64 dup : 1;
2148 u64 sync_bad : 1;
2149 u64 an_bad : 1;
2150 u64 rxlock : 1;
2151 u64 rxbad : 1;
2152 u64 rxerr : 1;
2153 u64 txbad : 1;
2154 u64 txfifo : 1;
2155 u64 txfifu : 1;
2156 u64 an_err : 1;
2157 u64 xmit : 1;
2158 u64 lnkspd : 1;
2159 } s;
2160 struct cvmx_bgxx_gmp_pcs_intx_s cn73xx;
2161 struct cvmx_bgxx_gmp_pcs_intx_s cn78xx;
2162 struct cvmx_bgxx_gmp_pcs_intx_s cn78xxp1;
2163 struct cvmx_bgxx_gmp_pcs_intx_s cnf75xx;
2164};
2165
2166typedef union cvmx_bgxx_gmp_pcs_intx cvmx_bgxx_gmp_pcs_intx_t;
2167
2168/**
2169 * cvmx_bgx#_gmp_pcs_link#_timer
2170 *
2171 * This is the 1.6 ms nominal link timer register.
2172 *
2173 */
2174union cvmx_bgxx_gmp_pcs_linkx_timer {
2175 u64 u64;
2176 struct cvmx_bgxx_gmp_pcs_linkx_timer_s {
2177 u64 reserved_16_63 : 48;
2178 u64 count : 16;
2179 } s;
2180 struct cvmx_bgxx_gmp_pcs_linkx_timer_s cn73xx;
2181 struct cvmx_bgxx_gmp_pcs_linkx_timer_s cn78xx;
2182 struct cvmx_bgxx_gmp_pcs_linkx_timer_s cn78xxp1;
2183 struct cvmx_bgxx_gmp_pcs_linkx_timer_s cnf75xx;
2184};
2185
2186typedef union cvmx_bgxx_gmp_pcs_linkx_timer cvmx_bgxx_gmp_pcs_linkx_timer_t;
2187
2188/**
2189 * cvmx_bgx#_gmp_pcs_misc#_ctl
2190 */
2191union cvmx_bgxx_gmp_pcs_miscx_ctl {
2192 u64 u64;
2193 struct cvmx_bgxx_gmp_pcs_miscx_ctl_s {
2194 u64 reserved_13_63 : 51;
2195 u64 sgmii : 1;
2196 u64 gmxeno : 1;
2197 u64 loopbck2 : 1;
2198 u64 mac_phy : 1;
2199 u64 mode : 1;
2200 u64 an_ovrd : 1;
2201 u64 samp_pt : 7;
2202 } s;
2203 struct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn73xx;
2204 struct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn78xx;
2205 struct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn78xxp1;
2206 struct cvmx_bgxx_gmp_pcs_miscx_ctl_s cnf75xx;
2207};
2208
2209typedef union cvmx_bgxx_gmp_pcs_miscx_ctl cvmx_bgxx_gmp_pcs_miscx_ctl_t;
2210
2211/**
2212 * cvmx_bgx#_gmp_pcs_mr#_control
2213 */
2214union cvmx_bgxx_gmp_pcs_mrx_control {
2215 u64 u64;
2216 struct cvmx_bgxx_gmp_pcs_mrx_control_s {
2217 u64 reserved_16_63 : 48;
2218 u64 reset : 1;
2219 u64 loopbck1 : 1;
2220 u64 spdlsb : 1;
2221 u64 an_en : 1;
2222 u64 pwr_dn : 1;
2223 u64 reserved_10_10 : 1;
2224 u64 rst_an : 1;
2225 u64 dup : 1;
2226 u64 coltst : 1;
2227 u64 spdmsb : 1;
2228 u64 uni : 1;
2229 u64 reserved_0_4 : 5;
2230 } s;
2231 struct cvmx_bgxx_gmp_pcs_mrx_control_s cn73xx;
2232 struct cvmx_bgxx_gmp_pcs_mrx_control_s cn78xx;
2233 struct cvmx_bgxx_gmp_pcs_mrx_control_s cn78xxp1;
2234 struct cvmx_bgxx_gmp_pcs_mrx_control_s cnf75xx;
2235};
2236
2237typedef union cvmx_bgxx_gmp_pcs_mrx_control cvmx_bgxx_gmp_pcs_mrx_control_t;
2238
2239/**
2240 * cvmx_bgx#_gmp_pcs_mr#_status
2241 *
2242 * Bits <15:9> in this register indicate the ability to operate when
2243 * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set to MAC mode. Bits <15:9> are always read as
2244 * 0, indicating that the chip cannot operate in the corresponding modes. The field [RM_FLT] is a
2245 * 'don't care' when the selected mode is SGMII.
2246 */
2247union cvmx_bgxx_gmp_pcs_mrx_status {
2248 u64 u64;
2249 struct cvmx_bgxx_gmp_pcs_mrx_status_s {
2250 u64 reserved_16_63 : 48;
2251 u64 hun_t4 : 1;
2252 u64 hun_xfd : 1;
2253 u64 hun_xhd : 1;
2254 u64 ten_fd : 1;
2255 u64 ten_hd : 1;
2256 u64 hun_t2fd : 1;
2257 u64 hun_t2hd : 1;
2258 u64 ext_st : 1;
2259 u64 reserved_7_7 : 1;
2260 u64 prb_sup : 1;
2261 u64 an_cpt : 1;
2262 u64 rm_flt : 1;
2263 u64 an_abil : 1;
2264 u64 lnk_st : 1;
2265 u64 reserved_1_1 : 1;
2266 u64 extnd : 1;
2267 } s;
2268 struct cvmx_bgxx_gmp_pcs_mrx_status_s cn73xx;
2269 struct cvmx_bgxx_gmp_pcs_mrx_status_s cn78xx;
2270 struct cvmx_bgxx_gmp_pcs_mrx_status_s cn78xxp1;
2271 struct cvmx_bgxx_gmp_pcs_mrx_status_s cnf75xx;
2272};
2273
2274typedef union cvmx_bgxx_gmp_pcs_mrx_status cvmx_bgxx_gmp_pcs_mrx_status_t;
2275
2276/**
2277 * cvmx_bgx#_gmp_pcs_rx#_states
2278 */
2279union cvmx_bgxx_gmp_pcs_rxx_states {
2280 u64 u64;
2281 struct cvmx_bgxx_gmp_pcs_rxx_states_s {
2282 u64 reserved_16_63 : 48;
2283 u64 rx_bad : 1;
2284 u64 rx_st : 5;
2285 u64 sync_bad : 1;
2286 u64 sync : 4;
2287 u64 an_bad : 1;
2288 u64 an_st : 4;
2289 } s;
2290 struct cvmx_bgxx_gmp_pcs_rxx_states_s cn73xx;
2291 struct cvmx_bgxx_gmp_pcs_rxx_states_s cn78xx;
2292 struct cvmx_bgxx_gmp_pcs_rxx_states_s cn78xxp1;
2293 struct cvmx_bgxx_gmp_pcs_rxx_states_s cnf75xx;
2294};
2295
2296typedef union cvmx_bgxx_gmp_pcs_rxx_states cvmx_bgxx_gmp_pcs_rxx_states_t;
2297
2298/**
2299 * cvmx_bgx#_gmp_pcs_rx#_sync
2300 */
2301union cvmx_bgxx_gmp_pcs_rxx_sync {
2302 u64 u64;
2303 struct cvmx_bgxx_gmp_pcs_rxx_sync_s {
2304 u64 reserved_2_63 : 62;
2305 u64 sync : 1;
2306 u64 bit_lock : 1;
2307 } s;
2308 struct cvmx_bgxx_gmp_pcs_rxx_sync_s cn73xx;
2309 struct cvmx_bgxx_gmp_pcs_rxx_sync_s cn78xx;
2310 struct cvmx_bgxx_gmp_pcs_rxx_sync_s cn78xxp1;
2311 struct cvmx_bgxx_gmp_pcs_rxx_sync_s cnf75xx;
2312};
2313
2314typedef union cvmx_bgxx_gmp_pcs_rxx_sync cvmx_bgxx_gmp_pcs_rxx_sync_t;
2315
2316/**
2317 * cvmx_bgx#_gmp_pcs_sgm#_an_adv
2318 *
2319 * This is the SGMII autonegotiation advertisement register (sent out as tx_Config_Reg<15:0> as
2320 * defined in IEEE 802.3 clause 37). This register is sent during autonegotiation if
2321 * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set (1 = PHY mode). If the bit is not set (0 =
2322 * MAC mode), then tx_Config_Reg<14> becomes ACK bit and tx_Config_Reg<0> is always 1. All other
2323 * bits in tx_Config_Reg sent will be 0. The PHY dictates the autonegotiation results.
2324 */
2325union cvmx_bgxx_gmp_pcs_sgmx_an_adv {
2326 u64 u64;
2327 struct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s {
2328 u64 reserved_16_63 : 48;
2329 u64 link : 1;
2330 u64 ack : 1;
2331 u64 reserved_13_13 : 1;
2332 u64 dup : 1;
2333 u64 speed : 2;
2334 u64 reserved_1_9 : 9;
2335 u64 one : 1;
2336 } s;
2337 struct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn73xx;
2338 struct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn78xx;
2339 struct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn78xxp1;
2340 struct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cnf75xx;
2341};
2342
2343typedef union cvmx_bgxx_gmp_pcs_sgmx_an_adv cvmx_bgxx_gmp_pcs_sgmx_an_adv_t;
2344
2345/**
2346 * cvmx_bgx#_gmp_pcs_sgm#_lp_adv
2347 *
2348 * This is the SGMII link partner advertisement register (received as rx_Config_Reg<15:0> as
2349 * defined in IEEE 802.3 clause 37).
2350 */
2351union cvmx_bgxx_gmp_pcs_sgmx_lp_adv {
2352 u64 u64;
2353 struct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s {
2354 u64 reserved_16_63 : 48;
2355 u64 link : 1;
2356 u64 reserved_13_14 : 2;
2357 u64 dup : 1;
2358 u64 speed : 2;
2359 u64 reserved_1_9 : 9;
2360 u64 one : 1;
2361 } s;
2362 struct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn73xx;
2363 struct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn78xx;
2364 struct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn78xxp1;
2365 struct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cnf75xx;
2366};
2367
2368typedef union cvmx_bgxx_gmp_pcs_sgmx_lp_adv cvmx_bgxx_gmp_pcs_sgmx_lp_adv_t;
2369
2370/**
2371 * cvmx_bgx#_gmp_pcs_tx#_states
2372 */
2373union cvmx_bgxx_gmp_pcs_txx_states {
2374 u64 u64;
2375 struct cvmx_bgxx_gmp_pcs_txx_states_s {
2376 u64 reserved_7_63 : 57;
2377 u64 xmit : 2;
2378 u64 tx_bad : 1;
2379 u64 ord_st : 4;
2380 } s;
2381 struct cvmx_bgxx_gmp_pcs_txx_states_s cn73xx;
2382 struct cvmx_bgxx_gmp_pcs_txx_states_s cn78xx;
2383 struct cvmx_bgxx_gmp_pcs_txx_states_s cn78xxp1;
2384 struct cvmx_bgxx_gmp_pcs_txx_states_s cnf75xx;
2385};
2386
2387typedef union cvmx_bgxx_gmp_pcs_txx_states cvmx_bgxx_gmp_pcs_txx_states_t;
2388
2389/**
2390 * cvmx_bgx#_gmp_pcs_tx_rx#_polarity
2391 *
2392 * BGX()_GMP_PCS_TX_RX()_POLARITY[AUTORXPL] shows correct polarity needed on the link
2393 * receive path after code group synchronization is achieved.
2394 */
2395union cvmx_bgxx_gmp_pcs_tx_rxx_polarity {
2396 u64 u64;
2397 struct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s {
2398 u64 reserved_4_63 : 60;
2399 u64 rxovrd : 1;
2400 u64 autorxpl : 1;
2401 u64 rxplrt : 1;
2402 u64 txplrt : 1;
2403 } s;
2404 struct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn73xx;
2405 struct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn78xx;
2406 struct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn78xxp1;
2407 struct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cnf75xx;
2408};
2409
2410typedef union cvmx_bgxx_gmp_pcs_tx_rxx_polarity cvmx_bgxx_gmp_pcs_tx_rxx_polarity_t;
2411
2412/**
2413 * cvmx_bgx#_smu#_cbfc_ctl
2414 */
2415union cvmx_bgxx_smux_cbfc_ctl {
2416 u64 u64;
2417 struct cvmx_bgxx_smux_cbfc_ctl_s {
2418 u64 phys_en : 16;
2419 u64 logl_en : 16;
2420 u64 reserved_4_31 : 28;
2421 u64 bck_en : 1;
2422 u64 drp_en : 1;
2423 u64 tx_en : 1;
2424 u64 rx_en : 1;
2425 } s;
2426 struct cvmx_bgxx_smux_cbfc_ctl_s cn73xx;
2427 struct cvmx_bgxx_smux_cbfc_ctl_s cn78xx;
2428 struct cvmx_bgxx_smux_cbfc_ctl_s cn78xxp1;
2429 struct cvmx_bgxx_smux_cbfc_ctl_s cnf75xx;
2430};
2431
2432typedef union cvmx_bgxx_smux_cbfc_ctl cvmx_bgxx_smux_cbfc_ctl_t;
2433
2434/**
2435 * cvmx_bgx#_smu#_ctrl
2436 */
2437union cvmx_bgxx_smux_ctrl {
2438 u64 u64;
2439 struct cvmx_bgxx_smux_ctrl_s {
2440 u64 reserved_2_63 : 62;
2441 u64 tx_idle : 1;
2442 u64 rx_idle : 1;
2443 } s;
2444 struct cvmx_bgxx_smux_ctrl_s cn73xx;
2445 struct cvmx_bgxx_smux_ctrl_s cn78xx;
2446 struct cvmx_bgxx_smux_ctrl_s cn78xxp1;
2447 struct cvmx_bgxx_smux_ctrl_s cnf75xx;
2448};
2449
2450typedef union cvmx_bgxx_smux_ctrl cvmx_bgxx_smux_ctrl_t;
2451
2452/**
2453 * cvmx_bgx#_smu#_ext_loopback
2454 *
2455 * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise one
2456 * of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].
2457 */
2458union cvmx_bgxx_smux_ext_loopback {
2459 u64 u64;
2460 struct cvmx_bgxx_smux_ext_loopback_s {
2461 u64 reserved_5_63 : 59;
2462 u64 en : 1;
2463 u64 thresh : 4;
2464 } s;
2465 struct cvmx_bgxx_smux_ext_loopback_s cn73xx;
2466 struct cvmx_bgxx_smux_ext_loopback_s cn78xx;
2467 struct cvmx_bgxx_smux_ext_loopback_s cn78xxp1;
2468 struct cvmx_bgxx_smux_ext_loopback_s cnf75xx;
2469};
2470
2471typedef union cvmx_bgxx_smux_ext_loopback cvmx_bgxx_smux_ext_loopback_t;
2472
2473/**
2474 * cvmx_bgx#_smu#_hg2_control
2475 *
2476 * HiGig2 TX- and RX-enable are normally set together for HiGig2 messaging. Setting just the TX
2477 * or RX bit results in only the HG2 message transmit or receive capability.
2478 *
2479 * Setting [PHYS_EN] and [LOGL_EN] to 1 allows link PAUSE or backpressure to PKO as per the
2480 * received HiGig2 message. Setting these fields to 0 disables link PAUSE and backpressure to PKO
2481 * in response to received messages.
2482 *
2483 * BGX()_SMU()_TX_CTL[HG_EN] must be set (to enable HiGig) whenever either [HG2TX_EN] or
2484 * [HG2RX_EN] are set. BGX()_SMU()_RX_UDD_SKP[LEN] must be set to 16 (to select HiGig2)
2485 * whenever either [HG2TX_EN] or [HG2RX_EN] are set.
2486 *
2487 * BGX()_CMR_RX_OVR_BP[EN]<0> must be set and BGX()_CMR_RX_OVR_BP[BP]<0> must be cleared
2488 * to 0 (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with the HiGig2
2489 * Protocol when [HG2TX_EN] = 0. (The HiGig2 protocol is indicated
2490 * by BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16.) Hardware
2491 * can only autogenerate backpressure via HiGig2 messages (optionally, when [HG2TX_EN] = 1) with
2492 * the HiGig2 protocol.
2493 */
2494union cvmx_bgxx_smux_hg2_control {
2495 u64 u64;
2496 struct cvmx_bgxx_smux_hg2_control_s {
2497 u64 reserved_19_63 : 45;
2498 u64 hg2tx_en : 1;
2499 u64 hg2rx_en : 1;
2500 u64 phys_en : 1;
2501 u64 logl_en : 16;
2502 } s;
2503 struct cvmx_bgxx_smux_hg2_control_s cn73xx;
2504 struct cvmx_bgxx_smux_hg2_control_s cn78xx;
2505 struct cvmx_bgxx_smux_hg2_control_s cn78xxp1;
2506 struct cvmx_bgxx_smux_hg2_control_s cnf75xx;
2507};
2508
2509typedef union cvmx_bgxx_smux_hg2_control cvmx_bgxx_smux_hg2_control_t;
2510
2511/**
2512 * cvmx_bgx#_smu#_rx_bad_col_hi
2513 */
2514union cvmx_bgxx_smux_rx_bad_col_hi {
2515 u64 u64;
2516 struct cvmx_bgxx_smux_rx_bad_col_hi_s {
2517 u64 reserved_17_63 : 47;
2518 u64 val : 1;
2519 u64 state : 8;
2520 u64 lane_rxc : 8;
2521 } s;
2522 struct cvmx_bgxx_smux_rx_bad_col_hi_s cn73xx;
2523 struct cvmx_bgxx_smux_rx_bad_col_hi_s cn78xx;
2524 struct cvmx_bgxx_smux_rx_bad_col_hi_s cn78xxp1;
2525 struct cvmx_bgxx_smux_rx_bad_col_hi_s cnf75xx;
2526};
2527
2528typedef union cvmx_bgxx_smux_rx_bad_col_hi cvmx_bgxx_smux_rx_bad_col_hi_t;
2529
2530/**
2531 * cvmx_bgx#_smu#_rx_bad_col_lo
2532 */
2533union cvmx_bgxx_smux_rx_bad_col_lo {
2534 u64 u64;
2535 struct cvmx_bgxx_smux_rx_bad_col_lo_s {
2536 u64 lane_rxd : 64;
2537 } s;
2538 struct cvmx_bgxx_smux_rx_bad_col_lo_s cn73xx;
2539 struct cvmx_bgxx_smux_rx_bad_col_lo_s cn78xx;
2540 struct cvmx_bgxx_smux_rx_bad_col_lo_s cn78xxp1;
2541 struct cvmx_bgxx_smux_rx_bad_col_lo_s cnf75xx;
2542};
2543
2544typedef union cvmx_bgxx_smux_rx_bad_col_lo cvmx_bgxx_smux_rx_bad_col_lo_t;
2545
2546/**
2547 * cvmx_bgx#_smu#_rx_ctl
2548 */
2549union cvmx_bgxx_smux_rx_ctl {
2550 u64 u64;
2551 struct cvmx_bgxx_smux_rx_ctl_s {
2552 u64 reserved_2_63 : 62;
2553 u64 status : 2;
2554 } s;
2555 struct cvmx_bgxx_smux_rx_ctl_s cn73xx;
2556 struct cvmx_bgxx_smux_rx_ctl_s cn78xx;
2557 struct cvmx_bgxx_smux_rx_ctl_s cn78xxp1;
2558 struct cvmx_bgxx_smux_rx_ctl_s cnf75xx;
2559};
2560
2561typedef union cvmx_bgxx_smux_rx_ctl cvmx_bgxx_smux_rx_ctl_t;
2562
2563/**
2564 * cvmx_bgx#_smu#_rx_decision
2565 *
2566 * This register specifies the byte count used to determine when to accept or to filter a packet.
2567 * As each byte in a packet is received by BGX, the L2 byte count (i.e. the number of bytes from
2568 * the beginning of the L2 header (DMAC)) is compared against CNT. In normal operation, the L2
2569 * header begins after the PREAMBLE + SFD (BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 1) and any
2570 * optional UDD skip data (BGX()_SMU()_RX_UDD_SKP[LEN]).
2571 */
2572union cvmx_bgxx_smux_rx_decision {
2573 u64 u64;
2574 struct cvmx_bgxx_smux_rx_decision_s {
2575 u64 reserved_5_63 : 59;
2576 u64 cnt : 5;
2577 } s;
2578 struct cvmx_bgxx_smux_rx_decision_s cn73xx;
2579 struct cvmx_bgxx_smux_rx_decision_s cn78xx;
2580 struct cvmx_bgxx_smux_rx_decision_s cn78xxp1;
2581 struct cvmx_bgxx_smux_rx_decision_s cnf75xx;
2582};
2583
2584typedef union cvmx_bgxx_smux_rx_decision cvmx_bgxx_smux_rx_decision_t;
2585
2586/**
2587 * cvmx_bgx#_smu#_rx_frm_chk
2588 *
2589 * The CSRs provide the enable bits for a subset of errors passed to CMR encoded.
2590 *
2591 */
2592union cvmx_bgxx_smux_rx_frm_chk {
2593 u64 u64;
2594 struct cvmx_bgxx_smux_rx_frm_chk_s {
2595 u64 reserved_9_63 : 55;
2596 u64 skperr : 1;
2597 u64 rcverr : 1;
2598 u64 reserved_6_6 : 1;
2599 u64 fcserr_c : 1;
2600 u64 fcserr_d : 1;
2601 u64 jabber : 1;
2602 u64 reserved_0_2 : 3;
2603 } s;
2604 struct cvmx_bgxx_smux_rx_frm_chk_s cn73xx;
2605 struct cvmx_bgxx_smux_rx_frm_chk_s cn78xx;
2606 struct cvmx_bgxx_smux_rx_frm_chk_s cn78xxp1;
2607 struct cvmx_bgxx_smux_rx_frm_chk_s cnf75xx;
2608};
2609
2610typedef union cvmx_bgxx_smux_rx_frm_chk cvmx_bgxx_smux_rx_frm_chk_t;
2611
2612/**
2613 * cvmx_bgx#_smu#_rx_frm_ctl
2614 *
2615 * This register controls the handling of the frames.
2616 * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The
2617 * most
2618 * common modes of operation:
2619 * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything
2620 * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames
2621 * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored
2622 *
2623 * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since
2624 * PAUSE
2625 * packets only apply to full duplex operation, any PAUSE packet would constitute an exception
2626 * which should be handled by the processing cores. PAUSE packets should not be forwarded.
2627 */
2628union cvmx_bgxx_smux_rx_frm_ctl {
2629 u64 u64;
2630 struct cvmx_bgxx_smux_rx_frm_ctl_s {
2631 u64 reserved_13_63 : 51;
2632 u64 ptp_mode : 1;
2633 u64 reserved_6_11 : 6;
2634 u64 ctl_smac : 1;
2635 u64 ctl_mcst : 1;
2636 u64 ctl_bck : 1;
2637 u64 ctl_drp : 1;
2638 u64 pre_strp : 1;
2639 u64 pre_chk : 1;
2640 } s;
2641 struct cvmx_bgxx_smux_rx_frm_ctl_s cn73xx;
2642 struct cvmx_bgxx_smux_rx_frm_ctl_s cn78xx;
2643 struct cvmx_bgxx_smux_rx_frm_ctl_s cn78xxp1;
2644 struct cvmx_bgxx_smux_rx_frm_ctl_s cnf75xx;
2645};
2646
2647typedef union cvmx_bgxx_smux_rx_frm_ctl cvmx_bgxx_smux_rx_frm_ctl_t;
2648
2649/**
2650 * cvmx_bgx#_smu#_rx_int
2651 *
2652 * SMU Interrupt Register.
2653 *
2654 */
2655union cvmx_bgxx_smux_rx_int {
2656 u64 u64;
2657 struct cvmx_bgxx_smux_rx_int_s {
2658 u64 reserved_12_63 : 52;
2659 u64 hg2cc : 1;
2660 u64 hg2fld : 1;
2661 u64 bad_term : 1;
2662 u64 bad_seq : 1;
2663 u64 rem_fault : 1;
2664 u64 loc_fault : 1;
2665 u64 rsverr : 1;
2666 u64 pcterr : 1;
2667 u64 skperr : 1;
2668 u64 rcverr : 1;
2669 u64 fcserr : 1;
2670 u64 jabber : 1;
2671 } s;
2672 struct cvmx_bgxx_smux_rx_int_s cn73xx;
2673 struct cvmx_bgxx_smux_rx_int_s cn78xx;
2674 struct cvmx_bgxx_smux_rx_int_s cn78xxp1;
2675 struct cvmx_bgxx_smux_rx_int_s cnf75xx;
2676};
2677
2678typedef union cvmx_bgxx_smux_rx_int cvmx_bgxx_smux_rx_int_t;
2679
2680/**
2681 * cvmx_bgx#_smu#_rx_jabber
2682 *
2683 * This register specifies the maximum size for packets, beyond which the SMU truncates. In
2684 * XAUI/RXAUI mode, port 0 is used for checking.
2685 */
2686union cvmx_bgxx_smux_rx_jabber {
2687 u64 u64;
2688 struct cvmx_bgxx_smux_rx_jabber_s {
2689 u64 reserved_16_63 : 48;
2690 u64 cnt : 16;
2691 } s;
2692 struct cvmx_bgxx_smux_rx_jabber_s cn73xx;
2693 struct cvmx_bgxx_smux_rx_jabber_s cn78xx;
2694 struct cvmx_bgxx_smux_rx_jabber_s cn78xxp1;
2695 struct cvmx_bgxx_smux_rx_jabber_s cnf75xx;
2696};
2697
2698typedef union cvmx_bgxx_smux_rx_jabber cvmx_bgxx_smux_rx_jabber_t;
2699
2700/**
2701 * cvmx_bgx#_smu#_rx_udd_skp
2702 *
2703 * This register specifies the amount of user-defined data (UDD) added before the start of the
2704 * L2C data.
2705 */
2706union cvmx_bgxx_smux_rx_udd_skp {
2707 u64 u64;
2708 struct cvmx_bgxx_smux_rx_udd_skp_s {
2709 u64 reserved_9_63 : 55;
2710 u64 fcssel : 1;
2711 u64 reserved_7_7 : 1;
2712 u64 len : 7;
2713 } s;
2714 struct cvmx_bgxx_smux_rx_udd_skp_s cn73xx;
2715 struct cvmx_bgxx_smux_rx_udd_skp_s cn78xx;
2716 struct cvmx_bgxx_smux_rx_udd_skp_s cn78xxp1;
2717 struct cvmx_bgxx_smux_rx_udd_skp_s cnf75xx;
2718};
2719
2720typedef union cvmx_bgxx_smux_rx_udd_skp cvmx_bgxx_smux_rx_udd_skp_t;
2721
2722/**
2723 * cvmx_bgx#_smu#_smac
2724 */
2725union cvmx_bgxx_smux_smac {
2726 u64 u64;
2727 struct cvmx_bgxx_smux_smac_s {
2728 u64 reserved_48_63 : 16;
2729 u64 smac : 48;
2730 } s;
2731 struct cvmx_bgxx_smux_smac_s cn73xx;
2732 struct cvmx_bgxx_smux_smac_s cn78xx;
2733 struct cvmx_bgxx_smux_smac_s cn78xxp1;
2734 struct cvmx_bgxx_smux_smac_s cnf75xx;
2735};
2736
2737typedef union cvmx_bgxx_smux_smac cvmx_bgxx_smux_smac_t;
2738
2739/**
2740 * cvmx_bgx#_smu#_tx_append
2741 *
2742 * For more details on the interactions between FCS and PAD, see also the description of
2743 * BGX()_SMU()_TX_MIN_PKT[MIN_SIZE].
2744 */
2745union cvmx_bgxx_smux_tx_append {
2746 u64 u64;
2747 struct cvmx_bgxx_smux_tx_append_s {
2748 u64 reserved_4_63 : 60;
2749 u64 fcs_c : 1;
2750 u64 fcs_d : 1;
2751 u64 pad : 1;
2752 u64 preamble : 1;
2753 } s;
2754 struct cvmx_bgxx_smux_tx_append_s cn73xx;
2755 struct cvmx_bgxx_smux_tx_append_s cn78xx;
2756 struct cvmx_bgxx_smux_tx_append_s cn78xxp1;
2757 struct cvmx_bgxx_smux_tx_append_s cnf75xx;
2758};
2759
2760typedef union cvmx_bgxx_smux_tx_append cvmx_bgxx_smux_tx_append_t;
2761
2762/**
2763 * cvmx_bgx#_smu#_tx_ctl
2764 */
2765union cvmx_bgxx_smux_tx_ctl {
2766 u64 u64;
2767 struct cvmx_bgxx_smux_tx_ctl_s {
2768 u64 reserved_31_63 : 33;
2769 u64 spu_mrk_cnt : 20;
2770 u64 hg_pause_hgi : 2;
2771 u64 hg_en : 1;
2772 u64 l2p_bp_conv : 1;
2773 u64 ls_byp : 1;
2774 u64 ls : 2;
2775 u64 reserved_3_3 : 1;
2776 u64 x4a_dis : 1;
2777 u64 uni_en : 1;
2778 u64 dic_en : 1;
2779 } s;
2780 struct cvmx_bgxx_smux_tx_ctl_s cn73xx;
2781 struct cvmx_bgxx_smux_tx_ctl_s cn78xx;
2782 struct cvmx_bgxx_smux_tx_ctl_s cn78xxp1;
2783 struct cvmx_bgxx_smux_tx_ctl_s cnf75xx;
2784};
2785
2786typedef union cvmx_bgxx_smux_tx_ctl cvmx_bgxx_smux_tx_ctl_t;
2787
2788/**
2789 * cvmx_bgx#_smu#_tx_ifg
2790 *
2791 * Programming IFG1 and IFG2:
2792 * * For XAUI/RXAUI/10Gbs/40Gbs systems that require IEEE 802.3 compatibility, the IFG1+IFG2 sum
2793 * must be 12.
2794 * * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise
2795 * one of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].
2796 */
2797union cvmx_bgxx_smux_tx_ifg {
2798 u64 u64;
2799 struct cvmx_bgxx_smux_tx_ifg_s {
2800 u64 reserved_8_63 : 56;
2801 u64 ifg2 : 4;
2802 u64 ifg1 : 4;
2803 } s;
2804 struct cvmx_bgxx_smux_tx_ifg_s cn73xx;
2805 struct cvmx_bgxx_smux_tx_ifg_s cn78xx;
2806 struct cvmx_bgxx_smux_tx_ifg_s cn78xxp1;
2807 struct cvmx_bgxx_smux_tx_ifg_s cnf75xx;
2808};
2809
2810typedef union cvmx_bgxx_smux_tx_ifg cvmx_bgxx_smux_tx_ifg_t;
2811
2812/**
2813 * cvmx_bgx#_smu#_tx_int
2814 */
2815union cvmx_bgxx_smux_tx_int {
2816 u64 u64;
2817 struct cvmx_bgxx_smux_tx_int_s {
2818 u64 reserved_5_63 : 59;
2819 u64 lb_ovrflw : 1;
2820 u64 lb_undflw : 1;
2821 u64 fake_commit : 1;
2822 u64 xchange : 1;
2823 u64 undflw : 1;
2824 } s;
2825 struct cvmx_bgxx_smux_tx_int_s cn73xx;
2826 struct cvmx_bgxx_smux_tx_int_s cn78xx;
2827 struct cvmx_bgxx_smux_tx_int_s cn78xxp1;
2828 struct cvmx_bgxx_smux_tx_int_s cnf75xx;
2829};
2830
2831typedef union cvmx_bgxx_smux_tx_int cvmx_bgxx_smux_tx_int_t;
2832
2833/**
2834 * cvmx_bgx#_smu#_tx_min_pkt
2835 */
2836union cvmx_bgxx_smux_tx_min_pkt {
2837 u64 u64;
2838 struct cvmx_bgxx_smux_tx_min_pkt_s {
2839 u64 reserved_8_63 : 56;
2840 u64 min_size : 8;
2841 } s;
2842 struct cvmx_bgxx_smux_tx_min_pkt_s cn73xx;
2843 struct cvmx_bgxx_smux_tx_min_pkt_s cn78xx;
2844 struct cvmx_bgxx_smux_tx_min_pkt_s cn78xxp1;
2845 struct cvmx_bgxx_smux_tx_min_pkt_s cnf75xx;
2846};
2847
2848typedef union cvmx_bgxx_smux_tx_min_pkt cvmx_bgxx_smux_tx_min_pkt_t;
2849
2850/**
2851 * cvmx_bgx#_smu#_tx_pause_pkt_dmac
2852 *
2853 * This register provides the DMAC value that is placed in outbound PAUSE packets.
2854 *
2855 */
2856union cvmx_bgxx_smux_tx_pause_pkt_dmac {
2857 u64 u64;
2858 struct cvmx_bgxx_smux_tx_pause_pkt_dmac_s {
2859 u64 reserved_48_63 : 16;
2860 u64 dmac : 48;
2861 } s;
2862 struct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn73xx;
2863 struct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn78xx;
2864 struct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn78xxp1;
2865 struct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cnf75xx;
2866};
2867
2868typedef union cvmx_bgxx_smux_tx_pause_pkt_dmac cvmx_bgxx_smux_tx_pause_pkt_dmac_t;
2869
2870/**
2871 * cvmx_bgx#_smu#_tx_pause_pkt_interval
2872 *
2873 * This register specifies how often PAUSE packets are sent.
2874 *
2875 */
2876union cvmx_bgxx_smux_tx_pause_pkt_interval {
2877 u64 u64;
2878 struct cvmx_bgxx_smux_tx_pause_pkt_interval_s {
2879 u64 reserved_33_63 : 31;
2880 u64 hg2_intra_en : 1;
2881 u64 hg2_intra_interval : 16;
2882 u64 interval : 16;
2883 } s;
2884 struct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn73xx;
2885 struct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn78xx;
2886 struct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn78xxp1;
2887 struct cvmx_bgxx_smux_tx_pause_pkt_interval_s cnf75xx;
2888};
2889
2890typedef union cvmx_bgxx_smux_tx_pause_pkt_interval cvmx_bgxx_smux_tx_pause_pkt_interval_t;
2891
2892/**
2893 * cvmx_bgx#_smu#_tx_pause_pkt_time
2894 */
2895union cvmx_bgxx_smux_tx_pause_pkt_time {
2896 u64 u64;
2897 struct cvmx_bgxx_smux_tx_pause_pkt_time_s {
2898 u64 reserved_16_63 : 48;
2899 u64 p_time : 16;
2900 } s;
2901 struct cvmx_bgxx_smux_tx_pause_pkt_time_s cn73xx;
2902 struct cvmx_bgxx_smux_tx_pause_pkt_time_s cn78xx;
2903 struct cvmx_bgxx_smux_tx_pause_pkt_time_s cn78xxp1;
2904 struct cvmx_bgxx_smux_tx_pause_pkt_time_s cnf75xx;
2905};
2906
2907typedef union cvmx_bgxx_smux_tx_pause_pkt_time cvmx_bgxx_smux_tx_pause_pkt_time_t;
2908
2909/**
2910 * cvmx_bgx#_smu#_tx_pause_pkt_type
2911 *
2912 * This register provides the P_TYPE field that is placed in outbound PAUSE packets.
2913 *
2914 */
2915union cvmx_bgxx_smux_tx_pause_pkt_type {
2916 u64 u64;
2917 struct cvmx_bgxx_smux_tx_pause_pkt_type_s {
2918 u64 reserved_16_63 : 48;
2919 u64 p_type : 16;
2920 } s;
2921 struct cvmx_bgxx_smux_tx_pause_pkt_type_s cn73xx;
2922 struct cvmx_bgxx_smux_tx_pause_pkt_type_s cn78xx;
2923 struct cvmx_bgxx_smux_tx_pause_pkt_type_s cn78xxp1;
2924 struct cvmx_bgxx_smux_tx_pause_pkt_type_s cnf75xx;
2925};
2926
2927typedef union cvmx_bgxx_smux_tx_pause_pkt_type cvmx_bgxx_smux_tx_pause_pkt_type_t;
2928
2929/**
2930 * cvmx_bgx#_smu#_tx_pause_togo
2931 */
2932union cvmx_bgxx_smux_tx_pause_togo {
2933 u64 u64;
2934 struct cvmx_bgxx_smux_tx_pause_togo_s {
2935 u64 reserved_32_63 : 32;
2936 u64 msg_time : 16;
2937 u64 p_time : 16;
2938 } s;
2939 struct cvmx_bgxx_smux_tx_pause_togo_s cn73xx;
2940 struct cvmx_bgxx_smux_tx_pause_togo_s cn78xx;
2941 struct cvmx_bgxx_smux_tx_pause_togo_s cn78xxp1;
2942 struct cvmx_bgxx_smux_tx_pause_togo_s cnf75xx;
2943};
2944
2945typedef union cvmx_bgxx_smux_tx_pause_togo cvmx_bgxx_smux_tx_pause_togo_t;
2946
2947/**
2948 * cvmx_bgx#_smu#_tx_pause_zero
2949 */
2950union cvmx_bgxx_smux_tx_pause_zero {
2951 u64 u64;
2952 struct cvmx_bgxx_smux_tx_pause_zero_s {
2953 u64 reserved_1_63 : 63;
2954 u64 send : 1;
2955 } s;
2956 struct cvmx_bgxx_smux_tx_pause_zero_s cn73xx;
2957 struct cvmx_bgxx_smux_tx_pause_zero_s cn78xx;
2958 struct cvmx_bgxx_smux_tx_pause_zero_s cn78xxp1;
2959 struct cvmx_bgxx_smux_tx_pause_zero_s cnf75xx;
2960};
2961
2962typedef union cvmx_bgxx_smux_tx_pause_zero cvmx_bgxx_smux_tx_pause_zero_t;
2963
2964/**
2965 * cvmx_bgx#_smu#_tx_soft_pause
2966 */
2967union cvmx_bgxx_smux_tx_soft_pause {
2968 u64 u64;
2969 struct cvmx_bgxx_smux_tx_soft_pause_s {
2970 u64 reserved_16_63 : 48;
2971 u64 p_time : 16;
2972 } s;
2973 struct cvmx_bgxx_smux_tx_soft_pause_s cn73xx;
2974 struct cvmx_bgxx_smux_tx_soft_pause_s cn78xx;
2975 struct cvmx_bgxx_smux_tx_soft_pause_s cn78xxp1;
2976 struct cvmx_bgxx_smux_tx_soft_pause_s cnf75xx;
2977};
2978
2979typedef union cvmx_bgxx_smux_tx_soft_pause cvmx_bgxx_smux_tx_soft_pause_t;
2980
2981/**
2982 * cvmx_bgx#_smu#_tx_thresh
2983 */
2984union cvmx_bgxx_smux_tx_thresh {
2985 u64 u64;
2986 struct cvmx_bgxx_smux_tx_thresh_s {
2987 u64 reserved_11_63 : 53;
2988 u64 cnt : 11;
2989 } s;
2990 struct cvmx_bgxx_smux_tx_thresh_s cn73xx;
2991 struct cvmx_bgxx_smux_tx_thresh_s cn78xx;
2992 struct cvmx_bgxx_smux_tx_thresh_s cn78xxp1;
2993 struct cvmx_bgxx_smux_tx_thresh_s cnf75xx;
2994};
2995
2996typedef union cvmx_bgxx_smux_tx_thresh cvmx_bgxx_smux_tx_thresh_t;
2997
2998/**
2999 * cvmx_bgx#_spu#_an_adv
3000 *
3001 * Software programs this register with the contents of the AN-link code word base page to be
3002 * transmitted during autonegotiation. (See IEEE 802.3 section 73.6 for details.) Any write
3003 * operations to this register prior to completion of autonegotiation, as indicated by
3004 * BGX()_SPU()_AN_STATUS[AN_COMPLETE], should be followed by a renegotiation in order for
3005 * the new values to take effect. Renegotiation is initiated by setting
3006 * BGX()_SPU()_AN_CONTROL[AN_RESTART]. Once autonegotiation has completed, software can
3007 * examine this register along with BGX()_SPU()_AN_LP_BASE to determine the highest
3008 * common denominator technology.
3009 */
3010union cvmx_bgxx_spux_an_adv {
3011 u64 u64;
3012 struct cvmx_bgxx_spux_an_adv_s {
3013 u64 reserved_48_63 : 16;
3014 u64 fec_req : 1;
3015 u64 fec_able : 1;
3016 u64 arsv : 19;
3017 u64 a100g_cr10 : 1;
3018 u64 a40g_cr4 : 1;
3019 u64 a40g_kr4 : 1;
3020 u64 a10g_kr : 1;
3021 u64 a10g_kx4 : 1;
3022 u64 a1g_kx : 1;
3023 u64 t : 5;
3024 u64 np : 1;
3025 u64 ack : 1;
3026 u64 rf : 1;
3027 u64 xnp_able : 1;
3028 u64 asm_dir : 1;
3029 u64 pause : 1;
3030 u64 e : 5;
3031 u64 s : 5;
3032 } s;
3033 struct cvmx_bgxx_spux_an_adv_s cn73xx;
3034 struct cvmx_bgxx_spux_an_adv_s cn78xx;
3035 struct cvmx_bgxx_spux_an_adv_s cn78xxp1;
3036 struct cvmx_bgxx_spux_an_adv_s cnf75xx;
3037};
3038
3039typedef union cvmx_bgxx_spux_an_adv cvmx_bgxx_spux_an_adv_t;
3040
3041/**
3042 * cvmx_bgx#_spu#_an_bp_status
3043 *
3044 * The contents of this register are updated
3045 * during autonegotiation and are valid when BGX()_SPU()_AN_STATUS[AN_COMPLETE] is set.
3046 * At that time, one of the port type bits ([N100G_CR10], [N40G_CR4], [N40G_KR4], [N10G_KR],
3047 * [N10G_KX4],
3048 * [N1G_KX]) will be set depending on the AN priority resolution. If a BASE-R type is negotiated,
3049 * then [FEC] will be set to indicate that FEC operation has been negotiated, and will be
3050 * clear otherwise.
3051 */
3052union cvmx_bgxx_spux_an_bp_status {
3053 u64 u64;
3054 struct cvmx_bgxx_spux_an_bp_status_s {
3055 u64 reserved_9_63 : 55;
3056 u64 n100g_cr10 : 1;
3057 u64 reserved_7_7 : 1;
3058 u64 n40g_cr4 : 1;
3059 u64 n40g_kr4 : 1;
3060 u64 fec : 1;
3061 u64 n10g_kr : 1;
3062 u64 n10g_kx4 : 1;
3063 u64 n1g_kx : 1;
3064 u64 bp_an_able : 1;
3065 } s;
3066 struct cvmx_bgxx_spux_an_bp_status_s cn73xx;
3067 struct cvmx_bgxx_spux_an_bp_status_s cn78xx;
3068 struct cvmx_bgxx_spux_an_bp_status_s cn78xxp1;
3069 struct cvmx_bgxx_spux_an_bp_status_s cnf75xx;
3070};
3071
3072typedef union cvmx_bgxx_spux_an_bp_status cvmx_bgxx_spux_an_bp_status_t;
3073
3074/**
3075 * cvmx_bgx#_spu#_an_control
3076 */
3077union cvmx_bgxx_spux_an_control {
3078 u64 u64;
3079 struct cvmx_bgxx_spux_an_control_s {
3080 u64 reserved_16_63 : 48;
3081 u64 an_reset : 1;
3082 u64 reserved_14_14 : 1;
3083 u64 xnp_en : 1;
3084 u64 an_en : 1;
3085 u64 reserved_10_11 : 2;
3086 u64 an_restart : 1;
3087 u64 reserved_0_8 : 9;
3088 } s;
3089 struct cvmx_bgxx_spux_an_control_s cn73xx;
3090 struct cvmx_bgxx_spux_an_control_s cn78xx;
3091 struct cvmx_bgxx_spux_an_control_s cn78xxp1;
3092 struct cvmx_bgxx_spux_an_control_s cnf75xx;
3093};
3094
3095typedef union cvmx_bgxx_spux_an_control cvmx_bgxx_spux_an_control_t;
3096
3097/**
3098 * cvmx_bgx#_spu#_an_lp_base
3099 *
3100 * This register captures the contents of the latest AN link code word base page received from
3101 * the link partner during autonegotiation. (See IEEE 802.3 section 73.6 for details.)
3102 * BGX()_SPU()_AN_STATUS[PAGE_RX] is set when this register is updated by hardware.
3103 */
3104union cvmx_bgxx_spux_an_lp_base {
3105 u64 u64;
3106 struct cvmx_bgxx_spux_an_lp_base_s {
3107 u64 reserved_48_63 : 16;
3108 u64 fec_req : 1;
3109 u64 fec_able : 1;
3110 u64 arsv : 19;
3111 u64 a100g_cr10 : 1;
3112 u64 a40g_cr4 : 1;
3113 u64 a40g_kr4 : 1;
3114 u64 a10g_kr : 1;
3115 u64 a10g_kx4 : 1;
3116 u64 a1g_kx : 1;
3117 u64 t : 5;
3118 u64 np : 1;
3119 u64 ack : 1;
3120 u64 rf : 1;
3121 u64 xnp_able : 1;
3122 u64 asm_dir : 1;
3123 u64 pause : 1;
3124 u64 e : 5;
3125 u64 s : 5;
3126 } s;
3127 struct cvmx_bgxx_spux_an_lp_base_s cn73xx;
3128 struct cvmx_bgxx_spux_an_lp_base_s cn78xx;
3129 struct cvmx_bgxx_spux_an_lp_base_s cn78xxp1;
3130 struct cvmx_bgxx_spux_an_lp_base_s cnf75xx;
3131};
3132
3133typedef union cvmx_bgxx_spux_an_lp_base cvmx_bgxx_spux_an_lp_base_t;
3134
3135/**
3136 * cvmx_bgx#_spu#_an_lp_xnp
3137 *
3138 * This register captures the contents of the latest next page code word received from the link
3139 * partner during autonegotiation, if any. See section 802.3 section 73.7.7 for details.
3140 */
3141union cvmx_bgxx_spux_an_lp_xnp {
3142 u64 u64;
3143 struct cvmx_bgxx_spux_an_lp_xnp_s {
3144 u64 reserved_48_63 : 16;
3145 u64 u : 32;
3146 u64 np : 1;
3147 u64 ack : 1;
3148 u64 mp : 1;
3149 u64 ack2 : 1;
3150 u64 toggle : 1;
3151 u64 m_u : 11;
3152 } s;
3153 struct cvmx_bgxx_spux_an_lp_xnp_s cn73xx;
3154 struct cvmx_bgxx_spux_an_lp_xnp_s cn78xx;
3155 struct cvmx_bgxx_spux_an_lp_xnp_s cn78xxp1;
3156 struct cvmx_bgxx_spux_an_lp_xnp_s cnf75xx;
3157};
3158
3159typedef union cvmx_bgxx_spux_an_lp_xnp cvmx_bgxx_spux_an_lp_xnp_t;
3160
3161/**
3162 * cvmx_bgx#_spu#_an_status
3163 */
3164union cvmx_bgxx_spux_an_status {
3165 u64 u64;
3166 struct cvmx_bgxx_spux_an_status_s {
3167 u64 reserved_10_63 : 54;
3168 u64 prl_flt : 1;
3169 u64 reserved_8_8 : 1;
3170 u64 xnp_stat : 1;
3171 u64 page_rx : 1;
3172 u64 an_complete : 1;
3173 u64 rmt_flt : 1;
3174 u64 an_able : 1;
3175 u64 link_status : 1;
3176 u64 reserved_1_1 : 1;
3177 u64 lp_an_able : 1;
3178 } s;
3179 struct cvmx_bgxx_spux_an_status_s cn73xx;
3180 struct cvmx_bgxx_spux_an_status_s cn78xx;
3181 struct cvmx_bgxx_spux_an_status_s cn78xxp1;
3182 struct cvmx_bgxx_spux_an_status_s cnf75xx;
3183};
3184
3185typedef union cvmx_bgxx_spux_an_status cvmx_bgxx_spux_an_status_t;
3186
3187/**
3188 * cvmx_bgx#_spu#_an_xnp_tx
3189 *
3190 * Software programs this register with the contents of the AN message next page or unformatted
3191 * next page link code word to be transmitted during autonegotiation. Next page exchange occurs
3192 * after the base link code words have been exchanged if either end of the link segment sets the
3193 * NP bit to 1, indicating that it has at least one next page to send. Once initiated, next page
3194 * exchange continues until both ends of the link segment set their NP bits to 0. See section
3195 * 802.3 section 73.7.7 for details.
3196 */
3197union cvmx_bgxx_spux_an_xnp_tx {
3198 u64 u64;
3199 struct cvmx_bgxx_spux_an_xnp_tx_s {
3200 u64 reserved_48_63 : 16;
3201 u64 u : 32;
3202 u64 np : 1;
3203 u64 ack : 1;
3204 u64 mp : 1;
3205 u64 ack2 : 1;
3206 u64 toggle : 1;
3207 u64 m_u : 11;
3208 } s;
3209 struct cvmx_bgxx_spux_an_xnp_tx_s cn73xx;
3210 struct cvmx_bgxx_spux_an_xnp_tx_s cn78xx;
3211 struct cvmx_bgxx_spux_an_xnp_tx_s cn78xxp1;
3212 struct cvmx_bgxx_spux_an_xnp_tx_s cnf75xx;
3213};
3214
3215typedef union cvmx_bgxx_spux_an_xnp_tx cvmx_bgxx_spux_an_xnp_tx_t;
3216
3217/**
3218 * cvmx_bgx#_spu#_br_algn_status
3219 *
3220 * This register implements the IEEE 802.3 multilane BASE-R PCS alignment status 1-4 registers
3221 * (3.50-3.53). It is valid only when the LPCS type is 40GBASE-R
3222 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS
3223 * types. IEEE 802.3 bits that are not applicable to 40GBASE-R (e.g. status bits for PCS lanes
3224 * 19-4) are not implemented and marked as reserved. PCS lanes 3-0 are valid and are mapped to
3225 * physical SerDes lanes based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS].
3226 */
3227union cvmx_bgxx_spux_br_algn_status {
3228 u64 u64;
3229 struct cvmx_bgxx_spux_br_algn_status_s {
3230 u64 reserved_36_63 : 28;
3231 u64 marker_lock : 4;
3232 u64 reserved_13_31 : 19;
3233 u64 alignd : 1;
3234 u64 reserved_4_11 : 8;
3235 u64 block_lock : 4;
3236 } s;
3237 struct cvmx_bgxx_spux_br_algn_status_s cn73xx;
3238 struct cvmx_bgxx_spux_br_algn_status_s cn78xx;
3239 struct cvmx_bgxx_spux_br_algn_status_s cn78xxp1;
3240 struct cvmx_bgxx_spux_br_algn_status_s cnf75xx;
3241};
3242
3243typedef union cvmx_bgxx_spux_br_algn_status cvmx_bgxx_spux_br_algn_status_t;
3244
3245/**
3246 * cvmx_bgx#_spu#_br_bip_err_cnt
3247 *
3248 * This register implements the IEEE 802.3 BIP error-counter registers for PCS lanes 0-3
3249 * (3.200-3.203). It is valid only when the LPCS type is 40GBASE-R
3250 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS
3251 * types. The counters are indexed by the RX PCS lane number based on the Alignment Marker
3252 * detected on each lane and captured in BGX()_SPU()_BR_LANE_MAP. Each counter counts the
3253 * BIP errors for its PCS lane, and is held at all ones in case of overflow. The counters are
3254 * reset to all 0s when this register is read by software.
3255 *
3256 * The reset operation takes precedence over the increment operation; if the register is read on
3257 * the same clock cycle as an increment operation, the counter is reset to all 0s and the
3258 * increment operation is lost. The counters are writable for test purposes, rather than read-
3259 * only as specified in IEEE 802.3.
3260 */
3261union cvmx_bgxx_spux_br_bip_err_cnt {
3262 u64 u64;
3263 struct cvmx_bgxx_spux_br_bip_err_cnt_s {
3264 u64 bip_err_cnt_ln3 : 16;
3265 u64 bip_err_cnt_ln2 : 16;
3266 u64 bip_err_cnt_ln1 : 16;
3267 u64 bip_err_cnt_ln0 : 16;
3268 } s;
3269 struct cvmx_bgxx_spux_br_bip_err_cnt_s cn73xx;
3270 struct cvmx_bgxx_spux_br_bip_err_cnt_s cn78xx;
3271 struct cvmx_bgxx_spux_br_bip_err_cnt_s cn78xxp1;
3272 struct cvmx_bgxx_spux_br_bip_err_cnt_s cnf75xx;
3273};
3274
3275typedef union cvmx_bgxx_spux_br_bip_err_cnt cvmx_bgxx_spux_br_bip_err_cnt_t;
3276
3277/**
3278 * cvmx_bgx#_spu#_br_lane_map
3279 *
3280 * This register implements the IEEE 802.3 lane 0-3 mapping registers (3.400-3.403). It is valid
3281 * only when the LPCS type is 40GBASE-R (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always
3282 * returns 0x0 for all other LPCS types. The LNx_MAPPING field for each programmed PCS lane
3283 * (called service interface in 802.3ba-2010) is valid when that lane has achieved alignment
3284 * marker lock on the receive side (i.e. the associated
3285 * BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), and is invalid otherwise. When valid, it
3286 * returns the actual detected receive PCS lane number based on the received alignment marker
3287 * contents received on that service interface.
3288 *
3289 * The mapping is flexible because IEEE 802.3 allows multilane BASE-R receive lanes to be re-
3290 * ordered. Note that for the transmit side, each PCS lane is mapped to a physical SerDes lane
3291 * based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS]. For the receive side,
3292 * BGX()_CMR()_CONFIG[LANE_TO_SDS] specifies the service interface to physical SerDes
3293 * lane mapping, and this register specifies the service interface to PCS lane mapping.
3294 */
3295union cvmx_bgxx_spux_br_lane_map {
3296 u64 u64;
3297 struct cvmx_bgxx_spux_br_lane_map_s {
3298 u64 reserved_54_63 : 10;
3299 u64 ln3_mapping : 6;
3300 u64 reserved_38_47 : 10;
3301 u64 ln2_mapping : 6;
3302 u64 reserved_22_31 : 10;
3303 u64 ln1_mapping : 6;
3304 u64 reserved_6_15 : 10;
3305 u64 ln0_mapping : 6;
3306 } s;
3307 struct cvmx_bgxx_spux_br_lane_map_s cn73xx;
3308 struct cvmx_bgxx_spux_br_lane_map_s cn78xx;
3309 struct cvmx_bgxx_spux_br_lane_map_s cn78xxp1;
3310 struct cvmx_bgxx_spux_br_lane_map_s cnf75xx;
3311};
3312
3313typedef union cvmx_bgxx_spux_br_lane_map cvmx_bgxx_spux_br_lane_map_t;
3314
3315/**
3316 * cvmx_bgx#_spu#_br_pmd_control
3317 */
3318union cvmx_bgxx_spux_br_pmd_control {
3319 u64 u64;
3320 struct cvmx_bgxx_spux_br_pmd_control_s {
3321 u64 reserved_2_63 : 62;
3322 u64 train_en : 1;
3323 u64 train_restart : 1;
3324 } s;
3325 struct cvmx_bgxx_spux_br_pmd_control_s cn73xx;
3326 struct cvmx_bgxx_spux_br_pmd_control_s cn78xx;
3327 struct cvmx_bgxx_spux_br_pmd_control_s cn78xxp1;
3328 struct cvmx_bgxx_spux_br_pmd_control_s cnf75xx;
3329};
3330
3331typedef union cvmx_bgxx_spux_br_pmd_control cvmx_bgxx_spux_br_pmd_control_t;
3332
3333/**
3334 * cvmx_bgx#_spu#_br_pmd_ld_cup
3335 *
3336 * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when
3337 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
3338 * and MDIO registers 1.1300-1.1303 for 40GBASE-R (when
3339 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
3340 * When link training
3341 * is in progress, each field reflects the contents of the coefficient update field in the
3342 * associated lane's outgoing training frame. The fields in this register are read/write even
3343 * though they are specified as read-only in 802.3.
3344 *
3345 * If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must be updated
3346 * by software during link training and hardware updates are disabled. If
3347 * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically
3348 * updated by hardware, and it should not be written by software. The lane fields in this
3349 * register are indexed by logical PCS lane ID.
3350 *
3351 * The lane 0 field (LN0_*) is valid for both
3352 * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for
3353 * 40GBASE-R.
3354 */
3355union cvmx_bgxx_spux_br_pmd_ld_cup {
3356 u64 u64;
3357 struct cvmx_bgxx_spux_br_pmd_ld_cup_s {
3358 u64 ln3_cup : 16;
3359 u64 ln2_cup : 16;
3360 u64 ln1_cup : 16;
3361 u64 ln0_cup : 16;
3362 } s;
3363 struct cvmx_bgxx_spux_br_pmd_ld_cup_s cn73xx;
3364 struct cvmx_bgxx_spux_br_pmd_ld_cup_s cn78xx;
3365 struct cvmx_bgxx_spux_br_pmd_ld_cup_s cn78xxp1;
3366 struct cvmx_bgxx_spux_br_pmd_ld_cup_s cnf75xx;
3367};
3368
3369typedef union cvmx_bgxx_spux_br_pmd_ld_cup cvmx_bgxx_spux_br_pmd_ld_cup_t;
3370
3371/**
3372 * cvmx_bgx#_spu#_br_pmd_ld_rep
3373 *
3374 * This register implements 802.3 MDIO register 1.154 for 10GBASE-R (when
3375 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R) and MDIO registers 1.1400-1.1403 for 40GBASE-R
3376 * (when BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of
3377 * training. Each field
3378 * reflects the contents of the status report field in the associated lane's outgoing training
3379 * frame. The fields in this register are read/write even though they are specified as read-only
3380 * in 802.3. If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must
3381 * be updated by software during link training and hardware updates are disabled. If
3382 * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically
3383 * updated by hardware, and it should not be written by software. The lane fields in this
3384 * register are indexed by logical PCS lane ID.
3385 *
3386 * The lane 0 field (LN0_*) is valid for both
3387 * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for
3388 * 40GBASE-R.
3389 */
3390union cvmx_bgxx_spux_br_pmd_ld_rep {
3391 u64 u64;
3392 struct cvmx_bgxx_spux_br_pmd_ld_rep_s {
3393 u64 ln3_rep : 16;
3394 u64 ln2_rep : 16;
3395 u64 ln1_rep : 16;
3396 u64 ln0_rep : 16;
3397 } s;
3398 struct cvmx_bgxx_spux_br_pmd_ld_rep_s cn73xx;
3399 struct cvmx_bgxx_spux_br_pmd_ld_rep_s cn78xx;
3400 struct cvmx_bgxx_spux_br_pmd_ld_rep_s cn78xxp1;
3401 struct cvmx_bgxx_spux_br_pmd_ld_rep_s cnf75xx;
3402};
3403
3404typedef union cvmx_bgxx_spux_br_pmd_ld_rep cvmx_bgxx_spux_br_pmd_ld_rep_t;
3405
3406/**
3407 * cvmx_bgx#_spu#_br_pmd_lp_cup
3408 *
3409 * This register implements 802.3 MDIO register 1.152 for 10GBASE-R (when
3410 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
3411 * and MDIO registers 1.1100-1.1103 for 40GBASE-R (when
3412 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
3413 * Each field reflects
3414 * the contents of the coefficient update field in the lane's most recently received training
3415 * frame. This register should not be written when link training is enabled, i.e. when
3416 * BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set. The lane fields in this register are indexed by
3417 * logical PCS lane ID.
3418 *
3419 * The lane 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields
3420 * (LN1_*, LN2_*, LN3_*) are only valid for 40GBASE-R.
3421 */
3422union cvmx_bgxx_spux_br_pmd_lp_cup {
3423 u64 u64;
3424 struct cvmx_bgxx_spux_br_pmd_lp_cup_s {
3425 u64 ln3_cup : 16;
3426 u64 ln2_cup : 16;
3427 u64 ln1_cup : 16;
3428 u64 ln0_cup : 16;
3429 } s;
3430 struct cvmx_bgxx_spux_br_pmd_lp_cup_s cn73xx;
3431 struct cvmx_bgxx_spux_br_pmd_lp_cup_s cn78xx;
3432 struct cvmx_bgxx_spux_br_pmd_lp_cup_s cn78xxp1;
3433 struct cvmx_bgxx_spux_br_pmd_lp_cup_s cnf75xx;
3434};
3435
3436typedef union cvmx_bgxx_spux_br_pmd_lp_cup cvmx_bgxx_spux_br_pmd_lp_cup_t;
3437
3438/**
3439 * cvmx_bgx#_spu#_br_pmd_lp_rep
3440 *
3441 * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when
3442 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
3443 * and MDIO registers 1.1200-1.1203 for 40GBASE-R (when
3444 * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
3445 * Each field reflects
3446 * the contents of the status report field in the associated lane's most recently received
3447 * training frame. The lane fields in this register are indexed by logical PCS lane ID.
3448 *
3449 * The lane
3450 * 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*,
3451 * LN3_*) are only valid for 40GBASE-R.
3452 */
3453union cvmx_bgxx_spux_br_pmd_lp_rep {
3454 u64 u64;
3455 struct cvmx_bgxx_spux_br_pmd_lp_rep_s {
3456 u64 ln3_rep : 16;
3457 u64 ln2_rep : 16;
3458 u64 ln1_rep : 16;
3459 u64 ln0_rep : 16;
3460 } s;
3461 struct cvmx_bgxx_spux_br_pmd_lp_rep_s cn73xx;
3462 struct cvmx_bgxx_spux_br_pmd_lp_rep_s cn78xx;
3463 struct cvmx_bgxx_spux_br_pmd_lp_rep_s cn78xxp1;
3464 struct cvmx_bgxx_spux_br_pmd_lp_rep_s cnf75xx;
3465};
3466
3467typedef union cvmx_bgxx_spux_br_pmd_lp_rep cvmx_bgxx_spux_br_pmd_lp_rep_t;
3468
3469/**
3470 * cvmx_bgx#_spu#_br_pmd_status
3471 *
3472 * The lane fields in this register are indexed by logical PCS lane ID. The lane 0 field (LN0_*)
3473 * is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only
3474 * valid for 40GBASE-R.
3475 */
3476union cvmx_bgxx_spux_br_pmd_status {
3477 u64 u64;
3478 struct cvmx_bgxx_spux_br_pmd_status_s {
3479 u64 reserved_16_63 : 48;
3480 u64 ln3_train_status : 4;
3481 u64 ln2_train_status : 4;
3482 u64 ln1_train_status : 4;
3483 u64 ln0_train_status : 4;
3484 } s;
3485 struct cvmx_bgxx_spux_br_pmd_status_s cn73xx;
3486 struct cvmx_bgxx_spux_br_pmd_status_s cn78xx;
3487 struct cvmx_bgxx_spux_br_pmd_status_s cn78xxp1;
3488 struct cvmx_bgxx_spux_br_pmd_status_s cnf75xx;
3489};
3490
3491typedef union cvmx_bgxx_spux_br_pmd_status cvmx_bgxx_spux_br_pmd_status_t;
3492
3493/**
3494 * cvmx_bgx#_spu#_br_status1
3495 */
3496union cvmx_bgxx_spux_br_status1 {
3497 u64 u64;
3498 struct cvmx_bgxx_spux_br_status1_s {
3499 u64 reserved_13_63 : 51;
3500 u64 rcv_lnk : 1;
3501 u64 reserved_4_11 : 8;
3502 u64 prbs9 : 1;
3503 u64 prbs31 : 1;
3504 u64 hi_ber : 1;
3505 u64 blk_lock : 1;
3506 } s;
3507 struct cvmx_bgxx_spux_br_status1_s cn73xx;
3508 struct cvmx_bgxx_spux_br_status1_s cn78xx;
3509 struct cvmx_bgxx_spux_br_status1_s cn78xxp1;
3510 struct cvmx_bgxx_spux_br_status1_s cnf75xx;
3511};
3512
3513typedef union cvmx_bgxx_spux_br_status1 cvmx_bgxx_spux_br_status1_t;
3514
3515/**
3516 * cvmx_bgx#_spu#_br_status2
3517 *
3518 * This register implements a combination of the following IEEE 802.3 registers:
3519 * * BASE-R PCS status 2 (MDIO address 3.33).
3520 * * BASE-R BER high-order counter (MDIO address 3.44).
3521 * * Errored-blocks high-order counter (MDIO address 3.45).
3522 *
3523 * Note that the relative locations of some fields have been moved from IEEE 802.3 in order to
3524 * make the register layout more software friendly: the BER counter high-order and low-order bits
3525 * from sections 3.44 and 3.33 have been combined into the contiguous, 22-bit [BER_CNT] field;
3526 * likewise, the errored-blocks counter high-order and low-order bits from section 3.45 have been
3527 * combined into the contiguous, 22-bit [ERR_BLKS] field.
3528 */
3529union cvmx_bgxx_spux_br_status2 {
3530 u64 u64;
3531 struct cvmx_bgxx_spux_br_status2_s {
3532 u64 reserved_62_63 : 2;
3533 u64 err_blks : 22;
3534 u64 reserved_38_39 : 2;
3535 u64 ber_cnt : 22;
3536 u64 latched_lock : 1;
3537 u64 latched_ber : 1;
3538 u64 reserved_0_13 : 14;
3539 } s;
3540 struct cvmx_bgxx_spux_br_status2_s cn73xx;
3541 struct cvmx_bgxx_spux_br_status2_s cn78xx;
3542 struct cvmx_bgxx_spux_br_status2_s cn78xxp1;
3543 struct cvmx_bgxx_spux_br_status2_s cnf75xx;
3544};
3545
3546typedef union cvmx_bgxx_spux_br_status2 cvmx_bgxx_spux_br_status2_t;
3547
3548/**
3549 * cvmx_bgx#_spu#_br_tp_control
3550 *
3551 * Refer to the test pattern methodology described in 802.3 sections 49.2.8 and 82.2.10.
3552 *
3553 */
3554union cvmx_bgxx_spux_br_tp_control {
3555 u64 u64;
3556 struct cvmx_bgxx_spux_br_tp_control_s {
3557 u64 reserved_8_63 : 56;
3558 u64 scramble_tp : 1;
3559 u64 prbs9_tx : 1;
3560 u64 prbs31_rx : 1;
3561 u64 prbs31_tx : 1;
3562 u64 tx_tp_en : 1;
3563 u64 rx_tp_en : 1;
3564 u64 tp_sel : 1;
3565 u64 dp_sel : 1;
3566 } s;
3567 struct cvmx_bgxx_spux_br_tp_control_s cn73xx;
3568 struct cvmx_bgxx_spux_br_tp_control_s cn78xx;
3569 struct cvmx_bgxx_spux_br_tp_control_s cn78xxp1;
3570 struct cvmx_bgxx_spux_br_tp_control_s cnf75xx;
3571};
3572
3573typedef union cvmx_bgxx_spux_br_tp_control cvmx_bgxx_spux_br_tp_control_t;
3574
3575/**
3576 * cvmx_bgx#_spu#_br_tp_err_cnt
3577 *
3578 * This register provides the BASE-R PCS test-pattern error counter.
3579 *
3580 */
3581union cvmx_bgxx_spux_br_tp_err_cnt {
3582 u64 u64;
3583 struct cvmx_bgxx_spux_br_tp_err_cnt_s {
3584 u64 reserved_16_63 : 48;
3585 u64 err_cnt : 16;
3586 } s;
3587 struct cvmx_bgxx_spux_br_tp_err_cnt_s cn73xx;
3588 struct cvmx_bgxx_spux_br_tp_err_cnt_s cn78xx;
3589 struct cvmx_bgxx_spux_br_tp_err_cnt_s cn78xxp1;
3590 struct cvmx_bgxx_spux_br_tp_err_cnt_s cnf75xx;
3591};
3592
3593typedef union cvmx_bgxx_spux_br_tp_err_cnt cvmx_bgxx_spux_br_tp_err_cnt_t;
3594
3595/**
3596 * cvmx_bgx#_spu#_bx_status
3597 */
3598union cvmx_bgxx_spux_bx_status {
3599 u64 u64;
3600 struct cvmx_bgxx_spux_bx_status_s {
3601 u64 reserved_13_63 : 51;
3602 u64 alignd : 1;
3603 u64 pattst : 1;
3604 u64 reserved_4_10 : 7;
3605 u64 lsync : 4;
3606 } s;
3607 struct cvmx_bgxx_spux_bx_status_s cn73xx;
3608 struct cvmx_bgxx_spux_bx_status_s cn78xx;
3609 struct cvmx_bgxx_spux_bx_status_s cn78xxp1;
3610 struct cvmx_bgxx_spux_bx_status_s cnf75xx;
3611};
3612
3613typedef union cvmx_bgxx_spux_bx_status cvmx_bgxx_spux_bx_status_t;
3614
3615/**
3616 * cvmx_bgx#_spu#_control1
3617 */
3618union cvmx_bgxx_spux_control1 {
3619 u64 u64;
3620 struct cvmx_bgxx_spux_control1_s {
3621 u64 reserved_16_63 : 48;
3622 u64 reset : 1;
3623 u64 loopbck : 1;
3624 u64 spdsel1 : 1;
3625 u64 reserved_12_12 : 1;
3626 u64 lo_pwr : 1;
3627 u64 reserved_7_10 : 4;
3628 u64 spdsel0 : 1;
3629 u64 spd : 4;
3630 u64 reserved_0_1 : 2;
3631 } s;
3632 struct cvmx_bgxx_spux_control1_s cn73xx;
3633 struct cvmx_bgxx_spux_control1_s cn78xx;
3634 struct cvmx_bgxx_spux_control1_s cn78xxp1;
3635 struct cvmx_bgxx_spux_control1_s cnf75xx;
3636};
3637
3638typedef union cvmx_bgxx_spux_control1 cvmx_bgxx_spux_control1_t;
3639
3640/**
3641 * cvmx_bgx#_spu#_control2
3642 */
3643union cvmx_bgxx_spux_control2 {
3644 u64 u64;
3645 struct cvmx_bgxx_spux_control2_s {
3646 u64 reserved_3_63 : 61;
3647 u64 pcs_type : 3;
3648 } s;
3649 struct cvmx_bgxx_spux_control2_s cn73xx;
3650 struct cvmx_bgxx_spux_control2_s cn78xx;
3651 struct cvmx_bgxx_spux_control2_s cn78xxp1;
3652 struct cvmx_bgxx_spux_control2_s cnf75xx;
3653};
3654
3655typedef union cvmx_bgxx_spux_control2 cvmx_bgxx_spux_control2_t;
3656
3657/**
3658 * cvmx_bgx#_spu#_fec_abil
3659 */
3660union cvmx_bgxx_spux_fec_abil {
3661 u64 u64;
3662 struct cvmx_bgxx_spux_fec_abil_s {
3663 u64 reserved_2_63 : 62;
3664 u64 err_abil : 1;
3665 u64 fec_abil : 1;
3666 } s;
3667 struct cvmx_bgxx_spux_fec_abil_s cn73xx;
3668 struct cvmx_bgxx_spux_fec_abil_s cn78xx;
3669 struct cvmx_bgxx_spux_fec_abil_s cn78xxp1;
3670 struct cvmx_bgxx_spux_fec_abil_s cnf75xx;
3671};
3672
3673typedef union cvmx_bgxx_spux_fec_abil cvmx_bgxx_spux_fec_abil_t;
3674
3675/**
3676 * cvmx_bgx#_spu#_fec_control
3677 */
3678union cvmx_bgxx_spux_fec_control {
3679 u64 u64;
3680 struct cvmx_bgxx_spux_fec_control_s {
3681 u64 reserved_2_63 : 62;
3682 u64 err_en : 1;
3683 u64 fec_en : 1;
3684 } s;
3685 struct cvmx_bgxx_spux_fec_control_s cn73xx;
3686 struct cvmx_bgxx_spux_fec_control_s cn78xx;
3687 struct cvmx_bgxx_spux_fec_control_s cn78xxp1;
3688 struct cvmx_bgxx_spux_fec_control_s cnf75xx;
3689};
3690
3691typedef union cvmx_bgxx_spux_fec_control cvmx_bgxx_spux_fec_control_t;
3692
3693/**
3694 * cvmx_bgx#_spu#_fec_corr_blks01
3695 *
3696 * This register is valid only when the LPCS type is BASE-R
3697 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are
3698 * defined in IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a
3699 * corrected FEC block, i.e. an FEC block that has been received with invalid parity on the
3700 * associated PCS lane and has been corrected by the FEC decoder. The counter is reset to all 0s
3701 * when the register is read, and held at all 1s in case of overflow.
3702 *
3703 * The reset operation takes precedence over the increment operation; if the register is read on
3704 * the same clock cycle as an increment operation, the counter is reset to all 0s and the
3705 * increment operation is lost. The counters are writable for test purposes, rather than read-
3706 * only as specified in IEEE 802.3.
3707 */
3708union cvmx_bgxx_spux_fec_corr_blks01 {
3709 u64 u64;
3710 struct cvmx_bgxx_spux_fec_corr_blks01_s {
3711 u64 ln1_corr_blks : 32;
3712 u64 ln0_corr_blks : 32;
3713 } s;
3714 struct cvmx_bgxx_spux_fec_corr_blks01_s cn73xx;
3715 struct cvmx_bgxx_spux_fec_corr_blks01_s cn78xx;
3716 struct cvmx_bgxx_spux_fec_corr_blks01_s cn78xxp1;
3717 struct cvmx_bgxx_spux_fec_corr_blks01_s cnf75xx;
3718};
3719
3720typedef union cvmx_bgxx_spux_fec_corr_blks01 cvmx_bgxx_spux_fec_corr_blks01_t;
3721
3722/**
3723 * cvmx_bgx#_spu#_fec_corr_blks23
3724 *
3725 * This register is valid only when the LPCS type is 40GBASE-R
3726 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC corrected-block counters are defined in
3727 * IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a corrected FEC
3728 * block, i.e. an FEC block that has been received with invalid parity on the associated PCS lane
3729 * and has been corrected by the FEC decoder. The counter is reset to all 0s when the register is
3730 * read, and held at all 1s in case of overflow.
3731 *
3732 * The reset operation takes precedence over the increment operation; if the register is read on
3733 * the same clock cycle as an increment operation, the counter is reset to all 0s and the
3734 * increment operation is lost. The counters are writable for test purposes, rather than read-
3735 * only as specified in IEEE 802.3.
3736 */
3737union cvmx_bgxx_spux_fec_corr_blks23 {
3738 u64 u64;
3739 struct cvmx_bgxx_spux_fec_corr_blks23_s {
3740 u64 ln3_corr_blks : 32;
3741 u64 ln2_corr_blks : 32;
3742 } s;
3743 struct cvmx_bgxx_spux_fec_corr_blks23_s cn73xx;
3744 struct cvmx_bgxx_spux_fec_corr_blks23_s cn78xx;
3745 struct cvmx_bgxx_spux_fec_corr_blks23_s cn78xxp1;
3746 struct cvmx_bgxx_spux_fec_corr_blks23_s cnf75xx;
3747};
3748
3749typedef union cvmx_bgxx_spux_fec_corr_blks23 cvmx_bgxx_spux_fec_corr_blks23_t;
3750
3751/**
3752 * cvmx_bgx#_spu#_fec_uncorr_blks01
3753 *
3754 * This register is valid only when the LPCS type is BASE-R
3755 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are
3756 * defined in IEEE 802.3 section 74.8.4.2. Each uncorrected-blocks counter increments by 1 for an
3757 * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the
3758 * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all
3759 * 0s when the register is read, and held at all 1s in case of overflow.
3760 *
3761 * The reset operation takes precedence over the increment operation; if the register is read on
3762 * the same clock cycle as an increment operation, the counter is reset to all 0s and the
3763 * increment operation is lost. The counters are writable for test purposes, rather than read-
3764 * only as specified in IEEE 802.3.
3765 */
3766union cvmx_bgxx_spux_fec_uncorr_blks01 {
3767 u64 u64;
3768 struct cvmx_bgxx_spux_fec_uncorr_blks01_s {
3769 u64 ln1_uncorr_blks : 32;
3770 u64 ln0_uncorr_blks : 32;
3771 } s;
3772 struct cvmx_bgxx_spux_fec_uncorr_blks01_s cn73xx;
3773 struct cvmx_bgxx_spux_fec_uncorr_blks01_s cn78xx;
3774 struct cvmx_bgxx_spux_fec_uncorr_blks01_s cn78xxp1;
3775 struct cvmx_bgxx_spux_fec_uncorr_blks01_s cnf75xx;
3776};
3777
3778typedef union cvmx_bgxx_spux_fec_uncorr_blks01 cvmx_bgxx_spux_fec_uncorr_blks01_t;
3779
3780/**
3781 * cvmx_bgx#_spu#_fec_uncorr_blks23
3782 *
3783 * This register is valid only when the LPCS type is 40GBASE-R
3784 * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC uncorrected-block counters are defined
3785 * in IEEE 802.3 section 74.8.4.2. Each corrected-blocks counter increments by 1 for an
3786 * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the
3787 * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all
3788 * 0s when the register is read, and held at all 1s in case of overflow.
3789 *
3790 * The reset operation takes precedence over the increment operation; if the register is read on
3791 * the same clock cycle as an increment operation, the counter is reset to all 0s and the
3792 * increment operation is lost. The counters are writable for test purposes, rather than read-
3793 * only as specified in IEEE 802.3.
3794 */
3795union cvmx_bgxx_spux_fec_uncorr_blks23 {
3796 u64 u64;
3797 struct cvmx_bgxx_spux_fec_uncorr_blks23_s {
3798 u64 ln3_uncorr_blks : 32;
3799 u64 ln2_uncorr_blks : 32;
3800 } s;
3801 struct cvmx_bgxx_spux_fec_uncorr_blks23_s cn73xx;
3802 struct cvmx_bgxx_spux_fec_uncorr_blks23_s cn78xx;
3803 struct cvmx_bgxx_spux_fec_uncorr_blks23_s cn78xxp1;
3804 struct cvmx_bgxx_spux_fec_uncorr_blks23_s cnf75xx;
3805};
3806
3807typedef union cvmx_bgxx_spux_fec_uncorr_blks23 cvmx_bgxx_spux_fec_uncorr_blks23_t;
3808
3809/**
3810 * cvmx_bgx#_spu#_int
3811 */
3812union cvmx_bgxx_spux_int {
3813 u64 u64;
3814 struct cvmx_bgxx_spux_int_s {
3815 u64 reserved_15_63 : 49;
3816 u64 training_failure : 1;
3817 u64 training_done : 1;
3818 u64 an_complete : 1;
3819 u64 an_link_good : 1;
3820 u64 an_page_rx : 1;
3821 u64 fec_uncorr : 1;
3822 u64 fec_corr : 1;
3823 u64 bip_err : 1;
3824 u64 dbg_sync : 1;
3825 u64 algnlos : 1;
3826 u64 synlos : 1;
3827 u64 bitlckls : 1;
3828 u64 err_blk : 1;
3829 u64 rx_link_down : 1;
3830 u64 rx_link_up : 1;
3831 } s;
3832 struct cvmx_bgxx_spux_int_s cn73xx;
3833 struct cvmx_bgxx_spux_int_s cn78xx;
3834 struct cvmx_bgxx_spux_int_s cn78xxp1;
3835 struct cvmx_bgxx_spux_int_s cnf75xx;
3836};
3837
3838typedef union cvmx_bgxx_spux_int cvmx_bgxx_spux_int_t;
3839
3840/**
3841 * cvmx_bgx#_spu#_lpcs_states
3842 */
3843union cvmx_bgxx_spux_lpcs_states {
3844 u64 u64;
3845 struct cvmx_bgxx_spux_lpcs_states_s {
3846 u64 reserved_15_63 : 49;
3847 u64 br_rx_sm : 3;
3848 u64 reserved_10_11 : 2;
3849 u64 bx_rx_sm : 2;
3850 u64 deskew_am_found : 4;
3851 u64 reserved_3_3 : 1;
3852 u64 deskew_sm : 3;
3853 } s;
3854 struct cvmx_bgxx_spux_lpcs_states_s cn73xx;
3855 struct cvmx_bgxx_spux_lpcs_states_s cn78xx;
3856 struct cvmx_bgxx_spux_lpcs_states_s cn78xxp1;
3857 struct cvmx_bgxx_spux_lpcs_states_s cnf75xx;
3858};
3859
3860typedef union cvmx_bgxx_spux_lpcs_states cvmx_bgxx_spux_lpcs_states_t;
3861
3862/**
3863 * cvmx_bgx#_spu#_misc_control
3864 *
3865 * "* RX logical PCS lane polarity vector <3:0> = [XOR_RXPLRT]<3:0> ^ [4[[RXPLRT]]].
3866 * * TX logical PCS lane polarity vector <3:0> = [XOR_TXPLRT]<3:0> ^ [4[[TXPLRT]]].
3867 *
3868 * In short, keep [RXPLRT] and [TXPLRT] cleared, and use [XOR_RXPLRT] and [XOR_TXPLRT] fields to
3869 * define
3870 * the polarity per logical PCS lane. Only bit 0 of vector is used for 10GBASE-R, and only bits
3871 * - 1:0 of vector are used for RXAUI."
3872 */
3873union cvmx_bgxx_spux_misc_control {
3874 u64 u64;
3875 struct cvmx_bgxx_spux_misc_control_s {
3876 u64 reserved_13_63 : 51;
3877 u64 rx_packet_dis : 1;
3878 u64 skip_after_term : 1;
3879 u64 intlv_rdisp : 1;
3880 u64 xor_rxplrt : 4;
3881 u64 xor_txplrt : 4;
3882 u64 rxplrt : 1;
3883 u64 txplrt : 1;
3884 } s;
3885 struct cvmx_bgxx_spux_misc_control_s cn73xx;
3886 struct cvmx_bgxx_spux_misc_control_s cn78xx;
3887 struct cvmx_bgxx_spux_misc_control_s cn78xxp1;
3888 struct cvmx_bgxx_spux_misc_control_s cnf75xx;
3889};
3890
3891typedef union cvmx_bgxx_spux_misc_control cvmx_bgxx_spux_misc_control_t;
3892
3893/**
3894 * cvmx_bgx#_spu#_spd_abil
3895 */
3896union cvmx_bgxx_spux_spd_abil {
3897 u64 u64;
3898 struct cvmx_bgxx_spux_spd_abil_s {
3899 u64 reserved_4_63 : 60;
3900 u64 hundredgb : 1;
3901 u64 fortygb : 1;
3902 u64 tenpasst : 1;
3903 u64 tengb : 1;
3904 } s;
3905 struct cvmx_bgxx_spux_spd_abil_s cn73xx;
3906 struct cvmx_bgxx_spux_spd_abil_s cn78xx;
3907 struct cvmx_bgxx_spux_spd_abil_s cn78xxp1;
3908 struct cvmx_bgxx_spux_spd_abil_s cnf75xx;
3909};
3910
3911typedef union cvmx_bgxx_spux_spd_abil cvmx_bgxx_spux_spd_abil_t;
3912
3913/**
3914 * cvmx_bgx#_spu#_status1
3915 */
3916union cvmx_bgxx_spux_status1 {
3917 u64 u64;
3918 struct cvmx_bgxx_spux_status1_s {
3919 u64 reserved_8_63 : 56;
3920 u64 flt : 1;
3921 u64 reserved_3_6 : 4;
3922 u64 rcv_lnk : 1;
3923 u64 lpable : 1;
3924 u64 reserved_0_0 : 1;
3925 } s;
3926 struct cvmx_bgxx_spux_status1_s cn73xx;
3927 struct cvmx_bgxx_spux_status1_s cn78xx;
3928 struct cvmx_bgxx_spux_status1_s cn78xxp1;
3929 struct cvmx_bgxx_spux_status1_s cnf75xx;
3930};
3931
3932typedef union cvmx_bgxx_spux_status1 cvmx_bgxx_spux_status1_t;
3933
3934/**
3935 * cvmx_bgx#_spu#_status2
3936 */
3937union cvmx_bgxx_spux_status2 {
3938 u64 u64;
3939 struct cvmx_bgxx_spux_status2_s {
3940 u64 reserved_16_63 : 48;
3941 u64 dev : 2;
3942 u64 reserved_12_13 : 2;
3943 u64 xmtflt : 1;
3944 u64 rcvflt : 1;
3945 u64 reserved_6_9 : 4;
3946 u64 hundredgb_r : 1;
3947 u64 fortygb_r : 1;
3948 u64 tengb_t : 1;
3949 u64 tengb_w : 1;
3950 u64 tengb_x : 1;
3951 u64 tengb_r : 1;
3952 } s;
3953 struct cvmx_bgxx_spux_status2_s cn73xx;
3954 struct cvmx_bgxx_spux_status2_s cn78xx;
3955 struct cvmx_bgxx_spux_status2_s cn78xxp1;
3956 struct cvmx_bgxx_spux_status2_s cnf75xx;
3957};
3958
3959typedef union cvmx_bgxx_spux_status2 cvmx_bgxx_spux_status2_t;
3960
3961/**
3962 * cvmx_bgx#_spu_bist_status
3963 *
3964 * This register provides memory BIST status from the SPU receive buffer lane FIFOs.
3965 *
3966 */
3967union cvmx_bgxx_spu_bist_status {
3968 u64 u64;
3969 struct cvmx_bgxx_spu_bist_status_s {
3970 u64 reserved_4_63 : 60;
3971 u64 rx_buf_bist_status : 4;
3972 } s;
3973 struct cvmx_bgxx_spu_bist_status_s cn73xx;
3974 struct cvmx_bgxx_spu_bist_status_s cn78xx;
3975 struct cvmx_bgxx_spu_bist_status_s cn78xxp1;
3976 struct cvmx_bgxx_spu_bist_status_s cnf75xx;
3977};
3978
3979typedef union cvmx_bgxx_spu_bist_status cvmx_bgxx_spu_bist_status_t;
3980
3981/**
3982 * cvmx_bgx#_spu_dbg_control
3983 */
3984union cvmx_bgxx_spu_dbg_control {
3985 u64 u64;
3986 struct cvmx_bgxx_spu_dbg_control_s {
3987 u64 reserved_56_63 : 8;
3988 u64 ms_clk_period : 12;
3989 u64 us_clk_period : 12;
3990 u64 reserved_31_31 : 1;
3991 u64 br_ber_mon_dis : 1;
3992 u64 an_nonce_match_dis : 1;
3993 u64 timestamp_norm_dis : 1;
3994 u64 rx_buf_flip_synd : 8;
3995 u64 br_pmd_train_soft_en : 1;
3996 u64 an_arb_link_chk_en : 1;
3997 u64 rx_buf_cor_dis : 1;
3998 u64 scramble_dis : 1;
3999 u64 reserved_15_15 : 1;
4000 u64 marker_rxp : 15;
4001 } s;
4002 struct cvmx_bgxx_spu_dbg_control_s cn73xx;
4003 struct cvmx_bgxx_spu_dbg_control_s cn78xx;
4004 struct cvmx_bgxx_spu_dbg_control_s cn78xxp1;
4005 struct cvmx_bgxx_spu_dbg_control_s cnf75xx;
4006};
4007
4008typedef union cvmx_bgxx_spu_dbg_control cvmx_bgxx_spu_dbg_control_t;
4009
4010/**
4011 * cvmx_bgx#_spu_mem_int
4012 */
4013union cvmx_bgxx_spu_mem_int {
4014 u64 u64;
4015 struct cvmx_bgxx_spu_mem_int_s {
4016 u64 reserved_8_63 : 56;
4017 u64 rx_buf_sbe : 4;
4018 u64 rx_buf_dbe : 4;
4019 } s;
4020 struct cvmx_bgxx_spu_mem_int_s cn73xx;
4021 struct cvmx_bgxx_spu_mem_int_s cn78xx;
4022 struct cvmx_bgxx_spu_mem_int_s cn78xxp1;
4023 struct cvmx_bgxx_spu_mem_int_s cnf75xx;
4024};
4025
4026typedef union cvmx_bgxx_spu_mem_int cvmx_bgxx_spu_mem_int_t;
4027
4028/**
4029 * cvmx_bgx#_spu_mem_status
4030 *
4031 * This register provides memory ECC status from the SPU receive buffer lane FIFOs.
4032 *
4033 */
4034union cvmx_bgxx_spu_mem_status {
4035 u64 u64;
4036 struct cvmx_bgxx_spu_mem_status_s {
4037 u64 reserved_32_63 : 32;
4038 u64 rx_buf_ecc_synd : 32;
4039 } s;
4040 struct cvmx_bgxx_spu_mem_status_s cn73xx;
4041 struct cvmx_bgxx_spu_mem_status_s cn78xx;
4042 struct cvmx_bgxx_spu_mem_status_s cn78xxp1;
4043 struct cvmx_bgxx_spu_mem_status_s cnf75xx;
4044};
4045
4046typedef union cvmx_bgxx_spu_mem_status cvmx_bgxx_spu_mem_status_t;
4047
4048/**
4049 * cvmx_bgx#_spu_sds#_skew_status
4050 *
4051 * This register provides SerDes lane skew status. One register per physical SerDes lane.
4052 *
4053 */
4054union cvmx_bgxx_spu_sdsx_skew_status {
4055 u64 u64;
4056 struct cvmx_bgxx_spu_sdsx_skew_status_s {
4057 u64 reserved_32_63 : 32;
4058 u64 skew_status : 32;
4059 } s;
4060 struct cvmx_bgxx_spu_sdsx_skew_status_s cn73xx;
4061 struct cvmx_bgxx_spu_sdsx_skew_status_s cn78xx;
4062 struct cvmx_bgxx_spu_sdsx_skew_status_s cn78xxp1;
4063 struct cvmx_bgxx_spu_sdsx_skew_status_s cnf75xx;
4064};
4065
4066typedef union cvmx_bgxx_spu_sdsx_skew_status cvmx_bgxx_spu_sdsx_skew_status_t;
4067
4068/**
4069 * cvmx_bgx#_spu_sds#_states
4070 *
4071 * This register provides SerDes lane states. One register per physical SerDes lane.
4072 *
4073 */
4074union cvmx_bgxx_spu_sdsx_states {
4075 u64 u64;
4076 struct cvmx_bgxx_spu_sdsx_states_s {
4077 u64 reserved_52_63 : 12;
4078 u64 am_lock_invld_cnt : 2;
4079 u64 am_lock_sm : 2;
4080 u64 reserved_45_47 : 3;
4081 u64 train_sm : 3;
4082 u64 train_code_viol : 1;
4083 u64 train_frame_lock : 1;
4084 u64 train_lock_found_1st_marker : 1;
4085 u64 train_lock_bad_markers : 3;
4086 u64 reserved_35_35 : 1;
4087 u64 an_arb_sm : 3;
4088 u64 an_rx_sm : 2;
4089 u64 reserved_29_29 : 1;
4090 u64 fec_block_sync : 1;
4091 u64 fec_sync_cnt : 4;
4092 u64 reserved_23_23 : 1;
4093 u64 br_sh_invld_cnt : 7;
4094 u64 br_block_lock : 1;
4095 u64 br_sh_cnt : 11;
4096 u64 bx_sync_sm : 4;
4097 } s;
4098 struct cvmx_bgxx_spu_sdsx_states_s cn73xx;
4099 struct cvmx_bgxx_spu_sdsx_states_s cn78xx;
4100 struct cvmx_bgxx_spu_sdsx_states_s cn78xxp1;
4101 struct cvmx_bgxx_spu_sdsx_states_s cnf75xx;
4102};
4103
4104typedef union cvmx_bgxx_spu_sdsx_states cvmx_bgxx_spu_sdsx_states_t;
4105
4106#endif